Gold IP - UMC Gold IP program continues to lead the foundry indus-try in the hardening of standard...

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UMC’s advanced deep sub-micron process technologiesoffer tremendous opportunities to IC designers looking toprofit from market-leading products. However, unprec-edented design complexity, increasingly competitive mar-kets and dramatically shortened life cycles often mitigatethese opportunities. Solutions to these challenges havebecome critical.

The Gold IP program continues to lead the foundry indus-try in the hardening of standard library elements, mixedsignal and analog cores, and timing-critical cores throughits Silicon Shuttle multi-chip test wafer program. Theresults are coded in the Gold IP catalog according to thecore’s maturity in UMC silicon (Bronze=Softcore or GDS-II, Silver=Hardcore available and silicon verified,Gold=Production). As the catalog evolves, the Gold IP pro-gram continues to emphasize the “Interoperability” of IPcores, leveraging alliances with IP platform developers, de-sign service providers, and EDA companies, as well asindustry associations such as the Virtual Socket Inter-face Alliance (VSIA). The Gold IP Program continues tobring faster time-to-market and design risk mitigation toits customers.

Gold IPTM Program

UMC’s goal is to provide its customers with a vast offeringof compatible library and IP elements that can be easilyincorporated into an SOC in a “plug and play” fashion. Inorder to achieve interoperability among IPs, UMC has en-couraged all of its partners to follow a set of IP creationstandards:

1. Standardization of process: All IP cores are developedin the UMC standard mainstream process for eachtechnology node.

2. Standardization for standard cell and I/O architecture:UMC has adopted Virtual Silicon’s 0.15um and 0.13umand Faraday’s 0.13um architectures under UMC’s openarchitecture initiative for standard cell and I/O. Openarchitecture will also be offered to customers for our90nm process from UMC.

As a member of the IP Protection Development WorkingGroup (DWG) at VSIA, UMC has driven the industry stan-dard of IP tracking and identification tagging tools [VSIAstandard version 1.0 (IPP 1 1.0)].

R

Table of ContentsFree-of-Charge Libraries Non-Free Libraries Page 12IP Catalog Page 23

PLL Page 23ADC Page 25DAC Page 25ANALOG/MIXED-MODE Page 26BUS INTERFACE Page 28MICROCONTROLLER AND MICROPROCESSOR Page 31MICROPROCESSOR PERIPHERAL Page 32DSP Page 33COMMUNICATIONS Page 33CONSUMER Page 35STORAGE Page 35INTEGRATED PLATFORM Page 36DESIGN-FOR-TEST Page 36EMBEDDED NON-VOLATILE MACRO Page 37EMBEDDED SRAM MACRO Page 37EMBEDDED ARRAY Page 38MEMORY SUB-SYSTEM Page 38

Silicon Shuttle Program Page 39IP Vendor Contact Page 40

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UMC has revolutionized the foundry industry by offeringour customers comprehensive free-of-charge libraries fordesigns implemented with UMC’s advanced process tech-nologies, ranging from 0.25um to the leading edge 0.13umtechnology. UMC has partnered with leading full servicelibrary providers, Artisan Components, Faraday Technol-ogy, and Virtual Silicon Technology, to provide silicon veri-fied standard cells, I/Os, memory compilers, and PLL com-pilers.

Artisan, Faraday, and Virtual Silicon provide free basic sup-port for UMC customers for their free-of-charge library prod-ucts. Additional services can be provided by these ven-dors under a separate service agreement. These servicesinclude creating additional EDA views, re-characterizationover an extended voltage and temperature range, customdevelopments for standard cells, I/Os, and memories.

To download the Artisan libraries:http://www.artisan.com/programs/freelibrary/umc.html

To download the VST libraries:http://www.virtual-silicon.com/part/libr/lb_umc_ov.html

Free-of-Charge Libraries

Virtual Silicon 0.13um Library - High Speed (Low-K) Process

To download the Faraday libraries:http://www.faraday.com.tw/component/lib/umc_lib.html

Standard Cell552 high density standard cells9-track cell architecture, performance optimized for300~800 MHZAverage cell density of 200K gates/sq.mmMultiple drive strengthsLayout using metal 1 onlyScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timingand powerOpen architecture developers kit available

Inline and Staggered I/O400+ 3.3V I/O padsPad pitch: 70um (in-line), 35um (staggered)Multiple current drives up to 16mAInput buffer types - Pull-up/pull-down resistor, padkeeper, normal/SchmittOutput and bi-directional buffer types with slew ratecontrolSilicon proven ESD and latch-up structuresAnalog power pads, crystal padsOpen architecture developers kit available

PLL CompilerProgrammable input, output frequencies andduty cycleInput frequency range: 20 MHz - 200 MHzOutput frequency range: 50MHz - 1GHzPLL module entirely located in the I/O pad ringsDedicated analog power supply pinsBuild-in ESD and latch-up protection structures

Single Port SRAM, Dual Port SRAM, Two PortRegister File, and Diffusion ROM Compilers

Synchronous reads/writesStatic design with zero standby currentByte write capabilityRoutable over the core with higher metal layerAbility to compile to multiple aspect ratioScan and BIST support

Size

128 bit - 1 Mbit

128 bit - 256 Kbit

64 bit - 72 Kbit

128 bit - 1 Mbit

Mux

4, 8, 16, 32

2, 4, 8

4, 8, 16, 32

4, 8, 16, 32

Bit

2 - 128(Increment: 1)




Word

64 - 256K(Increment: 2X mux)




Architecture

Single PortSync. SRAM

Dual PortSync. SRAM

Two Port Sync.Register File

Diffusion ROM

Access Time (ns)

4K x 16Typical: 1.19Worst: 1.88


128 x 144Typical: 1.08Worst: 1.72


3


Virtual Silicon 0.13um Library - Standard Performance (FSG) ProcessStandard Cell

510+ high density standard cells9-track cell architecture, performance optimized for300~800 MHZAverage cell density of 200K gates/sq.mmMultiple drive strengthsLayout using metal 1 onlyScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timingand powerOpen architecture developers kit available


PLL CompilerProgrammable input, output frequencies and dutycycleInput frequency range: 20 MHz - 200 MHzOutput frequency range: 50MHz - 1GHzPLL module entirely located in the I/O pad ringsDedicated analog power supply pinsBuild-in ESD and latch-up protection structures



Size

128 bit - 1 Mbit

128 bit - 256 Kbit

64 bit - 72 Kbit

128 bit - 1 Mbit

Mux

4, 8, 16, 32

2, 4, 8

4, 8, 16, 32

4, 8, 16, 32

Bit





Word





Architecture


Dual PortSync. SRAM


Diffusion ROM

Access Time (ns)



128 x 144Typical: 1.08Worst: 1.72


4

Via2 ROM

Architecture


Single Port 2MbSync. SRAM

Dual PortSync. SRAM



Bit




1, 2, 4, 8

Mux

1, 2, 4, 8, 16

1, 2, 4, 8, 16

1, 2, 4, 8

2, 4, 8, 16

Size

4 K bit - 2 Mbit

64 bit - 512 Kbit

16 bit - 72 Kbit

256 bit - 2 Mbit4K x 16

Typical: 1.67 Worst: 2.67

Access Time (ns)

4K x 16Typical: 1.25

Worst: 2

64K x 16Typical: 3Worst: 4.8


128 x 144Typical: 1.44Worst: 2.3

128 - 128K (Increment: 2X mux)

Word





1 - 128(Increment: 1) 128 bit - 1 Mbit

Standard Cell and I/OPower supply (internal logic and I/O): 1.2V.Second power supply (I/O): 3.3V.12-track cell architecture; Cell high =4.8um.X grid = 0.4um, Y grid = 0.4um.Very High speed: gate delay = 17.0ps/stage @ 1.2V,F.O. = 1.Power Consumption: 0.012µW/Gate/MHz @ 1.2V, 2-Input NAND, F.O. = 2.Gate density: 160K Gates/mm2 @Utilization = 100%.Fat/Slim profile I/O optimized for Core/Pad limiteddesign.Programmable input characteristics for pull up/down/keeper and Schmitt trigger.Programmable output driving current 2-8mA by stepsof 2mA, 4-16mA by steps of 4mA.Programmable output slew rate control.

Faraday 0.13um Library - High Speed (Low-K) Process

Programmable X’tal oscillator pads.Mixed 1.2V/3.3V interface.Wide selection of I/O buffers: 3.3V, 3.3V with 5Vtolerant.

Single Port SRAM, Dual Port SRAM, Two PortRegister File, and Via2 ROM Memory Instances

Synchronous reads/writesStatic design with zero standby currentByte write capabilityProvides both high speed and low power SRAMsAbility to compile to multiple aspect ratioScan and BIST supportPower port connection supportZero hold time for inputs


5


Standard Cell and I/O:Power supply (internal logic and I/O): 1.2VSecond power supply (I/O): 3.3V8-track cell architecture; Cell high = 3.2um.X grid = 0.4um, Y grid = 0.4um.Gate delay = 33ps/stage @ 1.2V, F.O. = 1Low power: 0.006µW/Gate/MHz @ 1.2V, 2-InputNAND, F.O. = 2Ultra high density: 250K Gates/mm2 @Utilization =100% (i.e. 1million transistors / mm2)Fat/Slim profile I/O optimized for Core/Pad limiteddesignProgrammable input characteristics for pull up/down/keeper and Schmitt triggerProgrammable output driving current 2-8mA by stepsof 2mA, 4-16mA by steps of 4mA.Programmable output slew rate controlProgrammable X’tal oscillator pads

Faraday 0.13um Library - Low Leakage (FSG) Process

Single Port SRAM, Dual Port SRAM, Two PortRegister File, and Via2 ROM Memory Instances


Via2 ROM

Architecture



Dual PortSync. SRAM



Bit




1, 2, 4, 8

Mux

1, 2, 4, 8, 16

1, 2, 4, 8, 16

1, 2, 4, 8

2, 4, 8, 16

Size

4 K bit - 2 Mbit

64 bit - 512 Kbit

16 bit - 72 Kbit

256 bit - 2 Mbit4K x 16


Access Time (ns)






Word






Mixed 1.2V/3.3V interfaceWide selection of I/O buffers: 3.3V, 3.3V with 5Vtolerant.

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Standard Cell and I/O:Power supply (internal logic and I/O): 1.2VSecond power supply (I/O): 3.3V8-track cell architecture; Cell high = 3.2um.X grid = 0.4um, Y grid = 0.4um.Gate delay = 17ps/stage @ 1.2V, F.O. = 1Low power: 0.006µW/Gate/MHz @ 1.2V, 2-InputNAND, F.O. = 2Ultra high density: 250K Gates/mm2 @Utilization =100% (i.e. 1million transistors / mm2)Fat/Slim profile I/O optimized for Core/Pad limiteddesignProgrammable input characteristics for pull up/down/keeper and Schmitt triggerProgrammable output driving current 2-8mA by steps of2mA, 4-16mA by steps of 4mA.Programmable output slew rate control

Faraday 0.13um Library - High Speed (FSG) Process

Single Port SRAM, Dual Port SRAM, Two PortRegister File, and Via2 ROM Instances


Programmable X’tal oscillator padsMixed 1.2V/3.3V interfaceWide selection of I/O buffers: 3.3V, 3.3V with 5Vtolerant.

Via2 ROM

Architecture



Dual PortSync. SRAM



Bit




1, 2, 4, 8

Mux

1, 2, 4, 8, 16

1, 2, 4, 8, 16

1, 2, 4, 8

2, 4, 8, 16

Size

4 Kbit - 2 Mbit

64 bit - 512 Kbit

16 bit - 72 Kbit

256 bit - 2 Mbit4K x 16


Access Time (ns)

4K x 16Typical: 1.25

Worst: 2





Word






7


Standard Cell500+ high density standard cells8-track cell architecture, performance optimized for300~800 MHZAverage cell density of 150K gates/sq.mmMultiple drive strengthsLayout using metal 1 onlyScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timingand powerOpen architecture developers kit available

Virtual Silicon 0.15um Library

Inline and Staggered I/O700+ 3.3V &3.3V/5VT I/O padsPad pitch: 60um (in-line), 40um (staggered)Multiple current drives up to 24mAInput buffer types - Pull-up/pull-down resistor, padkeeper, normal/SchmittOutput and bi-directional buffer types with slew ratecontrolSilicon proven ESD and latch-up structuresAnalog power pads, crystal padsOpen architecture developers kit available


Single Port SRAM, Single Port Borderless SRAM,Dual Port SRAM, Two Port Register File, andDiffusion ROM Compilers


Clock SynthesizerExcellent stability and noise-immunity and low jitterEntire module located in the I/O and ringsReference frequency range: 12.5 MHz-50MHzOutput frequency range:25MHz-400MHz

Diffusion ROM

Architecture


Borderless BitcellSingle Port

Sync. SRAM

Dual PortSync. SRAM



Bit




4, 8, 16, 32

Mux

4, 8, 16, 32

4, 8, 16, 32

4, 8, 16, 32

2, 4, 8

Size

128 bit - 1 Mbit

128 bit - 256 Kbit

64 bit - 72 Kbit

128 bit - 1 Mbit4K x 16


Access Time (ns)




128 x 144Typical: 1.20Worst: 1.95


Word






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Standard Cell478 high-density standard cells9-track cell architectureAverage cell density of 111K gates/sq.mmMultiple drive strengthsRoutable in 3, 4, 5 or more metal layersComprehensive design tool supportProcess specific electrical and physical tuning

Artisan 0.18um Library

Inline I/O600+ 3.3V/5VTPad pitch: 60 umInput: pull-up/pull-down, Schmitt trigger, LVTTL, CMOS

Single Port and Dual Port SRAM CompilersExceptional speedBroadly configurableLow active power and leakage-only standby currentComplete set of tool models and characterization dataFlexible power routingZero hold time (data, address and control inputs)

Architecture


Dual PortSync. SRAM

Bit


Mux

4, 8, 16

4, 8, 16

Size

32 bit - 512 Kbit

Access Time (ns)



Word



2 - 128(Increment: 1) 32 bit - 512 Kbit

Output: multiple current up tp 24mA with 3 slew rateoptionsSpecial pads: clock, crystal oscillator, corner, powerand ground

9


Standard Cell500+ high performance standard cells11-track cell architecture, performance optimized for200~700 MHzAverage cell density of 90K gates/sq.mmMultiple drive strengthsLayout using metal 1 onlyScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timing andpowerOpen architecture developers kit available

Virtual Silicon 0.18um Library

Inline and Staggered I/O700+ 3.3V & 3.3V/5VT I/O padsPad pitch: 60um (In-line), 40um (Staggered)Multiple current drives up to 24mAInput: Pull-up/pull-down resistor, pad keeper, normal/SchmittOutput and bi-directional with slew rate controlSilicon proven ESD and latch-up structuresAnalog power pads, crystal padsOpen architecture developers kit available

PLL CompilersProgrammable input, output frequencies and dutycycleInput frequency range: 20 MHz - 200 MHzOutput frequency range: 50MHz -900MHzPLL module entirely located in the I/O pad ringsDedicated analog power supply pinsBuild-in ESD and latch-up protection structures

Single Port Synchronons SRAM and Two PortRegister File Compilers


Architecture


Two PortRegister File

Bit


Mux

2, 4, 8, 16

1, 2, 4

Size

32 bit - 64 Kbit

Access Time (ns)



Word



2 - 128(Increment: 1) 32 bit - 256 Kbit

10

Dual Port Sync. SRAM

Architecture



Word


Size

32 bit - 512 Kbit

32 bit - 512 Kbit

Access Time (ns)


Mux

4, 8, 16

4, 8, 16

Bit




Artisan 0.25um Library


Standard Cell437+ high density standard cells8-track cell architectureAverage cell density of 64K gates/sq.mmMultiple drive strengthsRoutable in 3, 4, or 5 metal layersComprehensive design tool supportProcess specific electrical and physical tuning

Inline I/O600+ 2.5V/3.3VTPad pitch: 72umMultiple current drives up to 24mA3 slew rate optionsInput characteristics: pull-up/pull-down, Schmitttrigger, LVTTL CMOSOutput characteristics: N-channel and P-channel opendrainSpecial pads: clock, crystal oscillator, corner, powerand groundFully verified tool models

Single Port SRAM and Dual Port Memory CompilersExceptional speedBroadly configurableLow active power and leakage-only standby currentComplete set of tool models and characterization dataFlexible power routingZero hold time (data, address and control inputs)

11


Virtual Silicon 0.25um LibraryStandard Cells

500+ high performance standard cells11-track cell architecture, performance optimized for150~400 MHzAverage cell density of 45K gates/sq.mmMultiple drive strengthsHand-crafted layoutScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timing andpower

Inline I/O70+ 3.3V I/O padsPad pitch: 60umMultiple current drives up to 24mAInput buffer types - Pull-up/pull-down resistor, padkeeper, clock driver and normal/SchmittOutput and bi-directional buffer types with slew ratecontrolSilicon proven ESD and latch-up structures

Two Port Register FileSynchronous reads/writesStatic design with zero standby current

Automated EDA viewsRoutable over the core with higher metal layer

Architecture

Two PortRegister

Word

8 - 256(Increment: 2X mux)

Size

32 bit - 18 Kbit

Access Time (ns)


Mux

NA

Bit

(Increment: 2)

Standard cell and I/O450+ cellsSilicon provenAccurate timing characterizationSupport most of the EDA toolsOptimized for Cadence and Avanti place & route toolsHigh routing density, routability, high speed and lowpowerRoutable for 3,4,5 metals3.3V, 5V I/ODrive strength 4,8,12,16, and 24 mALatchup performance: 500 mAESD protection: 2.5kV HBMLow current leakage

GlobalCAD 0.35um libraryStandard cell and I/O

300+ cellsSilicon provenAccurate timing characterizationSupport most of the EDA toolsOptimized for Cadence and Avanti place & route toolsHigh routing density, routability, high speed and lowpowerRoutable for 2,3,4 metals5V I/ODrive strength 4,8,12,16, and 24 mALatchup performance: 500 mAESD protection: 2.5kV HBMLow current leakage

GlobalCAD 0.5um library

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In addition to the UMC free-of-charge libraries, several vendors have developed UMC library elements that are avail-able to our foundry customers on a fee basis. The following section lists those vendors and offerings:

Non-Free Libraries

Virage 0.13um Memory CompilerUMCProcessType

HS/SP/LL

HS/SP/LL

HS/SP

HS/SP/LL

HS/SP/LL

HS/SP

HS/SP

HS/SP/LL

HS/SP

HS/SP

HS/SP

HS/SP

SP HDASAP

DP HDASAP

1PRegisterfile

2PRegisterfile

ROM

SP HSASAP

DP HSASAP

SPSTARHD-4M

SPSTARHS-512K

DPSTARHS-512K

B-CAM144K

T-CAM144K

WordWidth

(bits/word)

2 - 128

2 - 128

2 - 128

2 - 256

8 - 64

2 - 256

2 - 256

8 - 256

2 - 256

2 - 256

4 - 144

4 - 144

WordWidth(word)

16 - 16K

16 - 8K

8 - 512

8 - 1024

256 - 64K

16 - 16K

32 - 8K

128 - 64K

16 - 16K

32 - 8K

16 - 1K

16 - 1K

MaxSize

(K bits)

32 - 512K

32 - 512K

16 - 16K

16 - 64K

2K - 1M

32 - 512K

64 - 512K

16K - 4M

32 - 512K

64 - 512K

64 - 144K

64 - 144K

MaxConfiguration

16Kx32

8Kx64

512x32

1Kx64

64Kx16

16Kx32

8Kx64

64Kx64

16Kx32

8Kx64

1Kx144

1Kx144

AspectRatio

(Yes/No)

Yes: 4, 8, 16

Yes: 4, 8, 16

Yes: 1, 2, 4

Yes: 1, 2, 4

Yes: 16, 32, 64

Yes: 4, 8, 16

Yes: 4, 8, 16

Yes: 8, 16, 32

Yes: 4, 8, 16

Yes: 4, 8, 16

Yes: 2

Yes: 2

Tcyc for2Kx16,4Kx16Block (Worst

Cond);32x32 forReg. File

2.19, 2.72

2.37, 3.04

2.39

1.370

3.41, 4.7

1.39, 1.55

1.49, 1.74

2.67, 2.98

1.47, 1.68

1.49, 1.74

5.39, 5.43

7.0, 7.21

Bit/Bytewrite

capability

Yes

Yes

Yes

Yes

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Ta for2Kx16,4Kx16Block (Worst


2.17, 2.69

2.35, 3.01

1.55

1.04

2.29, 3.03

1.33, 1.53

1.34, 1.61

2.65, 2.96

1.45, 1.66

1.42, 1.69

5.03, 5.09

6.46, 6.62

RedundancyBuilt-In

No

No

No

No

No

No

No

Yes

Yes

Yes

No

No

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Virtual Silicon 0.13um Library - Low Leakage Process

Standard Cell522 high density standard cells9-track cell architectureAverage cell density of 200K gates/sq.mmMultiple drive strengthsLayout using metal 1 onlyScan version of every flip-flop availableFully contacted well tiesAccurate modeling and characterization for timing andpowerOpen architecture developers kit available





Non-Free Libraries

Word





Bit





Mux

4, 8, 16, 32

4, 8, 16, 32

4, 8, 16, 32

Size

128 bit - 1 Mbit

128 bit - 256 Kbit

64 bit - 72 Kbit

128 bit - 1 Mbit



128 x 144Typical: 2.21Worst: 3.45


Access Time (ns)

2, 4, 8

Architecture

Single Port

Sync. SRAM

Dual Port

Sync. SRAM

Two Port

Sync. Register File

Diffusion ROM

14

Non-Free Libraries

Standard CellsFull custom standard cell library consisting of about500 cellsSingle metal layer design for high routing utilization10-track layoutHigh speed and high densityAccurate timing and power modelsComplete models and views for synthesis andfunctional simulation tools

Standard I/OsStaggered pad design with 30µm pitchCore/Area I/O pads for flip chip (C4) 200µm & 225µmLVCMOS, LVTTL & Schmitt Trigger inputI/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with3.3V outputI/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with3.3V output /5.0V toleranceI/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with2.5V outputI/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with2.5V output /3.3V tolerancePull-up, pull-down, sustain level options4 different slew rate keeper options, JTAG inputs fortestability, Schmitt trigger inputsLevel shifts from 1.2V core up to 3.3V I/O supply andfrom 3.3V to 1.2V

Dolphin 0.13um Library

Memory Compilers with and without RedundancySingle port SRAM, Dual port SRAM, 2-Port RegisterFile and 4-Port Register File compilers using RAMpilerTM

development system and user interfaceRAMpiler +TM with row and column redundancy of upto 2 rows & 2 columns/IOs

- Synchronous reads/writes- Static design with zero standby current- Ability to compile to multiple aspect ratios- Up to 1.1Mbit single instance- Up to 288 bit word- Up to 16K words deep- Fully routable over the memory with higher metallayers

- Small set-up and zero hold times- Power ring size based on frequency of operationand load

- Multiple pin placement and layer options- Multiple power ring metal layer and configurationoptions

- Register output options- Multiple output drive strengths- Different power ring design configurations- Bit Write Mask or Word (global write) options- Write through, transparent write- BIST Mux option on the inputs- Row redundancy- Column/IO redundancy

2-Port (1R/1W) register file compiler4-Port (2R/2W) register file compiler

Specialty MemoriesBinary BCAM memories and CAM compilers usingCAMpilerTM technologyTernary TCAM memories and CAM compilers usingCAMpilerTM technology

Custom single instance large density SRAMS withredundancy up to 24 MbitsCustom Register Files with different configurationssuch as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R,etc.

Word





Bit





Mux

4, 8, 16

4, 8, 16

1, 2, 4, 8, 16

Size

8 bit - 1296 Kbit

8 bit - 288 Kbit

2 bit - 288 Kbit

2 bit - 288 Kbit



128 x 144Typical: 1.59Worst: 2.29

128 x 44Typical: NAWorst: NA

Access Time (ns)

1, 2, 4, 8,16

Architecture

Single Port (1R/W)

Sync. SRAM

Dual Port (2R/W)

Sync. SRAM

Two Port Sync.

Register File (1R/1W)

4-Port Register File

15

Standard Cells1000+ high performance standard cells9-track cell architecture high speedAverage cell density of 156K gates/sq.mm8-track cell architecture high densityAverage cell density of 192K gates/sq.mmMultiple drive strengthsSilicon provenScan version of every flip-flop availableCompatible with mixed signal environmentAccurate timing and power models

Non-Free Libraries

Nurlogic 0.13um Library

In-line and staggered I/O3.3VPad pitch: 70um (In-line), 35um (Staggered)Multiple current drives up to 16mAPull ups, Pull downs, switchableHysteresisBuilt-in level shifting

GlobalCAD 0.15um libraryStandard cell andI/O

450+ cellsSilicon provenAccurate timing characterizationSupport most of the EDA toolsOptimized for Cadence and Avanti place & route toolsHigh routing density, routability, high speed and lowpower

Routable for 3,4,5 metals1.2/1.5V, 3.3V I/ODrive strength 4,8,12,16, and 24 mALatchup performance: 200 mAESD protection: 2.0kV HBMLow current leakage

Silicon Design Solutions 0.15um Memories

Word

2 - 1K(Increment: 1)




Bit





Mux

1, 2, 4

1, 2, 4

1, 2, 4

Size

4 bit - 65 Kbit

4 bit - 65 Kbit

4 bit - 65 Kbit





Access Time (ns)

1, 2, 4

Architecture

1- Port (1R/W)

Sync./Asnc.

Register File

2-Port (1R/1W)

Sync./Asnc.

Register File

3-Port (1R/1W)

Sync./Asnc.

Register File

4-Port (1R/1W)

Sync./Asnc.

Register File

4-Port (1R/1W)

Sync./Asnc.

Register File

4 bit - 65 Kbit



2 - 256(Increment: 1) 1, 2, 4 4 bit - 65 Kbit

16

Non-Free Libraries

Virage 0.18um Memory Compiler

SP HDSRAM

DP HDSRAM

2P RegisterFile

ROM

SP HSSRAM

DP HSSRAM

SP STARHD-4M(SRAM with

redundancy)

SP STARHS-512K

DP STARHS-512K(SRAM

withredundancy

T-CAM 32K

WordWidth

(bits/word)

2 - 128

2 - 128

2 - 256

8 - 64

2 - 256

2 - 256

8 - 256

2 - 256

2 -256

16 - 64

WordDepth(words)

16 - 16K

16 - 8K

8 - 1024

256 - 64K

16 - 16K

32 - 8K

128 - 64K

16 - 16K

32 - 8K

16 - 512

MaxSize

(Kbits)

32 - 512K

32 - 256K

16 - 16K

2K - 1M

32 - 512K

64 - 256K

16K - 4M

32 - 512K

64 - 256K

1K - 32K

MaxConfiguration

16 - 32K

8x32K

1Kx16

64Kx16

16Kx32

8Kx32

64Kx64

16Kx32

8Kx32

512Kx64

AspectRation

(Yes/NO)

Yes: 4,8,16

Yes: 4,8,16

Yes: 1,2,4

Yes: 16,32,64

4,8,16

4,8,16

Yes: 8,16,32

4,8,16

4,8,16

1

Tcyc for2Kx16, 4Kx16Block (Worst


3.03, 3.33

3.24, 3.67

2.02

4.09, 5.8

2.15, 2.45

2.44, 2.81

3.8, 4.1

2.31, 2.61

2.6, 2.97

6.46

Ta for2Kx16, 4Kx16Block (Worst


2.99, 3.3

3.19, 3.64

1.7

3.14, 4.34

2.13, 2.42

2.42, 2.78

3.6, 3.89

2.29, 2.58

2.58, 2.94

3.81

Bit/Bytewrite

capability

Yes

Yes

Yes

No

Yes

Yes

Yes

Yes

Yes

No

RedundancyBuilt-in

No

No

No

No

No

No

Yes

Yes

Yes

No


1-Port (1R/W)Sync./Async Register File

2-Port (1R, 1W)Sync./AsyncRegister File



4- Port (2R, 2W)Sync./AsyncRegister File

Architecture Word


Bit


Mux

1, 2, 4

Size

4 bit - 65 Kbit

Access Time (ns)














17

Non-Free Libraries

Faraday 0.18um Library

Architecture Access Time (ns)


Size

4 bit - 2 Mbit

Mux

1, 2, 4, 8, 16

BitWord

4 bit - 512 Kbit1, 2, 4, 8

256 bit - 2 Mbit


Via2 ROM

Dual PortSync. SRAM

4 - 256K(Increment:2X mux)





2 - 128(Increment: 1) 1, 2, 4, 8



Standard Cell400+ high performance standard cells9-track cell architectureAverage cell density >120K gates/sq.mmOptimized multiple drive strengthsHigh porosity and routabilityScan version of every flip-flop availableUltra low power cell availableGated input for preventing leakageFully tool models support

AnalogExcellent high PSRR and low jitter Phase-LockedLoops10-Bit DAC 200MHz8-Bit ADC 135MHzPower-on-reset circuitLow VDD DetectorRC oscillatorsVoltage RegulatorsComparatorsCrystal pads

Inline and Staggered I/O1.8V, 3.3V I/O pads1.8V/2.5VT, 3.3V/5VT I/O padsSupport over 500+ IO FunctionsPad pitch: 65um (In-line), 40um (Stagger)Programmable current drives and slew rate controlfrom 2mA to 16mAProgrammable pull-up/pull-down resistor, normal/Schmitt triggerProvide 90+ programming features in one I/OIn-line to staggered I/O corner available

Single Port SRAM, Dual Port SRAM, and Via2 ROMCompilers

Synchronous reads/writesStatic design with zero standby currentByte write capabilityProvides both high speed and low power SRAMsAbility to compile to multiple aspect ratioScan and BIST supportPower port connections supportZero hold time for inputs

Standard Cell1000+ High Performance standard cells9-track cell architectureAverage cell density of 73K gates/sq.mmMultiple drive strengthsSilicon provenScan version of every flip-flop availableCompatible with mixed signal environmentAccurate timing and power models

Nurlogic 0.18um LibraryIn-line and staggered I/O

3.3V/5VTPad pitch: 76.8um (In-line), 38.4um (Staggered)Multiple current drives up to 16mAPull ups, Pull downs, switchableHysteresisBuilt-in level shifting

18

Non-Free Libraries

Standard cell and I/O450+ cellsSilicon provenAccurate timing characterizationSupport most of the EDA toolsOptimized for Cadence and Avanti place & route toolsHigh routing density, routability, high speed and lowpowerRoutable for 3,4,5,6 metals1.8V, 3.3V I/ODrive strength 4,8,12,16, and 24 mALatchup performance: 200 mAmpESD protection: 2.0kV HBMLow current leakage

GlobalCAD 0.18um librarySingle Port SRAM, Two Port SRAM, Dual PortSRAM and Via2 Mask ROM Memory Instances

Synchronous reads/writesStatic design with zero standby currentBytes write capabilityProvides both high speed and low power SRAMsAbility to compile to multiple aspect ratioPower port connections support

Architecture Size

128 bit - 512 Kbit

Mux

4, 8, 16

BitWord

128 bit - 256 Kbit4, 8,16

128 bit - 256 Kbit


Via2 MROM

Dual PortSync. SRAM






8 - 64(Increment: 1) 4, 8, 16

Two PortSync. SRAM

32 bit - 2 Mbit32 - 8K

(Increment:128X mux)1 - 64

(Increment: 1) 4, 8, 16, 32, 64

Standard I/OStaggered pad design with 35,50,70 um pitchI/O pads for flip chip(C4) 240um &250umI/O Drive strengths 2/4/6/8/10/12mA 1.8V core with3.3V output

Dolphin 0.18 um Library

Pull-up, pull-down, sustain level options4 different slew rate keeper options, JTAG inputs fortestability, Schmitt trigger inputsLevel shifts from 1.8 V core up to 3.3 V I/O supply

19

Non-Free Libraries

Faraday 0.25um Library

Architecture Access Time (ns)


Size

4 bit - 2 Mbit

Mux

1, 2, 4, 8, 16

BitWord

4 bit - 160 Kbit1, 2, 4, 8

256 bit - 1 Mbit


Via2 ROM

Dual PortSync. SRAM







1, 2, 4, 8



Diffusion ROM 128 - 64K(Increment:128X mux)


1, 2, 4, 8 256 bit - 1 Mbit4K x 16

Typical: 7.3Worst: 12.1

Standard Cells400+ high performance standard cells8-track cell architectureAverage cell density >60K gates/sq.mmOptimized multiple drive strengthsHigh porosity and routabilityScan version of every flip-flop availableUltra low power cell availableGated input for preventing leakageFully tool models support

AnalogExcellent high PSRR and low jitter Phase-LockedLoops10-Bit DAC 200MHz8-Bit ADC 135MHzPower-on-reset circuitLow VDD DetectorRC oscillatorsVoltage RegulatorsComparatorsCrystal pads

Inline and Staggered I/O2.5V, 3.3V I/O pads2.5V/3.3VT, 3.3V/5VT I/O padsSupport over 500+ IO FunctionsPad pitch: 65um (In-line), 40um (Stagger)Programmable current drives and slew rate controlfrom 2mA to 16mAProgrammable pull-up/pull-down resistor, normal/Schmitt triggerProvide 90+ programming features in one I/O padIn-line to staggered I/O corner available

Single Port SRAM, Dual Port SRAM, Diffusion andVia2 ROM Compilers

Synchronous reads/writesStatic design with zero standby currentByte write capabilityProvides both high speed and low power SRAMsAbility to compile to multiple aspect ratioScan and BIST supportPower port connections supportZero hold time for inputs

20

Non-Free Libraries

Standard Cells1000+ cells10-track cell architectureAverage cell density of 36K gates/sq.mmMultiple drive strengthsSilicon provenScan version of every flip-flop availableCompatible with mixed signal environmentAccurate timing and power models

In-line and Staggered I/O3.3V/5VTPad pitch: 76.8mm (In-line), 52.8mm (Staggered)Multiple current drives up to 16mAPull ups, Pull downs, switchableHysteresisBuilt-in level shifting

Nurlogic 0.25um LibraryMemories

Single port register files, 24KbitsTwo port register files, 24Kbits

Analog800MHz Phase Locked Loop (PLL)266MHz Video Phase Locked Loop (PLL)Fast Crystal Oscillator 4-33 MHz


1-Port (1R/W)Sync./Async Register File

Architecture Word


Bit


Mux

1, 2, 4

Size

2 bit - 65 Kbit

Access Time (ns)














4- Port (2R, 2W)Sync./AsyncRegister File




21

Non-Free Libraries

Features450+ cellsSilicon provenAccurate timing characterizationSupport most of the EDA toolsOptimized for Cadence and Avanti place & route toolsHigh routing density, routability, high speed and lowpowerRoutable for 3,4,5,6 metals2.5V, 3.3V, 5V I/ODrive strength 4,8,12,16, and 24 mALatchup performance: 500 mAESD protection: 2.5kV HBMLow current leakage

GlobalCAD 0.25um librarySingle Port SRAM, Two Port SRAM, Dual PortSRAM and Via2 Mask ROM Memory Instances

Synchronous reads/writesStatic design with zero standby currentBytes write capabilityProvides both high speed and low power SRAMsAbility to compile to multiple aspect ratioPower port connections support

Architecture Size

128 bit - 512 Kbit

Mux

4, 8, 16

BitWord

128 bit - 256 Kbit4, 8,16

128 bit - 256 Kbit


Via2 ROM

Dual PortSync. SRAM






8 - 64(Increment: 1) 4, 8, 16

Two PortSync. SRAM

32 bit - 2 Mbit32 - 8K

(Increment:128X mux)1 - 64

(Increment: 1) 4, 8, 16, 32, 64

22

Special I/O

Technology

0.13um

0.15um

0.18um

0.25um

0.35um

Vendors

Dolphin

Leda

Macrotech

NurLogic

Faraday(LL)

Faraday

VST

GlobalCAD

GlobalCAD

Leda

VST

Dolphin

Faraday

(Low Power)

Faraday

GlobalCAD

Nurlogic

VST

Dolphin

Leda

VST

Faraday

GlobalCAD

Nurlogic

Faraday

GlobalCAD

*

4x

*

*

*

*

*

*

*

8x

CM

L

LVD

S

LV

TT

L

HS

DL

HS

TL

PE

CL

LVP

EC

L

DD

R-I/

II

SS

TL

AG

P

PC

I

PC

I-X

US

B1.

1

US

B2.

0

I2C

GT

L

K7b

us

HT

K8

Phy

LD

TP

hy

GM

II

RG

MII

DV

I

TM

DS

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

* * *

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

* *

*

*

*

2x

*

*

*

*

*

*

Q3/02

Q3/02

Q3/02

Q3/02 Q2/02

Q3/02

Q3/02

Q3/02

Q4/02 Q4/02 Q4/02Q4/02Q4/02

Q4/02

Q4/02

23

IP Catalog

UMC is helping designers and system developers overcome system-on-chip (SOC) and time-to-market hurdles byproviding easy access to third party IP blocks ready for integration into customer designs. Our goal is to build acatalog of third party IP mega-cells customizable to UMC process technology. “Interoperability” of IP remains amajor element of our program, speeding customer time-to-market and lowering the risks associated with very deepsub-micron design. The third party IP included in our IP catalog is characterized according to the following Gold IPguidelines:

Bronze: Softcore or GDSII available Silver: Hardcore available, silicon verified Gold: Production verified

PLL

Bronzeb

b

b

b

b

b

b

Part NumberETI-2800PLL8001

PLL8002PLL8002DPLL8003PLL8005

PLL8007PLL8011PLL9011PLL9011T

PLLA002U103A

PLL

TC_UM13A3910_PLTC_UM13A3920_DLTC_UM13A3930_PD

LDPLL10-13LDPLL10-18LDPLL11-13LDPLL3-13

LDPLL38-18LDPLL39-15LDPLL40-15LDPLL6-13

LDPLL8-18PLL2-15125 MHz PLL266MHz DeSkew PLL

CEPLLPLL

DescriptionPLL, Fout < 800MHz3.3V,ckout:2.5-280Mhz,N=1~323.3V, ckout:15-200Mhz,N/M=3/2 bit

3.3V, ckout:40-400Mhz,N/M=3/2 bit3.3V,ckout:2.5-280Mhz,N=1~643.3V, ckout:5-280Mhz,N=1-323.3V, ckout:5-280Mhz,N=1-64

3.3V, ckout:20-200Mhz,N/M=6/3 bit2.5V, ckout:20-200Mhz,N/M=6/3 bit2.5V, ckout:20-200Mhz,N/M=8/8 bit1.8V, ckout:20-300Mhz,N/M=6/6 bit

PLL up to 1Ghz freq synthesis is possible (0.25um).Silicon proven on 480MHzprogrammable PLL clock generator. Integrated MULand DIV

Programmable PLL(250 MHz to 800 MHz)DLL (Logic design—Synthesizable)Phase Detector(Largic Design—Synthesizable)3.1 GHz PLL

50-200 MHz PLL19.44-1244 MHz PLL250-1650 MHz PLL10-250 MHz PLL

100-400 MHz PLL400 MHz, 8 phase PLL3 - 6 GHz PLL2-50 Mhz PLL

250-1650 MHz PLL F-out: 100~167MHz F-out: 66MHz,133MHz,266MHz F-out: 78~700 MHz

F-out: 80~333 MHz

Silver

0.35um

0.35um

0.35um0.35um

0.25um

b

0.15um

0.13um0.13um0.13um

0.13um

0.15um0.15um

0.15um

0.13um

Gold

0.35um0.35um

0.35um

0.25um

0.18um

0.35um/0.25um/0.18um

0.13um0.13um

0.13um

VendorET IFaradayFaraday

FaradayFaradayFaradayFaraday


FTDPL

GlobalCAD

ITCITCITCLEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDANurlogicNurlogicNurlogic

Nurlogic

24

PLL

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Part NumberQuadrature PLL

Video PLL 266 MHzFractional N PllsLow refresh PLlsPLL_Expert

13PLL-150/17413PLL-48

SXPLL-FS240SXPLL-P800TCI13HS400CGPLLTCI13HS400DSPLL

TCI13HS800CGPLLTCI13HS800DSPLLTCI13SP400CGPLLTCI13SP400DSPLL

TCI13SP800CGPLLTCI13SP800DSPLLTCI15HS350CGPLLTCI15HS350DSPLL

TCI15HS700CGPLLTCI15HS700DSPLLTCI18G250CGPLLTCI18G250DSPLL

TCI18G275CGPLLTCI18G275DSPLLTCI18G500CGPLLTCI18G500DSPLL

TCI18G550CGPLLTCI18G550DSPLLTCI25G200CGPLLTCI25G200DSPLL

TCI25G400CGPLLTCI25G400DSPLL

DescriptionF-out: 107~333 MHzF-out: 266 MHz

Frequency synthesizer: output frequency:10 MHz - 650 MHz, Deskewing, programmable

feedback dividersPLL, 150/174 MHzPLL, 48 MHz240 MHz Clock Generator PLL

Programmable 96-800MHz PLL0.13um HS 80-400MHz Clock Generator PLL0.13um HS 80-400MHz Deskew PLL0.13um HS 160-800MHz Clock Generator PLL

0.13um HS 160-800MHz Deskew PLL0.13um SP 80-400MHz Clock Generator PLL0.13um SP 80-400MHz Deskew PLL0.13um SP 160-800MHz Clock Generator PLL

0.13um SP 160-800MHz Deskew PLL0.15um HS 70-350MHz Clock Generator PLL0.15um HS 70-350MHz Deskew PLL

0.15um HS 140-700MHz Clock Generator PLL0.15um HS 140-700MHz Deskew PLL0.18um GII 50-250MHz Clock Generator PLL0.18um GII 50-250MHz Deskew PLL

0.18um G 55-275MHz Clock Generator PLL0.18um G 55-275MHz Deskew PLL0.18um GII 100-500MHz Clock Generator PLL0.18um GII 100-500MHz Deskew PLL

0.18um G 110-550MHz Clock Generator PLL0.18um G 110-550MHz Deskew PLL0.25um G 40-200MHz Clock Generator PLL0.25um G 40-200MHz Deskew PLL

0.25um G 80-400MHz Clock Generator PLL0.25um G 80-400MHz Deskew PLL

Silver

0.13um-Q3/020.13um-Q3/02

0.35um

0.25um

Gold0.13um0.25um

0.18um0.18um0.18um

VendorNurlogic

NurlogicParthusParthusParthus

SarnoffSarnoff

Sl iceXSliceXTrue CircuitsTrue Circuits

True CircuitsTrue CircuitsTrue CircuitsTrue Circuits





True CircuitsTrue Circuits

25

DAC

ADC

Bronze

b

b

b

b

b

Gold0.35um

0.25um

Part Number

ADC8011ADC9011

1-bit ADC

LDACD20-18LDADC10-13LDADC20-13

LDADC24-18LDDADC25-18LDDADC29-1813ADC10-50

SXAD0810MSXAD1016M-0SXAD1032M-0

DescriptionSAR ADC 10bit 100KSPS two channels VCC=3.3VSAR ADC 8bit 100KSPS VCC=3.3V for core and 2.5Vfor digital output interface

Maximum cover frequency 1 MHz with 20mV peak topeak voltage level10 bit, 100 Msps ADC16 bit, 44KHz Sigma-Delta ADC

10 bit, 100 Msps Pipeline ADC10 bit, 1 Msps ADCDual 10 bit,1 Msps ADC6 bit, 44 Msps dual ADC

ADC 10 bits, 50 MHz8-bit 10MSPS A/D Converter10-bit 16MSPS A/D Converter10-bit 32MSPS A/D Converter

Silver

0.25um

0.18um

0.13um-Q3/020.35um0.35um0.35um

VendorFaraday

Faraday

GlobalCAD

LEDALEDALEDALEDA

LEDALEDASarnoffSl iceX

SliceXSliceX

Part Number

ETI-3008 ETI-3009 ETI-3010 ETI-3108

ETI-3109 ETI-3110 DAC8001DAC8002

DAC8003DAC8011DAC9003

DAC9011

8-bit ADC

LDDAC11-18LDDAC2-13

LDDAC3-13LDDAC4-18

Description8-bit Video DAC, 520MHz, triple video with sync

9-bit Video DAC, 520MHz, triple video with sync10-bit Video DAC, 520MHz, triple video with sync 8-bit Video DAC, 570MHz, triple video with sync 9-bit Video DAC, 570MHz, triple video with sync

10-bit Video DAC, 570MHz, triple video with sync 8bit 200MHz one channel VCC=3.3V8bit 200MHz three channels VCC=3.3VCurrent steering DAC 10bit 80MHz VCC=3.3V

R2R DAC 8bit 500KSPS one channel VCC=3.3VCurrent steering DAC 10bit 80MHz one channel,VCC=3.3V and 2.5V for digital input interfaceR2R DAC 8bit 500KSPS one channel VCC=3.3V for

core and 2.5V for digital input interface8-bit successive approximation (SAR) ADC. Operatesupto 1.5 MHz.Features with analog comparator with sample-and-hold

and offset calibration8 bit, 5 Mhz DAC10 bit, 100 MHZ Current DAC12 bit, 250 MHz Current DAC

10 bit, 200 MHz DAC

Bronze

b

b

b

Silver

0.25um0.25um0.25um0.18um

0.18um0.18um0.35um0.35um

0.35um0.35um0.25um

0.25um

0.18um

Gold

0.25um

Vendor

ET IET IET IET I

ET IET IFaradayFaraday

FaradayFaradayFaraday

Faraday

GlobalCAD

LEDALEDA

LEDALEDA

26

DAC

Part NumberLDDDAC14-18LDDDAC32-18

LDTDAC8-13LDTDAC8-1518DAC1018DAC12

PWMSSDAC

13DAC12-200SXDA10-0

Description10 bit, 1 MHz dual DAC8 bit, 44 MHz dual DACTriple 10 bit 400 MHz Video DAC

Triple 10 bit, 400 MHzVideo DAC10-bit DAC12-bit DAC24-Bit, Audio D/A Converter with Oversampling

Interpolation FilterDAC 12 bits, 200 MHz10-bit 90MSPS Current Steering DAC

Bronzeb

b

Silver

0.13um0.15um0.18um0.18um

0.18um

0.13um-Q3/020.35um

Gold VendorLEDALEDA

LEDALEDAMacrotechMacrotech

NEL

SarnoffSl iceX

ANALOG/MIXED-MODE

Part NumberEOSC1EOSC2

EOSC3BGA001BGC001BGC002

CMP9001CMPTDIOSC8002OSC9001

POR8001

POR9001

POR9002

PORA001

PORM3

REG8003H

REG9001H

REG9002H

Description1MHz ~ 20MHz XTAL OSC20MHz ~ 35MHz XTAL OSC

35MHz ~ 50MHz XTAL OSCVCC=3.3V VBG=1.23VVCC=3.3V VBG=1.23VVCC=1.2V VBG=0.615V

0.25um 20MHz General Purpose Comparator0.8V and 4.4V Voltage Comparator for Voltage DetectorOscillator VCC=3.3VOscillator VCC=2.5V

Power On Reset with detect voltage Vrr=2.3VVfr=2.1V VCC=3.3VPower On Reset with detect voltage Vrr=1.9VVfr=1.6V VCC=2.5V

Power On Reset with detect voltage Vrr=1.8VVCC=2.5VPower On Reset with detect voltage Vrr=1.1VVfr=1.0V VCC=1.8V

Power On Reset with detect voltage Vrr=2.6VVCC=3.3VRegulator with driving capability 150mA VCC=5VV33=3.3V and low standby current

Regulator with driving capability 70mA VCC=3.3VV25=2.5VRegulator with driving capability 150mA VCC=3.3VV25=2.5V

Bronze0.25um, 0.35um

0.25um, 0.35um0.25um, 0.35um

Silver

0.13um

0.13um0.25um0.35um

0.35um

0.25um

0.25um

0.18um

0.35um

Gold

0.18um

0.35um0.25um

0.35um

0.35um

0.25um

VendorET I

ET IET IFaradayFaraday



Faraday

Faraday

Faraday

Faraday

Faraday

Faraday

Faraday

27

ANALOG/MIXED-MODE

VendorFaraday

Faraday

FaradayFaradayGlobalCAD

GlobalCAD

GlobalCAD

GlobalCAD

GlobalCAD

GlobalCAD

GlobalCADITC

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

SarnoffSarnoffSarnoff

Gold0.18um

0.18um

0.25um,

0.18um

0.25um

0.25um

0.18um

0.25um

0.18um

Part NumberREGA001H

REGA002H

VDT8002

VDT9001LV

OSC10_50

OSC24OSC32

OSC48Power Regulator

R O S CITC_UM13A3924_OSBGB2-18LDBGB1-13

LDBGB1-15LDBGB2-15LDBGB4-13LDBGB5-13

LDCMP1-15LDMUX1-15LDOP1-15LDOP4-15

LDOP6-15LDPMC1-18LDPMC2-18LDVR3-18

LDXTAL1-15LDXTAL3-18LDXTAL4-18POR3-18

VR1-18VR2-1813AIOP13BNDGP

13PWRD

DescriptionRegulator with driving capability 50mA VCC=3.3V

V18=1.8VRegulator with driving capability 100mA VCC=3.3VV18=1.8VVoltage detector with Vdet=2.8V VCC=3.3V

Voltage detector with Vdet=2.0V VCC=2.5VVoltage level shifter

Design to work with standard 10 MHz to 50 MHz real

time crystalDesign to work with standard 24 MHz real time crystalLow power consumption (less than 40uA).Power downmode and works with standard 32 KHz real time

crystalDesign to work with standard 48 MHz real time crystalFeed in 3.3V and regulated to 2.5V with maximumcurrent of 100 mA

Relaxation OscillatorOscillator (10 to 30 MHz) — four pad locations (2 pwr)3.3v, external R. BandgapBandgap with internal resistor

Bandgap, 3.3v with internal resistor2.5v, internal R. BandgapInternal Resistor BandgapBandgap with internal resistor

P-channel Comparator, 12ns delay2 input, 50 ohm Analog MUXOpamp1 MHz, 2.5V Opamp

1 MHz, 2.5v Opamp3.3v PCM1.8v PCMExt BG, x4 20 mA Voltage Regulator

27 MHz Crystal Oscillator10-15 MHz Crystal Osc.10-15 MHz Crystal Osc.Power on reset

Ext BG, 5 mA Voltage RegulatorExt BG, 20 mA Voltage RegulatorAnalog I/O PadBandgap Reference

Power Detect

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

Silver

0.35um0.25um0.15um

0.35um

0.15um0.13um

0.13um0.15um0.15um

0.15um0.15um0.15um

0.15um

0.15um

0.13um-Q3/02

0.13um-Q3/020.13um-Q3/02

28

BUS INTERFACE

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Part NumberFPCI

FPCI66

FUSB100

FZUSB200H90AUSB90B1HUSB90B2H

USBA0A1HZUSB_S80AG2250G2261U

G2262UU S B

PECL

SL100

SL200Sl250SL258SL730

SL75SL755SL770e1377

1378169616981755

1761180518071813

1992199419972179

23872513

DescriptionPCI MASTER/SLAVE 33MHz

PCI MASTER/SLAVE 66MHz

USB 1.1 controller with Bulk, Interrupt, ISO, and Controltransfer

USB2.0 TransceiverUSB1.1USB1.1USB1.1

USB1.1RS232 Compatible UARTUniversal USB transceiverUniversal USB protocol engine

USB transceiver is fully support to Standard USBRev. 1.1Low power consumption. Support full speed(12 Mbs),low speed(1.5Mbs)and suspension mode

This receiver is terminated to reflection noises in order toprovide better signalUSB 1.1 Device ControllerUSB 2.0 Transceiver

USB 2.0 Device ControllerUSB - AHB Device Controller1394a PHYUSB 1.1 Transceiver

1394a Link1394a A/V Link with encryption32 bit, 33MHz PCI32 bit, 66MHz PCI

64 bit, 33MHz PCI64 bit, 66MHz PCIIEEE 1394A Device Controller Link CoreIEEE-1394 CPHY Synthesizable Core - Digital Cable PHY

USB 1.1 Host Controller Synthesizable CoreUSB 1.1 Device Controller Synthesizable Core (Function)USB 1.1 HUB Controller Synthesizable CoreIEEE 1394A AV Link Core (61883)

IEEE-1394 OHCI LinkPCI-XUSB 2.0 Device ControllerUSB 2.0 PHY UTMI (Hard Macro)

Utopia Level III

Si lver0.25um,

0.35um0.25um-Q3/02

0.25um0.25um0.25um

0.18um

0.35um

0.15um

0.25um,0.18um

0.18um

Gold

0.35um

0.35um

0.35um,0.25um,0.18um

VendorFaraday

Faraday

Faraday


FaradayGlobalCADGlobalCADGlobalCAD

GlobalCAD

Innovative

InnovativeInnovative

InnovativeInnovativeInnovativeInnovative

InnovativeinSiliconinSiliconinSilicon

inSiliconinSiliconinSiliconinSilicon



inSilicon

29

BUS INTERFACE

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Part Number25302554

CION200T1225LDCML1-13LDCML2-13LDDVI1-15

LDDVI-13LDLVDS1-13LDLVDS2-15 (Rx)LDLVDS2-15 (Tx)

LDLVDS3-13 (Rx)LDLVDS3-13 (Tx)LDLVDS4-13LDLVPECL1-13

LDLVTTL1-15LDSSTL2CII-15LDSSTL2CII3-13LDTMDS1-13

LDTMDS1-15 (Tx)LDTSC8-18LDUSB1-13LVDS4-15 (Rx)

LVDS4-15 (Tx)LVTTL8IO100-15LVTTLRX100-15LVTTLTX100-15

M1284HM16550AM16550SM16C450

M16X50M82365SLM8490MCAN2.0

MI2CMI2Cv2MPCI32MPCMCIA1

MUSBFDRCMUSBFSFCMUSBHSFCMUSBLSFC

DescriptionUSB 2.0 Host Controller

USB On-The-GoCardbus200 MHz LVCMOSCML 1.5 GHz

CML 2.5 GHz6 Channel 1.65 GHz DVI (Tx)Triple 1.65G DVI TXLVDS 750 MHz

622-800 MHz LVTTL622-800 MHz LVTTL1.244 GHz LVDS1.244 GHz LVDS

LVDS 622 GHzLVPECL 750 MHz8 mA Bidirectional LVTTL400 Mhz SSTL

SSTL, 2.5v, 167 MHzTMDS 1.625 GHzTMDS 250-1650 MHzTouch Screen Controller

USB 1.1(12 MHz)622 MHz LVDS622 MHz LVDS8 mA, 100 MHz bd LVTTL

100 MHz Rx LVTTL8 mA, 100 MHz Tx LVTTLIEEE 1284 Host Parallel PortEnhanced UART with FIFO

Enhanced UART with FIFO and Synchronous CPU I/FUARTEnhanced UART with FIFO and IrDAPCMCIA PC Host Interface

5380 Compatible SCSI InterfaceCAN 2.0 Network ControllerI²C Bus InterfaceI²C V2.0 Bus Interface

32Bit 33/66MHz PCI Peripheral CorePCMCIA PC Card InterfaceUSB 2.0 High/Full Speed Function Controller (OTG)USB 1.1 Full Speed Function Controller

USB 2.0 High/Full Speed Function ControllerUSB 1.1 Low Speed Function Controller

Silver0.18um

0.15um0.13um

0.15um0.15um0.13um0.13um

0.15um

0.13um0.15um

0.15um0.15um0.15um

0.15um0.15um

Gold VendorinSiliconinSiliconinSilicon

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

LEDALEDALEDALEDA

MentorMentorMentorMentor




30

BUS INTERFACE

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Part NumberHypertransport PHYPCI 1366PCI 13X

PCI 25BK-3103BK-3105BK-3110

BK-3211BK-3220BK-3401BK-3712

BK-3713BK3754DW_PCIDW_PCIX

DW_USBM16450M16550AV6001

V6201V8101V9012PWipro1394A-1000

Wipro1394A-1010Wipro1394A-1200Wipro1394A-1400Wipro1394A-2000

Wipro1394BLinkWipro1394BPHYWiproUSB1.1DevWiproUSB1.1Host

WiproUSB2.0Dev

DescriptionHypertransport PHY Interface Core

PCI, 33MHz/66MHzPCI-X, 66MHz/133MHzPCI, 33MHz/66MHzUART - 16450/16550 compatible UART

UART liteUART - Smart 16550 CompatibleSPI master coreSerial I2C

IEEE 1284 parallel port controllerPCMCIA Host ControllerPCMCIA Client Interface ISO7816 smart card interface

PCI 2.2 corePCI-X coreUSB 2.0 device controllerUART

UART with FIFOAMBA AHB-APB Bus BridgeConfigurable PCI-X ControllerAHB-Based Memory Controller

USB 1.1 Device Controller1394.a Link1394.a Link+PCI1394.a Link+OHCI+PCI

1394 A/V Link + 5C Content Protection1394.a Digital PHY1394.b Link1394.b Digital PHY

USB 1.1 Device Controller CoreUSB 1.1 Host Controller CoreUSB 2.0 Device Controller Core

Silver0.13um-Q4/02

Gold

0.13um

0.13um0.25um

0.25um

0.35um

VendorNurlogicNurlogic

NurlogicNurlogicPalmchipPalmchip

PalmchipPalmchipPalmchipPalmchip

PalmchipPalmchipPalmchipSynopsys

SynopsysSynopsysVirtual IP GroupVirtual IP Group

Virtual IP GroupVirtual IP GroupVirtual IP GroupVirtual IP Group

WiproWiproWiproWipro


WiproWipro

31

MICROCONTROLLER AND MICROPROCESSOR

Gold

0.25um,0.18um

0.18um

0.35um

0.35um

0.18um,0.25um,

0.35um

0.18um,

0.35um,0.5um

Part NumberARCtangent

Turbo 186Turbo 86V186V6502

V 8V8086VZ80ARM1022E

ARM7TDMI

ARM922T

ARM946E

ETM10

ETM7ETM9F8031

F8032

FT8032

G1000

G2000

GC2000CA

GC2000CBITC_UM13A3950_RK

ITC_UM13A395A_RKM8051M8051EW

DescriptionSynthesizable 32-bit RISC/DSP core customizable instrset, code compression, DSP

“Turbocharged” 80186 microprocessor core“Turbocharged” 8086 microprocessor core“Classic 80186 microprocessor core6502 microprocessor core

V8 microRISC microprocessor core“Classic” 8086 microprocessor coreZ80 Microporcessor CoreARM1022E

ARM7TDMI

ARM922T

ARM946E

Embedded Trace Macrocell ARM10 cores

Embedded Trace Macrocell ARM7 coresEmbedded Trace Macrocell ARM9 cores8-bit micro-controller with standard 12clk/machinecycle128 bytes of on-chip Data RAM,two 16-bit timer/

counters8-bit micro-controller with standard 12clk/machinecycle256 bytes of on-chip Data RAM,Three 16-bit timer/counters

8-bit micro-controller high speed 4clk/machine cyclearchitecture 256 bytes of on-chip Data RAM,Three 16-bittimer/countersTwo 16-bit dptrIntegrated 8-bit micro-controller core compatible with

8052 specificationIntegrated 16/32-bit micro-controller with many peripher-als

8088/8086/80186 Compatible Microprocessor Core,100MHz80186 Compatible Microcontroller, 100MHzOMNIcore — 32-bit RISC Processor

OMNIcore — 32-bit RISC Processor with AMBA AHB8-bit MicrocontrollerFast 8-bit Microcontroller with on-chip debug

Silver

0.13HS-Q3/020.13SP &

0.13LL-Q3/020.13HS, Q3/02

0.13SP, Q3/020.15LL

0.18um-Q3/02,0.13SP-Q4/02

0.13um-Q3/020.13um-Q4/020.13um-Q3/02

0.15um, 0.18um,0.25um, 0.35um0.15um, 0.25um

0.35um

0.35um

0.13um-Q3/020.13um-Q3/02

Bronzeb

b

b

b

b

b

b

b

b

b

Vendor

ARC International

ARC InternationalARC International

ARC InternationalARC InternationalARC InternationalARC International

ARC InternationalARMARM

ARM

ARM

ARMARMARM

Faraday

Faraday

Faraday

GlobalCAD

GlobalCAD

GlobalCAD

GlobalCADITCITCMentor

Mentor

32

VendorMentorMentorMIPS

PalmchipPalmchipSuperHSuperH

SynopsysTensilicaVirtual IP Group

Gold

0.25um

0.35um

Part NumberM8051WM8052

20KcFM-6251FM-6255SH-4

SH4-202DW_8051XtensaM8051TC

DescriptionFast 8-bit Microcontroller8-bit Microcontroller

High performance 64-bit Microprocessor core1 inch Micro-Drive, Ultra Low Power Portable, Controller1 inch Micro-Drive, Ultra Low Power Portable ControllerCPU Core, max. 300MHz

32-bit RISC-FPU Microprocessor Core, 266MHz8051 microcontroller32-bit Configurable RISC Micropro. Core8-bit MCU

Silver

0.13um-Q3/02

0.13um-Q3/020.13um-Q3/02

0.18um

Bronzeb

b

b

b

MICROPROCESSOR PERIPHERAL

Part Number

SBC-5 G2237 G2254 G2259

M146818M8237AM8254M8255

M8259AM85230

M85C30

Bronze

b

b

b

b

b

b

b

b

b

Silver

0.35um

0.35um0.35um

Gold Vendor3DSP

GlobalCADGlobalCADGlobalCADMentor

MentorMentorMentor

MentorMentor

Mentor

DescriptionOn-chip System Bus Controller

Programmable DMA Controller Programmable Timer/Counter Programmable Interrupt ControllerReal Time Clock

4 Channel DMA Controller3 Channel Counter-TimerParallel Peripheral Interface8 Channel Programmable Interrupt Controller

Enhanced Version of M85C30 Serial Comm.ControllerSerial Communications Controller w/FIFOs

MICROCONTROLLER AND MICROPROCESSOR

33

COMMUNICATIONS

Bronze

0.18um-Q3/02

Tapeout0.18um0.18um

b

b

b

b

b

b

b

b

Silver0.25um0.25um

0.35um

0.13um-Q3/020.13um

GoldPart NumberFEP110H90AFMACLVDSR80H80A

U104A

U108A

U110A252422842371

2452LDMWISPI4P2LDQSD1-13LDQSD6-13

10/100/1000 MACE1-DFRME1-KIT-R

Description100/10 Base Ethernet PHY VCC=2.5VEthernet 10/100 media access controller

LVDS ReceiverLVDS Transmitter

LVDS ReceiverDVI Receiver10/100 Ethernet MAC corePacket over Sonet Layer 3

SPI-4 level 110/100/1000 Ethernet MACSystem Packet Interface Level 4 (SPI-4) Phase 2:Quad 3.1Gbps SerDes TRX

Quad 2.5/3.1/5.0 Gbps SerDes10/100/1000 Mbps Ethernet MACE1 DeframerE1 Framing/Deframing Kit (Re-ordering Add/Drop)

VendorFaradayFaradayFaraday

FTDPL

FTDPL

FTDPLinSiliconinSiliconinSilicon

inSiliconLEDALEDALEDA

MentorMentorMentor

DSP

Part Number

SP-20SP-3SP-5

FD216FD220

D S P

ITC_UM13A3970_DPITC_UM13A397A_DPZSP400

ZSP500ZSP600FFT

Bronze

b

b

0.35um

0.25um

b

b

b

Silver

0.25um

0.25um,

0.35um

0.13um-Q3/02

0.13um-Q3/02

Gold

0.18um,0.35um

0.18um

Vendor3DSP3DSP3DSP

FaradayFaraday

GlobalCAD

ITCITC

LSILS ILS IMentor

Description1200 MIPS Digital Signal Processor200 MIPS Digital Signal Processor400 MIPS Digital Signal Processor

16-bit fixed point DSP24-bit fixed point DSP

Integrated 32-bit CPU and DSP, up to 100 MHzReal time MPEG2 decoder and encoderRADcore — Configurable DSP CoprocessorRADcore — Config. Coprocessor with AMBA AHB

16 bit Dual MAC DSP Processor16 bit Dual MAC High Performance DSP16 bit Quad MAC Media DSPFast Fourier Transform/Inverse FFT/Fast

Convolver

34

COMMUNICATIONS

Bronzeb

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Silver

0.18um, 0.13um-Q2/02

0.13um-Q4/02

0.35um

GoldPart Number

E1-KIT-SHDLC-COREHDLC-FIFOHDLCxN

PE_GMAC0PE-MACMIIT1-DFRMT1-E1-FRM

T1-KIT-RT1-KIT-SX50-RXX50-TX

MystiPHY110

SerDesSXPNA20-T1

Wipro802.11Wipro802.11aWipro802.11bWipro8023-1000

Wipro8023-1010WiproBthh/wWiproGMAC

DescriptionE1 Framing/Deframing Kit (Selective Add/Drop)Single Channel HDLC CoreSingle Channel HDLC with FIFO

Multi-Channel HDLC ControllerGigabit Ethernet MAC10/100 Mbps Dual-Speed Ethernet MACT1 Deframer

T1/E1 FramerT1 Framing/Deframing Kit (Re-ordering Add/Drop)T1 Framing/Deframing Kit (Selective Add/Drop)X50 Multiplexing Receiver

X50 Multiplexing Transmitter10/100 Mbps ETHERNET TX PHY

Quad 3.318Gbps Transceiver Core

HomePNA 2.0 Tranceiver802.11 MAC802.11a Baseband Controller Core802.11b Baseband Controller Core

10/100 Mbps Ethernet MAC10/100mbps Enthernet MAC+PCIBluetooth Hardware Baseband ControllerGigabit Ethernet MAC

VendorMentorMentor



MentorMentorMysticom

NurlogicSl iceXWiproWipro


Wipro

35

CONSUMER

Part NumberFJPEG2283

2429249225172518

DCT-8X8G711-CMPG711-EXPINT-DEINT

PRSDECPRSENCRSDECRSENC

TRELLISV42BISV CVITERBI

DescriptionJPEG encoderJPEG CODEC

DES and Triple DES EncryptionAES Encryption CoreJVXtreme Java Accelerator CoProcessorJPEG 2000 CODEC

8X8 Discrete Cosine TransformG711 PCM Compressing FunctionG711 PCM Expanding FunctionInterleaver/Deinterleaver

Programmable Reed-Solomon DecoderProgrammable Reed-Solomon EncoderReed Solomon DecoderReed Solomon Encoder

Trellis DecoderV.42bis Compression EngineVoice CodecViterbi Encoder/Decoder

Bronze

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

b

Silver Gold0.35um

VendorFaradayinSilicon





STORAGE

Bronzeb

b

b

b

b

b

b

b

b

b

Silver GoldPart NumberM765A78

M82092IDEM82371IDEM82801IDEMDDS78

MFDC78BK-3709-133BK-3709-33/66/100BK-3710-133

BK-3710-33/66/100

DescriptionFloppy Disk Controller

IDE Controller, ATA-1IDE Controller, ATA-4 (UDMA/33)IDE Controller, ATA-5 (UDMA/66)Digital Data Separator for Floppy/Tape

PC-AT Floppy Disk ControllerIDE Host Ultra ATA-133 w/o DMAIDE Host Ultra ATA-33/66/100 w/o DMAIDE Host Ultra ATA-133 with DMA

IDE Host Ultra ATA-33/66/100 with DMA

VendorMentor


MentorPalmchipPalmchipPalmchip

Palmchip

36

INTEGRATED PLATFORM

Part NumberA5001-EUIDP-1800DP-1845

802.11

BlueStream

(Baseband)

BlueStream(Radio)

G P S

InfoStream

MediaStream

DW_AMBA

Description

512-bit RSA Encryption AcceleratorConfigurable Storage-Connectivity SoC PlatformLinux Supported Configurable Storage-Connectiv-ity SoC Platform

802.11 a/b/g Mac’s, 802.11 a/g Baseband Phy’s,802.11 a/b/g dual mode Baseband PhyWireless IA platform - includes basebandcompatible with industry Standard Radio. Protocol

stack.Wireless IA platform in RF CMOS process

Complete GPS solution for Cellular and Telematic

application- Baseband, Software and RF. Meets911 reqt.PDA platform -designed with ARM9 processor-PLLs, multiple I/O’s, USB transceiver, touch

screen A/DSingle chip MP3 platform - includes DSP cores,I2C slave, PLL, and DMA controller.A 6 chaneelgeneral purpose audio processor designed for

audio decoding, processing, speech recognitionand voice coding.AMBA on-chip bus platform and peripherals

Bronze

b

b

b

b

Silver0.25um

0.18um

0.18um

Gold

0.18um

0.18um

0.18um

Vendor

AILPalmchipPalmchip

Parthus

Parthus

Parthus

Parthus

Parthus

Parthus

Synopsys

DESIGN-FOR-TEST

DescriptionBuilt-In Self-Test, Diagnosis and Repair of

embedded memoriesMemory BIST cores (RAM + ROM)

Bronze

b

Silver Gold0.18um

VendorGenesys Testware

Synopsys

Part NumberMBISTmaker

DW_membist

37

EMBEDDED NON-VOLATILE MACRO

EMBEDDED SRAM MACRO

Part Number

1T SRAM standard macro1T-SRAM

1T-SRAM-M

1T-SRAM-R

M1T0D5HU18PE64EM1T0D5LU15FE32EM1T1HU18PE64E

M1T2D5LU15FE64E

SRAM(6T)

Description6 additional spec available on request

MoSys 1T-SRAM® Ultra-dense Memory

MoSys 1T-SRAM® Ultra-dense Memory for Mobile

applications

MoSys 1T-SRAM® Ultra-dense Memory withTransparent Error Correction

1T-SRAM 0.5-Mbit 220Mhz 8KX641T-SRAM 0.5-Mbit 18Mhz 16KX321T-SRAM 1-Mbit 220Mhz 16KX641T-SRAM 2.5-Mbit 18Mhz 40KX64

6.4um2 cell size,2Mbit max size,100 MHz,HS/sync.15.8um2 cell size,512 Kbit max size,100 MHZ,HS/sync.15.8um2 cell size,512 Kbit max

size,Tacc=10ns,HS/async.4.0um2 cell size,2Mbit max size,100 MHz,HS/sync.4.17um 2 cell size,1Mbit max size,120MHz,HS/sync2.28um2 cell size,2Mbit max size, 133MHz, HS/

sync

Bronze Silver

0.18um,0.15um,

0.13um-Q2/020.18um,

0.15um,0.13um-Q2/020.13um-Q2/02

0.18um, Q3/020.15um, Q3/020.18um, Q3/020.15um, Q3/02

0.25um

0.18um0.15um0.13um

Vendor

MOSYSMOSYS

MOSYS

MOSYS

MOSYSMOSYSMOSYS

MOSYSUMCUMC

UMC

UMCUMC

UMC

Part Number

EEPROMEEPROMEPROMFlash

Description18.34um2 cell,16K max size

9.82um2 cell size,6.4K bit max size3.24um2 cell size,2M max size2um2 cell size,2M max size

Brone

0.25um

Silver

0.35um

Gold0.35um

0.5um

VendorUMC

UMCUMCUMC/PMC

Gold

0.35um

0.35um

38

EMBEDDED ARRAY

Part NumberVariCore

eASICore .13

eASICore .15

eASICore .18

eI/O .15

DescriptionHigh Efficient embedded FPGA core. Configuration

Vl8L4x4R-U, Vl8L4x2R-U, Vl8L2x2R-U, Vl8L4x4-U,Vl8L4x2-U, Vl8L4x1-U, Vl8L2x2-U, Vl8L2x1-U High density configurable logic core(60Kgate/mm2)with FPGA-like Time-to-Market

High density configurable logic core(45Kgate/mm2)with FPGA-like Time-to-MarketHigh density configurable logic core(30Kgate/mm2)with FPGA-like Time-to-Market

Single mask configurable I/O cell (can be configuredas INPUT, OUTPUT, BI-DIRECTIONAL, or SUPPLY)

Brone

b

Silver

0.18um

0.15um

0.18um

0.15um

Gold Vendor

Actel

eASIC

eASIC

eASIC

eASIC

MEMORY SUB-SYSTEM

Part Number

CG-7410

CG-7420

DW_memcntrl

DescriptionSDRAM Shared Memory Processor ( 32 bit, 8 Channels, 166Mhz, Flash, SRAM, SDRAM)

DDR Shared Memory Processor ( 32/64 bit, 8 Chan-nels, 400Mhz, ECC )Memory controller core (DRAM, SRAM, FLASH, ROM)

Brone

b

b

b

Silver Gold Vendor

Palmchip

Palmchip

Synopsys

39

Silicon Shuttle Program

Silicon Shuttle Schedule for 2002

G:Generic (standard logic process)0.25um, 1P5M, 2.5V/3.3V0.18um, 1P6M, 1.8V/3.3V0.15um, 1P7M, 1.5V/3.3V0.13um, 1P8M, 1.2V/3.3V90nm, 1P9M, 1.0V/2.5V

M:Mixed-mode process with MMC/RFCMOS0.25um, 1P5M, 2.5V/3.3V0.18um, 1P6M, 1.8V/3.3V0.13um, 1P8M, 1.2V/3.3V*S: Special Shuttle*G: Subcontract to Faraday

0.25um

0.18um

0.15um

0.13um

90nm

0.15um

Jan

M

M

Feb

M

G

G

Mar

M

G

Apr

M

G

G

M

May

M

G

Jun

M/*G

G

M

Jul

M

G

Aug

M

G

G

M

Sep

*G

M

G

*S

Oct

M

G

M

Nov

M

G

G

G

Dec

M/*G

G

M

R

Starting from March 2002, the 0.13um Silicon Shuttle program will offer capability for the “Fusion” process, a L130 designeroption that enables High Speed and Low Leakage to be combined onto a single chip.Customer database needs to be DRC-clean on the latest Calibre run-set.Test-chip size is 5000umx5000um.Customers must submit a completed GDS-II database, mask tooling form, and DRC report before the first business day of theshuttle launch month. Please check with your sales representative for the exact dates.For convenient application and prompt response for customers, UMC provide web-based on-line reservation and access toSilicon Shuttle status.For more information or to apply for the Silicon Shuttle program, please contact your UMC sales representative or [email protected]

Early silicon verification of your prototype designs is thekey to bringing your product to market ahead of the com-petition. However, running test silicon for today’s leadingedge technologies can be prohibitively expensive. UMC isaddressing these issues by enhancing its Silicon Shuttlemulti-project test wafer program for 2002. We have ex-panded the number of shuttle runs and technologies avail-able and now run each shuttle on UMC’s hot-lot scheduleto greatly reduce cycle time. The 2002 Silicon Shuttleprogram will introduce the unparalleled 0.13um L130 plat-

form and will also offer special shuttles targeted at ourmixed-signal and RF CMOS processes. In June 2002, UMCwill subcontract the 0.25um logic Silicon Shuttle serviceto Faraday and will begin offering mature shuttle processesto better meet customer’s time-to-market and economicalprototyping demands.

UMC’s Silicon Shuttle program will reduce your risk andcost by verifying your advanced designs, prototypes, IPs(digital/analog), cell libraries, and I/O’s in UMC silicon.

Process

8” wafer

12” wafer

40

IP Vendor Contact

Vendor

3DSPActelAILA R C

ARMArtisanDolphin TechnologyeASIC

Enabling TechnologyFaraday TechnologyFTDPLGenesys Testware

GlobalCADInfinite TechnologyInnovativeinSilicon

Leda SystemsLSI LogicMacroTech ResearchMentor Graphics

MIPSMosysMysticomNEL

NurlogicPalmchipParthusSarnoff

Silicon Design SolutionsSl iceXSuperHSynopsys

TensilicaTrue CircuitsVirage LogicVirtual IP Group

Virtual SiliconWipro Technologies

Websitewww.3dsp.comwww.actel.com

www.ailabo.co.jpwww.arccores.comwww.arm.comwww.artisan.com

www.dolphin-ic.comwww.easic.comwww.enablingtechnology.comwww.faraday-usa.com

www.ftdpl.com.sgwww.genesystest.comwww.gcadinc.comwww.itc-usa.com

www.isi96.comwww.insilicon.comwww.ledasystems.comwww.zsp.com

www.macrotechnic.comwww.mentor.comwww.mips.comwww.mosys.com

www.mysticom.comwww.nel.co.jpwww.nurlogic.comwww.palmchip.com

www.parthus.comwww.sarnoff.comwww.siliconcompiler.comwww.slicex.com

www.superh.comwww.synopsys.comwww.tensilica.comwww.truecircuits.com

www.viragelogic.comwww.virtualipgroup.comwww.virtual-silicon.comwww.wipro.com

Phone949-435-0600408-739-1010

(81)3-3320-6251408-437-3400408-579-2200408-734-5600

408-392-0012408-264-7128408-720-3310408-935-0888

(65)744-9789510-661-0791408-588-9600972-437-7800

650-934-0170408-894-1900408-275-1416408-433-6249

510-353-9666408-451-5660650-567-5000408-731-1800

650-210-8080(81)42-799-8537858-455-7570408-952-2000

408-514-2900609-734-2000408-586-9469801-474-1447

408-456-2034650-584-5000408-986-8000650-691-2500

510-360-8000408-733-3344408-548-2700408-249-6345

[email protected]@actel.com

[email protected]@[email protected]@artisan.com

[email protected]@[email protected]@faraday-usa.com

[email protected]@[email protected]@itc-usa.com

[email protected][email protected]@[email protected]

[email protected][email protected]@[email protected]

[email protected]@[email protected]@palmchip.com

[email protected]@[email protected]@slicex.com

[email protected]@[email protected]@truecircuits.com

[email protected]@[email protected]@wipro.com

LocationIrvine, CASunnyvale, CATokyo, Japan

San Jose, CALos Gatos, CASunnyvale, CASan Jose, CA

San Jose, CASunnyvale, CASanta Clara, CASingapore

Fremont, CASanta Clara, CARichardson, TXMountain View, CA

San Jose, CASan Jose, CAMilpitas, CAFremont, CA

San Jose, CAMountain View, CASunnyvale, CAMountain View, CA

Kanagawa, JapanSan Diege, CASan Jose, CASan Jose, CA

Princeton, NJMilpitas, CASalt Lake City, UTSan Jose, CA

Mountain View, CASanta Clara, CALos Altos, CAFremont, CA

Sunnyvale, CASunnyvale, CASanta Clara, CA

Gold IP - UMC Gold IP program continues to lead the foundry indus-try in the hardening of standard...

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