GNSS RF Front-End DATASHEET - Saphyrion · 2019. 1. 22. · SY1007 GNSS RF Front-End DS-SY1007 Rev....

Literature Number: DS-SY1007January 31, 2014

Rev. 1.4

SY1007

GNSS RF Front-End

DATASHEET

www.saphyrion.ch

DATASHEET SY1007 GNSS RF Front-End

Document Team

Author Francesco Piazza Reviewers Lorenzo MoriggiaChristian IeraMariano PernaAngelo Consoli

Revision History

Rev. Date Who Description1.0 September 16, 2009 fp SPH document created, loosely derived from previous versions.1.1 November 26, 2009 fp Expanded all sections (based on customer support requests).1.2 October 4, 2011 fp Corrected errors and typos, added new sections (10 to 15).1.3 August 19, 2013 fp Extended Sections 4, 5, 7 and 13, corrected typos (all sections),

added application example (Section 16).1.4 January 31, 2014 fp Re-characterization of the VCOs: updated VCOs tuning curves

and phase noise specs, added VCOs phase noise graph. Addedhandling precautions (Section 14), corrected IF PLL range.

Contents

1 General Description 1

2 Features 1

3 Applications 1

4 Absolute Maximum Ratings 2

5 Electrical Characteristics 2

6 Device Marking 4

7 Typical Operating Characteristics 5

8 Pin Description 6

9 Equivalent Circuits 7

10 Circuit Description 9

11 Serial Interface 10

12 Register File 11

13 Applications Information 12

14 Handling Precautions 17

15 Radiation Tolerance 17

16 Application Example 18

17 Layout Recommendations 21

18 PCB Recommendations 21

19 Mounting Recommendations 22

20 Package Drawing 23

ii Saphyrion Sagl Rev. 1.4, January 31, 2014

SY1007 GNSS RF Front-End

DS-SY1007 Rev. 1.4 - January 31, 2014 DATASHEET

1 General Description

The SY1007 is a radiation hardened L-band RF downcon-verter for GNSS receivers aimed at the professional andspace markets. This device is designed in a 0.35µm SiGeprocess and includes all functional blocks needed to im-plement the complete RF front-end of multiband GNSS re-ceivers, thus allowing a substantial reduction of BOM, sizeand weight with respect to discrete designs. It directly inter-faces to the ESA AGGA-4 GNSS base-band processor.

The SY1007 is a programmable dual conversion super-heterodyne receiver. Both the RF and the IF local oscillatorscan be independently programmed to accommodate variousfrequency plans. It can be configured to receive all GPS,all GLONASS and most Galileo signals in the L-band up toa bandwidth of 24MHz by selecting the appropriate externalcomponents and configuring the RF and IF PLLs. The outputis analog quadrature (I/Q) at base-band. Four low latencypower down modes are provided to aid in implementing dif-ferent power saving schemes.

Since the SY1007 mainly targets the space market, avariant qualified to ESA ESCC9000 for satellite applicationsis available. This variant has demonstrated latch-up and ra-diation damage free operation. The SY1007 comes into acompact 6mm x 6mm ceramic-metal hermetic BGA packagecontaining no organic materials.

2 Features

• Complete, highly integrated RF front-end. Supports allGNSS signals up to 24MHz bandwidth.

• Compact, low bill-of-materials, small PCB area.• Low voltage operation, low power consumption.

– AVDD: 2.4V to 3.6V, DVDD: 2.2V to 3.6V.– Fully active: 12.3mA– Stand-by: 3.3mA– Doze: 280µA– Sleep: < 1µA

• Supports passive and active antennas.• Flexible 2MHz to 5MHz reference frequency.• Analog quadrature I/Q outputs.• Compact 6mm x 6mm ceramic-metal BGA package.

3 Applications

• Space-borne GNSS receivers.• Precise orbit determination.• Antenna arrays, beam forming, attitude determination.• Multi-frequency precision/monitoring GNSS receivers.• Reliable GNSS receivers, safety of life.

Figure 1: SY1007 Block Diagram.

RFLoopfilter

IFLoopfilter

SAW

RF-Filter IF-Filter 1 IF-Filter 2

RF LOinductor

IF LOinductor

SAWor LC

RFin

GNSSAntenna

C1

L1

L2

L3L4

L5 L6

C2

C3

C4 C5

C7 C8

C9

C10

C11

C12

To

AD

C, b

ase-

band

pro

cess

or

R1 R2

C6

:2 :N2

PFC

log:N1

PFC

LNI

LNO

RF

N

OIP

OIN

OQP

OQN

AGCI

VB

VBG

RE

NB

IEN

B

RL1 RL2 IL1 IL2RP

LL

IPLLDIO

RCP

AVDD DVDD

LPF(15MHz)

I

Q

DBMLNA VGA

RF

P

MIX

N

MIX

P

IF1N

IF1P

IF2N

IF2P

SY1007R

:4

bias

reg

AVSSDVSS

:2I Q

DBM

DBM

IF-Amp

Buffers

RFVCO

IFVCO

AVDDDVDD

A1

A2

A3

A4A5A6 B1

B2

B3B4B5B6

C1

C2

C3 C4

C5

C6

D1

D2

D3 D4D5

D6

E1 E2E3 E4

E5

E6

F1

F2

F3 F4F5

F6

Copyright c© 2014 Saphyrion SAGL. All Rights Reserved. All trademarks and registered trademarks are the property of their respectiveowners. Saphyrion SAGL reserves the right to change the detail specifications as may be required to permit improvements in the designof its products. Saphyrion SAGL assumes no responsibility for this product’s use, nor for any infringement of patents or other rights fromthird parties which may result from its use. No license is implied under any patent or patent right by Saphyrion SAGL.

Saphyrion SAGL, CH-6934 Bioggio, Switzerland, http://www.saphyrion.ch 1


4 Absolute Maximum Ratings

Max. supply voltage, AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 4.0VMax. RF input on LNI, RFx . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10dBmESD susceptibility, HBM, JESD22-A114 . . . . . . . . . .Class 1B, 1KVContinuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mWCurrent on any pin except LNI, RFx . . . . . . . . . . . . . . . . . . . . . . ±1mACurrent on supply and VB pins . . . . . . . . . . . . . . . . . . . . . . . . . .±50mACurrent on VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

Operating junction temperature . . . . . . . . . . . . . . . . . −55 to +125CStorage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65 to +150CLead temperature (soldering, 40s) . . . . . . . . . . . . . . . . . . . . . . . . 240CVoltage on any pin except LNI, RFx . . . . . . . . . .−0.3V / xVDD+0.3Voltage on LNI (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.3VVoltage on RFx (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.5V

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Absolute maximum ratings areshort term stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the recommendedoperating conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

ESD sensitive device: Use proper precautions when handling this device.

Pb Device contains lead: Product is not RoHS compliant and shall be handled accordingly. Do not disperse into the environment.

5 Electrical Characteristics

AVDD = 2.4V to 3.6V, DVDD = 2.2V to AVDD+0.2V, f(RCP) = 2.0MHz, Tjunction = −40C to +125C, no load, unless otherwise stated. Allvoltages are referred to their respective VSS. Typical values are at AVDD = 3.0V, DVDD = 3.0V, Tjunction = +25C.

Parameter Conditions Min Typ Max Unit Notes

LNAPower gain 1575MHz, noise matched 18.2 18.9 25.0 dB 2

1575MHz, Z-matched 20 dB 2Noise figure 1575MHz, noise matched 1.6 1.8 dB 2

1575MHz, Z-matched 4.5 dB 21dB compression point Input referred −24 −23 −20 dBm 2Group delay Noise matched 1.19 1.25 1.29 ns 2Third order intercept IP3, Input referred −14 −10 dBm 2Input refl. coefficient S11, noise matched −2 dB 2

S11, Z-matched −15 dB 2Output refl. coefficient S22 −12 dB 2

RF Mixer and 1st IF Stage

Conversion voltage gain To MIXP-MIXN, no load 14 15 16 dB 3To IF1P-IF1N, no load 24 26 29 dB 3

SSB noise figure Differential output 11.0 13.5 dB1dB compression point Input referred, to MIXP-MIXN −16 −13 dBm 3Third order intercept Input referred, to MIXP-MIXN −3 dBm 3Input refl. coefficient S11 at 1.5742 GHz −15 dBDifferential resistances MIXP to MIXN 500 600 720 Ω 4

IF1P to IF1N 500 600 720 Ω 4IF2P to IF2N 54 65 81 kΩ 4

Diff. capacitance MIX, IF1 and IF2 0.5 pF

IF Amplifier and Base-Band Section

VCA voltage gain I/Q output, V(AGCI) ≥ 2V 64 66 dB 5VCA gain control range V(AGCI) = 0.3V to 2V, Fig. 8 50 80 dB 5VCA sensitivity pin AGCI 6 9 12 mV/dB 5DC output voltage I/Q to AVSS, VDD=2.5V 1.5 1.8 2.1 VDC offset voltage I/Q outputs −30 +30 mVOutput signal amplitude ≤ 1dB compression 1.4 1.8 VppIF amp bandwidth 10 400 MHzI/Q 3dB Bandwidth Internal low-pass filter 12 15 18 MHzI/Q output Impedance See note 6! 120 125 150 Ω 6I/Q load capacitance No bandwidth reduction 10 pF

2 Saphyrion Sagl Rev. 1.4, January 31, 2014



Local Oscillator, RF PLL

VCO frequency range L=4.7nH between RL1 & RL2 1.35 1.50 GHz 14VCO sensitivity L=4.7nH between RL1 & RL2 740 880 1050 MHz/V 14Main PLL divider range 64 255Charge Pump Current Pin RPLL 42 50 63 µAPLL SSB phase noise 100Hz offset −58 dBc/Hz 7,14

1kHz offset −66 dBc/Hz 7,1410kHz offset −68 dBc/Hz 7,14100kHz offset −70 dBc/Hz 7,141MHz offset −100 dBc/Hz 7,14

PLL spurs Recommended loop filter −40 dBcExt. RF LO amplitude Between RL1 & RL2, RENB=1 −17 +5 dBu 15Ext. RF LO resistance Between RL1 & RL2, RENB=1 10 kΩExt. RF LO capacitance Between RL1 & RL2, RENB=1 1.5 pF

Local Oscillator, IF PLL

VCO frequency range L=47nH between IL1 & IL2 360 420 MHz 16,17VCO sensitivity L=47nH between IL1 & IL2 160 250 298 MHz/V 16,17Main PLL divider range 32 255Charge Pump Current Pin IPLL 42 50 63 µAPLL SSB phase noise 100Hz offset −78 dBc/Hz 7,16

1kHz offset −86 dBc/Hz 7,1610kHz offset −88 dBc/Hz 7,16100kHz offset −95 dBc/Hz 7,161MHz offset −110 dBc/Hz 7,16

PLL spurs Recommended loop filter −60 dBc 7Ext. IF VCO amplitude Between IL1 & IL2, IENB=1 −17 +5 dBu 15,17Ext. IF VCO resistance Between IL1 & IL2, IENB=1 10 kΩExt. IF VCO capacitance Between IL1 & IL2, IENB=1 2.0 pF

Voltage Regulator

Band-gap voltage No load 1.12 1.17 1.22 VBand-gap output current 200 µA 8Band-gap load regulation I(VGB) = 0 to −200µA 2 5 mVRegulator output voltage No load 1.8 1.9 2.0 VRegulator line regulation AVDD 2.4V to 3.6V 4 10 mVRegulator output current 1 mA 8Regulator load regulation I(VB) = 0 to −4mA 7 15 mV 9

Digital Interface

Reference Freq. Range 1.9 5 MHzInput capacitance RCP and DIO 1.0 pFInput high level 0.7 DVDD DVDD+0.2 VInput low level −0.2 0.3 DVDD VOutput high level I(OH) = −1mA 0.9 DVDD VOutput low level I(OL) = +1mA 0.1 DVDD VOutput rise time C(LOAD) = 5pF 3.4 6.1 ns 10Output fall time C(LOAD) = 5pF 2.8 4.8 ns 10

Power Supply

Supply Voltage Analog AVDD 2.4 3.6 VDigital DVDD 2.2 AVDD+0.2 V

Supply Current Fully active AVDD 9.5 12.5 19.0 mA 11DVDD 20 40 80 µA

Stand-by AVDD 2.0 3.3 5.5 mA 11DVDD 20 40 80 µA

Doze AVDD 180 280 380 µA 11DVDD 2 5 10 µA

Sleep AVDD/DVDD 100 nA 11

Rev. 1.4, January 31, 2014 Saphyrion Sagl 3



Thermal CharacteristicsOperating temp. range Guaranteed performance −40 +125 C

No degradation −55 +125 CThermal resistance Rth Junction to case 25 C/W

Radiation CharacteristicsTotal dose (C60) 100 kRad(Si)Dose rate (C60) 12 Rad/min

LET No latch-up 45 MeV cm2

mg 18

Notes

Note 1: LNI and RFx pins shall be AC coupled. Setting LNI to 0V disables the LNA. Shorting RFx to VSS will damage the device.Note 2: LNA with recommended input and output matching networks (see section 13.3.1).Note 3: Voltage conversion gain, differential, input is RFP-RFN, output as indicated, unloaded.Note 4: I/O impedances track to 5% or better.Note 5: Voltage gain, from IF2P-IF2N, differential, to OIP-OIN or OQP-OQN, also differential.Note 6: Caution: OIP-OIN and OQP-OQN shall not be loaded with less than 10kΩ, or severe distortion and amplitude limiting will occur.Note 7: Closed PLL loop, with 33µF decoupling capacitors on VBG pins to reduce noise of bias circuit.Note 8: Minimum current available to an external load under worst-case conditions.Note 9: Doze mode, internal loads are turned off.Note 10: Measured between the 10% and 90% points. Load capacitance on these pins must be minimized (preferably below 5pF).Note 11: Supply current increases with temperature (see Figure 12).Note 12: Minimum and maximum frequency allowed.Note 13: Voltage range needed to guarantee full AGC regulation.Note 14: With L = 4.7nH, muRata LQW18, reference test board. Other frequency ranges may be obtained using different inductor values.Note 15: Referred to 50Ω (0dBu=223.6mV). Signal levels between −8dBu and 0dBu give the best, most stable performances.Note 16: With L = 47nH, muRata LQW18, reference test board. Other frequency ranges may be obtained using different inductor values.Note 17: IF local oscillator frequency is half the VCO frequency, i.e. f(LO) = f(VCO)/2 (see Section 10).Note 18: DUTs have been tested at 85C and xVDD=3.6V until a cumulated fluence of 1E+7 ions/cm2 without detecting any latch-up.

6 Device Marking

The marking of the device is in accordance with the requirements of ESCC Basic Specification No. 21700. The informationto be marked on the component shall as a minimum be:

• Terminal identification.• Component number.• Traceability information.

Engineering model marking may occasionally deviate from the specification shown here. Please consult with Saphyrion incase of doubt.

SY1007R – Engineering Model (EM) Marking

A1 dot and die part number: 07=SY1007.

YYWW = Year and week of sealing.

R = EM part, xxx = Unique serial number.

07YYWW

Rxxx

SY1007S – Flight Model (FM) Marking

A1 dot and die part number: 07=SY1007.

YYWW = Year and week of sealing.

S = FM part, xxx = Unique serial number.

07YYWW

Sxxx



7 Typical Operating Characteristics

Figure 2: LNA Gain and NF.

1

2

20

NF

(dB

)

1.0 1.2

5

1.4 1.6 1.8 2.0Frequency (GHz)

Gai

n (d

B)

1.5

10

15

LNA noise matched at 1.57GHz

Figure 3: LNA Linearity

Pou

t (dB

m)

-40 0-20Pin (dBm)

-10-30

+20

0

-20

-40

-60

-80-50

CP

IP3

Figure 4: LNA S11 and S22

S11

-S22

(dB

)

1.2 1.6Frequency [GHz]

2.01.4

-5

-10

-15

-30

-25

1.0

0

+5

+10

-301.8

S11S22

Figure 5: RF Mixer Gain

0

10

30

Vol

tage

Gai

n (d

B)

-60 -30 120

20

0 30 60 90Temperature (°C)

To MIXP-MIXN

To IF1P-IF1N

Figure 6: RF Mixer Linearity

Vou

t (dB

u)

-40 0-20Pin (dBm)

+10-10-30

+30

+10

-10

-30

-50

-70

CP

IP3

Figure 7: LNA S21 and S12

S21

-S12

(dB

)1.2 1.6

Frequency [GHz]2.01.4

0.0

-10

-20

-30

-40

1.0

+10

+20

+30

-501.8

S21S12

Figure 8: IF Amp Gain vs. AGC

-60

90

Gai

n (d

B)

3AGC Voltage (V)

0

-30

0

30

60

1 2

85°C

-40°C

27°C

-55°C

125°C

Figure 9: RF VCO tuning curve

Fre

quen

cy (

GH

z)

0.5 2.51.5Tuning Voltage (V)

2.01.0

1.65

1.60

1.45

0.0

1.55

1.50

1.40

1.35

1.30

1.25

-40°C25°C125°C

2.4V3.0V

3.6V

L(RF) = 4.7nH

Figure 10: IF VCO tuning curve

Fre

quen

cy (

MH

z)

0.5 2.51.5Tuning Voltage (V)

2.01.0

230

220

190

0.0

210

200

180

170

160

-40°C25°C125°C

L(IF) = 47nH

2.4V

3.0V3.6V

IF LO frequency is shown (VCO is at 2x LO frequency).

Figure 11: VCOs phase noise

Pha

se n

oise

(dB

c/H

z)

1 10k100Frequency offset (Hz)

100k1k10

-20

-40

-60

-80

-100

-1201M

RF-LO

IF-LO

f(RF-LO) = 1400MHz f(IF-LO) = 185MHzf(RCP) = 2.0MHz

Figure 12: I(AVDD) vs. Temp.

18

6

14

I

(m

A)

-60 -30 120

10

0 30 60 90Temperature (°C)

AV

DD

16

12

8

2.4V

3.6V

Figure 13: VBG/VB vs. Temp.

1.181

1.914

Out

put V

olta

ge (

V)

-40 -20 800 20 40 60Temperature (°C)

1.910

1.184

VB

VBG



8 Pin Description

A

1

B

C

D

E

F

2 3 4 5 6

Figure 14: SY1007 pin-out (top view).

Name Ball Domain DescriptionRCP A1 DVDD External reference clock.DIO A2 DVDD Digital input output interface, needs a weak pull down. Test: scan output.

AGCI A3 AVDD Set the AGC IF conversion gain, to be connected to a decoupling capacitor.IF2P A4 AVDD IF VGA positive input.IF1P A5 AVDD First IF amplifier positive output.MIXP A6 AVDD RF mixer IF positive output.DVDD B1 - Positive digital supply voltage.DVSS B2 - Negative digital supply voltage.IF2N B3 AVDD IF VGA negative input.IF1N B4 AVDD First IF amplifier negative output.MIXN B5 AVDD RF mixer IF negative output.RFP B6 AVDD Radio frequency positive mixer input.OQP C1 AVDD Quadrature base-band GNSS positive signal.OQN C2 AVDD Quadrature base-band GNSS negative signal.AVSS C3 - Negative analog supply voltage.AVSS C4 - Negative analog supply voltage.RFN C5 AVDD Radio frequency negative mixer input.AVSS C6 - Negative analog supply voltage.OIP D1 AVDD In-phase base-band GNSS positive signal.OIN D2 AVDD In-phase base-band GNSS negative signal.

AVSS D3 - Negative analog supply voltage.AVSS D4 - Negative analog supply voltage.RENB D5 AVDD RF PLL enable – active low. Test: scan enable (SE).LNO D6 AVDD LNA output.IL1 E1 AVDD IF VCO tank-circuit – first terminal.

IPLL E2 AVDD IF PLL loop filter.RPLL E3 AVDD Output of the PLL phase frequency comparator, connect to the output filter.IENB E4 AVDD IF PLL enable – active low. Test: scan input (SI).VBG E5 AVDD Band-gap voltage reference output, 1.2V. Decouple to AVSS close to the chip.

AVDD E6 - Positive analog supply voltage.IL2 F1 AVDD IF VCO tank-circuit – second terminal.VB F2 AVDD Voltage regulator output, 1.9V. Decouple to AVSS close to the chip.RL1 F3 AVDD RF VCO tank-circuit – first terminal.RL2 F4 AVDD RF VCO tank-circuit – second terminal.

AVSS F5 - Negative analog supply voltage.LNI F6 AVDD LNA input.



9 Equivalent Circuits

Pin Description Equivalent circuit

A1 RCP Digital inputs and outputs DVDD

DVSS

DIO

ESD

ESDRENB, IENB,RCP, DIO

ESD

ESD

xVDD

xVSS

A2 DIOD5 RENBE4 IENB

E3 RPLL PLL charge pump outputs

ESD

RPLLIPLL

AVDD

UP

DN

AVSS

CLAMP

50µA

50µA

E2 IPLL

F6 LNI LNA input and output

LNI

AVSS

ESD

AVDD

bias-1

bias-218k

LNO

ESD

ESD500D6 LNO

B6 RFP RF mixer input

RFPBias

AVSS

AVDD

RFN

ESD

ESD

ESD

ESD

C5 RFN (internally matched to 50Ω)

A6 MIXP IF input/output

ESD

ESD

ESD

ESD

AVDD

AVSS

MixerIF-amp

300Ω 300Ω

MIXN,IF1N

MIXP,IF1P

B5 MIXNA5 IF1PB4 IF1N



Pin Description Equivalent circuit

A4 IF2P IF VCA input (AGC)

ESD

ESD

IF2P

ESD ESD

ESD

ESD

IF2N

AVDD

AVSS

VBG

65kΩ 65kΩ

B3 IF2N

A3 AGC AGC control circuit, gain control input

AGCI

ESD

ESD

AVSS

AVDD

C1 OQP Quadrature I/Q base-band outputs

OIPOQP

ESD

ESD

OINOQN

AVDD

AVSS

C2 OQND1 OIPD2 OIN

F3 RL1 RF and IF voltage controlled oscillators

ESD

ESD

ESD

ESD

AVDD

AVSS

RL2IL2

RL1IL1

RPLLIPLL

F4 RL2E1 IL1F1 IL2



10 Circuit Description

The SY1007 is a radiation hardened super-heterodyne RFfront-end for GNSS receivers aimed at aerospace applica-tions. It offers a high degree of versatility and can be con-figured to receive all GPS, all GLONASS and most Galileosignals in the L-band up to a bandwidth of 24MHz by se-lecting the appropriate external components and configur-ing the RF and IF PLLs. The output is base-band analogI/Q. All active building blocks needed to construct a GNSSRF receiver channel are included on-chip. RF and IF filtersare external to the chip such that their bandwidth and ordercan be selected to suit the needs of various applications.

10.1 LNA

The LNA is a single stage cascode amplifier. It requires ex-ternal matching networks at both its input and output andcan be configured for all GNSS frequencies by adjustingthe matching networks. It provides about 20dB gain and1.6dB NF under noise matching conditions. Pin LNI is theLNA input, is biased to about 0.7V and shall be AC cou-pled. Pin LNO is the output of the LNA and needs to bebiased at AVDD. If desired the LNA can be disabled per-manently by connecting its input to AVSS. In that case anexternal LNA is needed.

10.2 RF Mixer

The RF mixer converts the RF signal to the 1st IF. Themixer is double-balanced, provides a voltage gain of 15dBand a SSB noise figure of 11dB. The input is balanced andprovides a broad-band 50Ω impedance to directly matchtypical SAW filters for GNSS use. The output of the mixeris balanced, has an impedance of 600Ω and is meant tobe connected to an LC tank-circuit (part of the IF filter).It is directly connected to the 1st IF amplifier stage inter-nally. The local oscillator signal is either generated by theon-chip RF-VCO or can be supplied externally to the pinsRL1 and RL2 as a differential signal.

10.3 IF-Strip

The IF-strip consists of a fixed gain (11dB) amplifier fol-lowed by a 3-stage variable gain IF amplifier with logarith-mic (dB-linear) gain control. A differential amplifier struc-ture has been used to achieve rejection to common modesignals. The input of the fixed gain stage is connected tothe mixer, while the 600Ω output is available on pins IF1Pand IF1N, which are meant to be connected to the 2nd sec-tion of the LC IF-filter. The variable gain amplifier providesabout 45dB gain and ≥ 50dB control range. The input isbalanced, has an impedance of about 65kΩ and is biasedat 1.2V by the band-gap voltage reference. The output isinternally connected to the following stages and is not ac-cessible externally.

10.4 I/Q Downconverter

The I/Q downconverter converts the output of the IF-stripto a base-band signal. This quadrature downconvertedsignal is then low-pass filtered by a 3rd order Bessel activefilter with 15MHz bandwidth, amplified by 12dB and output

as a vectorial I/Q signal on pins OIP, OIN, OQP and OQN.In order to obtain an accurate I/Q output the quadrature LOsignal is obtained with a divider-by-2. In consequence, theIF-VCO frequency shall always be set to 2x the requiredLO frequency to compensate this division. The VCO sig-nal can be generated either by the on-chip IF-VCO or canbe supplied by an external PLL to pins IL1 and IL2 as adifferential signal. Pin IENB selects between internal PLL(IENB = 0) and external LO signal (IENB = 1).

10.5 RF and IF PLLs

The SY1007 requires 2 local oscillator signals: one for theRF and a second one for the IF downconverters. Thesesignals can be either generated by the on-chip RF and IFlocal oscillators or supplied externally. The VCOs are bal-anced LC oscillators and require one external coil.

Loop FilterRF

Mixer

(Register)

VCO

:4

LO

N(64-255)

RCP

Loop Filter I/QMixers

(Register)

VCO

2xLO

RCP

N(4-255)

:2 :2

Figure 15: SY1007’s RF and I/Q PLL configuration.

The integer-N PLLs are independent from each otherand can be programmed via the serial interface. They bothuse the clock signal applied to pin RCP as reference. Theiroutput frequency is calculated as follows (see figure 15):

• RF PLL: f(RF-LO) = 4*N1*f(RCP); 64≤N1≤255.

• IF PLL: f(IF-LO) = N2*f(RCP)⇒ f(IF-VCO) = 2*N2*f(RCP); 32≤N2≤255.

The CRC loop filters shall be connected to pins RPLL andIPLL respectively. The RF and IF PLLs can be enabled in-dependently by setting pins RENB and IENB to logic low.When disabled (pins xENB to logic high) the balanced ex-ternal local oscillator signals shall be applied to pins RL1-RL2 and IL1-IL2 respectively while pins RPLL and IPLLshall be left open. The PLL enable pins RENB and IENBare also used as test inputs by the testability logic.

10.6 Band-Gap Reference

It is a band-gap voltage reference generating approxi-mately 1.17V. It is used by most analog blocks and its out-put is available on pin VBG. It is able to source up to 200µAbut can sink a couple µA at most. It requires an externalcapacitor ≥1µF for stability, although larger capacitors arerecommended to reduce noise voltage.

10.7 LDO Voltage Regulator

It is a linear low drop-out voltage regulator meant to gen-erate the supply voltage for the parts of the SY1007 thatare sensitive to power supply noise and ripple (mainly the



PLL). The nominal output voltage is 1.9V. A ≥1µF capac-itor – which can be increased without limit – is requiredfor stability. The LDO is able to source up to 15mA andits output is the VB pin. Although not explicitely meant tosupply external loads, the LDO can power external circuitsconsuming up to 1mA, provided that they don’t generatepower supply noise that would disturb the internal SY1007sensitive parts.

10.8 Serial Bus and Register File

A configuration register, accessible via a single-wire serialinterface, is implemented on the SY1007. Its purpose is toconfigure the RF and IF PLLs and control the power modesof the device. The register is protected against SEU with aHamming error correction mechanism.

11 Serial Interface

The SY1007 can be programmed via a single wire syn-chronous interface. The following can be accessedthrough the serial interface:

• Power modes;• RF PLL main divider;• IF PLL main divider.

All registers are read/write in order to allow readingback their contents for verification purposes. In case anerror is detected (may happen only under a high radiationenvironment) the affected register needs to be rewritten.

11.1 Communications Protocol

Communication to the SY1007 occurs through a single-wire synchronous bidirectional interface (pin DIO) that issynchronous to RCP. The SY1007 works as a slave andnever initiates a communication.

A communication always consists of packets of twoblocks: a control word and a data byte. Figure 17 showsa write and a read packet respectively. A packet consistsof a start bit, followed by 6 bits (read) or 7 bits (write) de-pending on the operation requested, then by 8 data bits.The master device cannot abort an on-going packet. Anaborted packet may cause register corruption.

The control word – always sent by the master device(typically a SY1017) – specifies the kind of operation re-quired (read or write) and the address of the register to beaccessed. A communication is initiated by setting the DIOpin to logic 1 for one clock cycle. A parity bit (odd parity) isrequired, and in case a parity error occurs the operation is

aborted. The second 8-bit block contains the data read orwritten to the selected register, in LSB-first form.

Back-to-back communications (no idle cycles betweentwo consecutive communications) are supported. If DIO ispulled high immediately after the completion of the previ-ous communication, the SY1007 accepts a new communi-cation already at the clock cycle following the last data bit(bit D7).

11.2 Timing Diagram

The SY1007 samples the DIO line on the falling edgeof RCP. If requested to return data (read operation), theSY1007 will drive DIO and send data bits on RCP fallingedge. At the end of a communication the DIO line goeslow, the interface then remains idle as long as the DIO lineis kept low. Figure 16, and tables 5 and 6 show the timingdiagram of the serial interface.

D6

T WR

D7D4 D5

D6D4 D5A0 D7

T WR A0

tcp

tsu

tr

tpd tpZ

tf

RCP

DIO(W)

DIO(R)

Figure 16: Serial interface timing diagram.

Name Parameter Min Typ Max Unittcp Clock cycle time 200 nstsu Setup time 15 nsth Hold time 0 nstpdLH Propagation delay L→H 4.0 8.5 nstpdHL Propagation delay H→L 5.5 7.6 nstpZ Propagation delay to Z 4.0 7.0 nstr Output rise time, 10-90% 3.6 6.1 nstf Output fall time, 90-10% 3.3 4.8 ns

Table 5: Conditions: 2.2V, 125C, Cl=5pF.

Name Parameter Min Typ Max Unittcp Clock cycle time 200 nstsu Setup time 10 nsth Hold time 0 nstpdLH Propagation delay L→H 2.4 6.4 nstpdHL Propagation delay H→L 4.0 5.7 nstpZ Propagation delay to Z 2.4 5.5 nstr Output rise time, 10-90% 3.4 4.9 nstf Output fall time, 90-10% 2.8 3.8 ns

Table 6: Conditions: 3.0V, 125C, Cl=5pF.

RCP

DIO(W)

DIO(R) A1ST WR D7A2 P D1 D2 D3 D4 D5 D6R D0A0

A1ST WR D7A0 A2 P R R D0 D1 D2 D3 D4 D5 D6

Figure 17: SY1007 read and write packets.



11.3 Packet Structure

A packet consists of 2 blocks: a control word followed bya data byte. The structure of the control word is shown intable 7 and the meaning of the various fields in the controlword is shown in table 8.

Field Start WR Addr P Res DataPosition 0 1 2:4 5 6(7) 8:15

Table 7: Structure of the control word.

Field DescriptionStart Must go HIGH to start communication.WR Transfer direction:

0 : READ operation.1 : WRITE operation.

Addr[0:2] Register address, LSB first (see table 9).P Parity. It is calculated on Start bit, Write and Ad-

dress fields. Parity is ODD, i.e. the number of 1’s inbits [4:0] of the control word must be odd.

Res Reserved (1 bit for read, 2 bit for write).Data[0:7] Write operation: the master sends the data to be

written in register.Read operation: the SY1007 returns the registercontent.

Table 8: Description of the control word.

11.4 Parity Check

As a means to prevent registers corruption during write un-der a high radiation environment, parity check is performedon the control word. Parity is calculated on the valid fieldsof the control word, i.e. Start, WR and Addr[0:2]. TheRes[0:1] bits are not used to calculate parity. The expectedparity type is odd, i.e. the total number of 1’s in bits [0:5] ofthe control word must be odd. If a parity error is detectedduring a write operation, e.g. a SEU occurs, that operationis immediately aborted, i.e. the data is discarded and thecorresponding register is not updated.

The parity bit is ignored during a read operation,i.e. the data is returned regardless of the value of the paritybit. It is highly recommended that every write is followed bya read operation to verify that the write actually succeededand that the written value is the intended one.

12 Register File

12.1 Register Map

The register map is reported in table 9. Register loca-tions marked as Reserved are reserved for future develop-ments. To maintain compatibility with new releases of theSY1007 no attempt should be made to access these loca-tions. While in the current release an attempt to access

these locations results in no operation, in future versions itcould results in temporary malfunctions.

AddressRW A0 A1 A2 Dir Register

0 0 0 0 R RF-PLL (8-bit)0 0 0 1 R Reserved0 0 1 0 R Pwr-Modes (2-bit)0 0 1 1 R Reserved0 1 0 0 R IF-PLL (8-bit)0 1 0 1 R Reserved0 1 1 0 R Reserved0 1 1 1 R Reserved1 0 0 0 W RF-PLL (8-bit)1 0 0 1 W Reserved1 0 1 0 W Pwr-Modes (2-bit)1 0 1 1 W Reserved1 1 0 0 W IF-PLL (8-bit)1 1 0 1 W Reserved1 1 1 0 W Reserved1 1 1 1 W Reserved

Table 9: Register map.

12.2 Register Fields

The meaning of the fields of all registers is shown in ta-ble 10. The fields marked as Reserved are reserved forfuture developments. To maintain compatibility with newreleases of the SY1007 it is recommended that these fieldsare written with zeros. When read back these fields returnzeros. The content of all registers is undefined until writ-ten, there is no default value.

12.3 Hamming Error Correction

As a means to protect the register’s content from singleevent upset (SEU) errors that may occur under high radia-tion, Hamming error correction has been implemented onall registers. This error correction mechanism is able tocorrect up to one error per register per clock cycle.

To implement Hamming error correction 12-bit regis-ters are used, as shown in figure 18. Each register holdsthe actual data value and 4 check-sum bits. During a reg-ister write cycle the new check-sum is computed by thegeneration matrix and stored in the register together withthe actual data.

Error-correction occurs on each clock cycle (exceptduring register write cycle). The correction matrix com-putes corrected data out of the data stored in the 12 bitregisters and rewrites it back at the following clock fallingedge, thus removing any single SEU error. Every registerhas its independent error correction system, thus severalsimultaneous errors will be corrected as long as they occurin different registers.

Register Bits Count Field Description TypePwr-Modes 0:1 2 Power Modes 00=Sleep RW

01=Doze11=Stand-By10=Fully active

2:7 6 (Reserved) Currently ignored, set to 0 N/ARF-PLL 0:7 8 RF-PLL Divider RF-PLL division factor: RW

D020+ D121

+ · · ·+ D727

IF-PLL 0:7 8 IF-PLL Divider IF-PLL division factor: RWD020

+ D121+ · · ·+ D727

Table 10: Register fields description.



ErrorCorrection

HammingCode

Generator

HammingCode [3:0]

Data [7:0]

C[3:0]

D[7:0]

0

1

0

1

WR

RCP

DI[7:0]DO[7:0]

Figure 18: Hamming error correction register.

The various circuit blocks of the SY1007 receive datadirectly from the correction matrix rather than from the out-put of the registers. This ensures that in case of a SEU er-ror the correct value is available immediately within a com-binational delay and not with a clock cycle latency. Glitchsuppression logic removes the eventual error correctionglitch, as well as single event transient (SET) glitches.

During a read operation, if a SEU occurs in the sameclock cycle when data is latched by the read shift register,the incorrect value might be returned back, although thecontent of the register itself will be corrected on the nextclock cycle.

13 Applications Information

13.1 Power Control

The SY1007 provides 4 different power modes that can beused to implement various power saving methods. Thesepower modes are listed in Table 11 and their purpose isthe following:

• Sleep: In sleep mode all circuits of the SY1007 arepowered down. In this mode, the registers can stillbe read or written. Power consumption will mainlydepend on the input clock frequency and the num-ber of accesses that are made to the registers. If theclock frequency is set to zero, the power consump-tion consists mainly of leakage currents.

• Doze: In doze mode the band-gap reference andthe voltage regulator are turned on. The time re-quired to enter this state is dominated by the timerequired by the voltage regulator to turn on. With a33µF capacitor it approximately 50ms.

• Stand-By: In stand-by mode the PLL is turned onwhile the signal path stays powered down. Thisstate may be used to allow the PLL to stabilize be-fore entering the fully active mode.

• Fully active: In fully active mode the SY1007 is fullyon and operating.

The power modes of the SY1007 may be selected via thedigital interface by writing in the Pwr-Modes register (bits[0:1], see table 10). Table 11 shows the approximate timerequired to reach stable operation (latency) from the pre-vious state. Exiting any power mode is much faster andtypically takes less than 100µs. Gray coding has beenused to simplify avoiding glitches while switching from onepower mode to the other. Switching from one power modeto the other may be done in any order.

Mode Code LatencySleep 00 -Doze 01 50msStand-By 11 5-10ms (depends on

PLL loop filter)Fully Active 10 150-250µs

Table 11: SY1007 power modes.

13.2 Frequency Plans

Since the SY1007 has independent RF and IF local oscilla-tors, it offers a great freedom in the selection of frequencyplans. Basically, any frequency plan that places the IFsomewhere around 100-300MHz and the near base-bandsignal bandwidth inside the I/Q filter bandwidth (12MHzworst-case) is potentially suitable. In the interest of reduc-ing the PLL spurious content a high reference frequencycan be used. The limiting factor is however the resolu-tion of the integer-N PLLs that is 4x RCP for the RF PLLand RCP for the IF PLL. Using excessively high referencefrequencies may prevent good frequency plans to be de-signed.

Table 12 shows a few frequency plans examples thatcan be implemented using the on-chip PLLs. In these ex-amples the use of either a common RF or IF local oscilla-tor frequency has been assumed together with a referencefrequency of 5MHz. This gives a resolution of 20MHz and5MHz for the RF PLL and IF PLL respectively. Using acommon IF frequency may simplify the design of the IFfilters, as one single filter type may serve several bands.

The performances of the SY1007’s on-chip PLLs weretailored for generic GNSS navigation receivers. For morecritical applications requiring better phase noise than theSY1007 can offer, external local oscillators can be used. Inthe interest of reducing the effect of phase noise, in multi-channel receivers it is best to share the signal of a singlelow-noise local oscillator among all channels rather thanregenerating the local oscillator signals locally. The phasenoise will then be coherent on all channels, such that it canbe rejected as a common-mode signal.

Good frequency plans with shared local oscillatorsmay be achieved e.g. by using a common RF local oscilla-tor frequency of 1400MHz, as shown in table 12. A singleexternal RF PLL would then be required, while the on-chipIF PLLs can still be used. A phase noise improvement ofup to approximately 20dB at offsets below 100Hz may beachieved this way, without requiring any external IF PLLs.



13.3 Analog Blocks

13.3.1 Low Noise Amplifier (LNA)

The LNA requires matching networks at its input and out-put. Figure 19 depicts a typical configuration for the LNAwith its matching networks.

LNI

AVDD

RFIN

LNOLNA

RFOUT

100pF

L1 L3

L2

100pFR1

C1

C2 C3

Figure 19: LNA configuration (matching networks).

Depending of the type of signal source used (antenna,external LNA), the input of the LNA may need to be config-ured for noise matching or for impedance matching, whilethe output of the LNA – which typically is connected toa SAW filter – needs to be impedance matched to 50Ω.Tables 13 and 14 show typical values for the matching net-works and the resulting LNA performances, obtained onthe SY1007 test board.

For the impedance-matched case a RLC network hasbeen proposed in order to broaden the impedance match-ing bandwidth. The 100Ω resistor will however increasethe noise figure by about 1.5dB, which is usually accept-able if sufficient gain is placed in front of the SY1007’sLNA. If the gain of the external LNA is above ≈25dB anattenuator can be used to further improve matching andachieve a higher interferer resilience.

As with any GHz RF circuit, RLC component types anddesign of the PCB are critical to the performances of theLNA. Proper RF PCB design is needed, while componentswith size 0805 or smaller shall be used. The values of allmatching components depend on the layout of the PCBor the substrate dielectric constant. The component val-ues shown in Tables 13 and 14 have been found experi-mentally on the SY1007 test board and may (will) vary andrequire optimization. LNA S-parameters in Touchstone for-mat are available.

Band L1/E1 L2 L5/E5aFrequency 1575MHz 1227MHz 1176MHzC1 N/F N/F N/FL1 3.9nH 6.8nH 6.8nHL2 5.6nH 12nH 15nHL3 6.8nH 12nH 12nHR1 N/F N/F N/FGain 18.9dB 20.4dB 21.2dBNF 1.6dB 1.5dB 1.4dBS11 −2.6dB −2.1dB −1.9dBS22 −14.6dB −23.1dB −23.3dB

Table 13: Noise matching networks.

Band L1/E1 L2 L5/E5aFrequency 1575MHz 1227MHz 1176MHzC1 3.3pF 3.3pF 3.3pFL1 4.7nH 8.2nH 10nHL2 5.6nH 12nH 15nHL3 6.8nH 12nH 12nHR1 100Ω 100Ω 100ΩGain 20.0dB 22.5dB 21.0dBNF 4.5dB 3.5dB 4.2dBS11 −17.6dB −16.13dB −21.3dBS22 −12.6dB −13.6dB −13.2dB

Table 14: Impedance matching networks.

Coupling between LNI and LNO shall be minimized.Stray inductances and capacitances will create a Hartleyoscillator tank-circuit around the LNA. If the capacitancebetween LNI and LNO is not minimized the LNA will breakinto sustained oscillation. A ground track running betweenLNI and LNO is usually needed. Please make also surethat AVDD is very well decoupled. Any stray impedanceon AVDD will appear in series with L2, thus upsetting out-put matching.

In systems having a gain >30-35dB in front of theSY1007, the on-chip LNA may not be necessary or mayeven lead to poor front-end linearity if used. In such casesthe on-chip LNA may be disabled by tying its input (LNI) toground and leaving its output (LNO) open. In such caseno components need to be mounted around the LNA.

GNSS signal GNSS Freq. LO freq. IF1 IF220-25MHz Signals, RCP=5.0MHz, RF-LO=1400MHz, fs=40-50MH zGPS L1, GAL E1bc 1575.42MHz 175MHz 175.42MHz 0.42MHzGLO L1 1601.71MHz 200MHz 201.71MHz 1.71MHzGPS L2 1227.60MHz 170MHz 172.40MHz 2.40MHzGLO L2 1245.78MHz 155MHz 154.22MHz 0.78MHzGPS L5, GAL E5a 1176.45MHz 225MHz 223.55MHz 1.45MHzGAL E5b 1207.14MHz 195MHz 192.86MHz 2.14MHzGAL E6 (BPSK5) 1278.80MHz 120MHz 121.20MHz 1.20MHz20-25MHz Signals, RCP=5.0MHz, IF-LO=175MHz ( ⇒IF-VCO=350MHz), fs=40-50MHzGPS L1, GAL E1bc 1575.42MHz 1400MHz 175.42MHz 0.42MHzGLO L1 1601.71MHz 1420MHz 181.71MHz 6.71MHzGPS L2 1227.60MHz 1400MHz 172.40MHz 2.60MHzGLO L2 1245.78MHz 1420MHz 174.22MHz 0.78MHzGAL E5b 1207.14MHz 1380MHz 172.86MHz 2.14MHzGAL E6 (BPSK5) 1278.80MHz 1460MHz 181.20MHz 6.20MHz

Table 12: Some possible frequency plans (for GPS, GALILEO and GLONASS).



13.3.2 RF Filter (SAW or Dielectric)

An RF filter is always required with the SY1007, in orderto remove out-of-band signals that could disturb chip per-formance. A filter with sufficient selectivity to suit the oper-ating environment should be chosen. The most importantfilter parameters to look at are:

• Attenuation of the image frequency (≥20dB recom-mended).

• Attenuation of signals from on-board transmitters.• Insertion loss, especially if passive antennas and no

external LNAs are used (≤2.5dB recommended).

Either SAW filters or dielectric filters may be used as longas sufficient performances are available. Suitable filterscan be found e.g. by Vectron, ComDev or Norspace, insome cases already qualified for Space use (ESCC 9000or MIL-STD-883 Class S).

The PCB layout around the RF filter is critical to filterperformance. Input and output of the filter shall be verywell isolated, otherwise the RF signal would be allowed tobypass the filter, thus compromising its out-of-band rejec-tion. Figure 20 shows a possible PCB layout (for a SAWfilter in LCC package). A fence between filter’s input andoutput – well connected to the ground plane with severalvias – minimizes capacitive coupling that would bypass thefilter.

IN OUT

GroundGround

GroundGround

Figure 20: Suggested SAW filter PCB layout.

13.3.3 RF Mixer Input

The RF mixer input is 50Ω balanced and can typically beconnected directly to either a SAW filter (with balancedoutput) or to a 1:1 balun. Suitable baluns for the SY1007are transformer, transmission line or discrete LC designs.LC baluns may be preferable since they use simple LCparts readily available in space-qualified quality.

C C

L

L

C C

RF-INUnbal.(50Ω)

RF-OUTBalanced

(50Ω)

Figure 21: LC balun schematic diagram.

A possible LC balun structure is shown in Figure 21.Since an LC balun is selective, the values of the compo-nents must be adapted to the operating frequency of thebalun. In order to cover all GNSS bands two designs aresufficient. Table 15 shows the LC values for these twodesigns (low and high band), which must be adjusted ex-perimentally to fit PCB parasitics.

Band C LLow, 1.2GHz (L2-L5) 2.7pF 6.8nHHigh, 1.6GHz (L1) 2.0pF 5.6nH

Table 15: Component values for LC balun.

Again – as usual with RF designs – good PCB RFlayout is necessary, as any stray impedance will upset in-put matching, reduce the conversion gain of the mixer andworsen its noise figure.

The input of the RF mixer is biased to about 400mVand shall never be DC shorted to ground or receive any DCbiasing from outside, otherwise the SY1007 will be perma-nently damaged. If the RF filter or balun has a DC path toground DC blocking series capacitors shall be used. Suchcapacitors may also be used to compensate possible strayinductance of the PCB trace; as a starting point the rec-ommended value is 18pF, which should then be optimizedexperimentally.

13.3.4 IF Filter

The SY1007 requires an external IF filter for channel se-lection and to filter off noise at the images of the AD-converter. Various IF filter types may be accommodated bythe SY1007 in order to suit different operating conditions.When selecting an appropriate IF filter it is however im-portant to consider that all receiver’s filtering requirementsshall be implemented by the RF and IF filters, before thehigh gain IF-strip, otherwise poor receiver performancesmay result.

Although the SY1007 accommodates various IF-filtertypes, in most cases a 4th or 6th order bandpass LC-filteris used. Figure 22 shows the schematic diagram of suchfilter. It consists of a parallel resonator (L1-C1, implement-ing 2 poles of the filter) followed by a coupled resonator 4thorder stage (L2-C2, L3-C3-R3 and the coupling capacitorsC4-C5).

L1 L2

R3

L3

C3C4

C2

C1

MIXP IF1NIF1P IF2P IF2NMIXN

RFNRFP

C5

Mixer IF Amp IF VC Amp

Figure 22: IF LC-filter configuration.

The whole IF filter is best considered as a single filter(rather than separate filters) and may be calculated withreadily available computer programs or using filter tables.Since the input impedance of the VCA is high, resistor R3is necessary if a 6th order filter is to be implemented. Thisresistor however causes the insertion loss of the filter toincrease. In order to avoid an excessive insertion loss thatcan no longer be compensated by the IF VCA this resis-tor should be selected to be ≥600Ω. A good starting pointcould be 1.0-1.5kΩ. A 600Ω resistor already results in anextra 6dB insertion loss.



In many cases a 4th order filter is sufficient. In thiscase C4 and C5 shall be set to 100pF and C3-L3-R3 omit-ted. 4th order IF filters for 3 different IF frequencies areshown in the application example (Section 16, Figure 29).Figure 23 shows a measured frequency response (from120MHz to 220MHz) of the 4th order 174MHz IF filter ofthe application example.

120 130 140 150 160 170 180 190 200 210 220−40

−35

−30

−25

−20

−15

−10

−5

0

5

10174MHz IF Filter

Center 170.0 MHz Span 20.0 MHz#Res BW 1.0 MHz VBW 1.0 MHz Sweep 401 pts

Am

plitu

de5.

0 dB

/

Figure 23: Measured 4th order IF-filter response.

Accurate, temperature stable components shall beused in the IF filter. Ceramic NPO capacitors with 2%(maximum 5%) tolerance are recommended. Placing twocapacitors in parallel as shown in Figure 29 allows an easyfine tuning of the IF filter. Wire-wound or multi-layer in-ductors (again with maximum 5% tolerance) can be usedfor values below about 500nH, while shielded ferrite-coreinductors are useful for higher values. Unshielded open-core ferrite inductors shall never be used in the IF filter.Open-core ferrite inductors are in fact efficient antennas(rod antennas) that would easily pick-up any interferencearound the frequency to which the IF filter is tuned.

13.3.5 IF-Strip and Quadrature Output

The IF-strip of the SY1007 comprises a VCA with loga-rithmic (dB-linear) control input and a quadrature down-converter. The gain of the VCA is controlled by the volt-age applied to pin ACGI, which is typically obtained withthe DA-converter of a SY1017. When used in combinationwith the SY1017 a gain step of about 1dB is obtained. If adifferent device is used to generate the AGC control volt-age it must be able to produce a V(AGCI) = 0.2V to 2V inorder to cover the whole gain control range. Please ob-serve the temperature dependence of gain vs. V(AGCI),Fig. 8. Since the AGC control is rather sensitive (about9mV/dB) the control voltage shall be kept clean, otherwisegain modulation will occur. An RC low-pass filter may beused to reduce possible noise on pin AGCI.

The near base-band quadrature output is available onpins OIP, OIN, OQP, OQN. Typically these outputs are AC-coupled to a SY1017 AD-converter ASIC, as shown inFig. 24. 100nF ceramic X7R (or better) capacitors are rec-ommended.

These outputs are filtered with on-chip 3rd order low-pass filters and are internally buffered with low outputimpedance (about 125Ω) amplifiers to minimize errors dueto loading effects. In order to keep amplitude and phaseerrors low it is however mandatory that load impedances –including PCB strays – are kept as similar as possible on

both I and Q outputs. Traces with equal length and widthshould be used as well.

C1100nFC2

100nFC3100nFC4

100nF

C5

1.0nF

SY1007SY1008

OIN

OIP

OQN

OQP

AGCI

I1N

I1P

I0N

I0P SY1017

AGCO

Figure 24: Typical SY1007 to SY1017 interface.

Although the output impedance of the I/Q outputs is125Ω, this does not mean that they can drive a 125Ω load.OIP-OIN and OQP-OQN shall in fact not be loaded withless than 10kΩ, or severe distortion and amplitude limitingwill occur.

Adding base-band off-chip filtering on the I and Q out-puts as a means to improve channel filtering is stronglyNOT RECOMMENDED. Such filtering – if used – will in-troduce quadrature errors (unless the filters are carefullyaligned) and will very likely cause AGC misbehavior orreceiver blocking in presence of near-band interferers. Ifbase-band filtering is required please make sure that anyand all interferers are removed at RF and IF, before theycan reach the high gain IF-strip (pins IF2P-IF2N).

13.3.6 RF and IF Frequency Synthesizers

The SY1007 contains two frequency synthesizers whichgenerate the required RF and IF local oscillator signals.RF and IF PLLs are enabled with pins RENB and IENB(active on low logic level) respectively, and can be enabledor disabled independently from each other.

Both RF and IF synthesizers need an off-chip inductorfor the VCO, whose value depends on the required localoscillator frequency and that shall be adjusted depend-ing on PCB strays. In order to align the PLL, a VCO in-ductor value of 4.7nH and 47nH respectively can be usedas starting point, then the reference frequency of the PLLshall be swept and the loop filter voltage measured andrecorded. Curves similar to the ones shown in Figures 9and 10 (Section 7) should be obtained. The VCO inductorsshall then be adjusted (replaced) until the PLL operatingpoint is in the middle of the measured PLL curve.

The Q of the inductors is instrumental in obtaining rea-sonable VCO performances and phase noise. If inductorswith excessively low Q are used phase noise will increase,while the VCO may even stop operating, especially at thehigher temperature limit. If such behavior is noticed induc-tors with higher Q shall be used.

Caution: great attention has to be paid to the PCBlayout around the VCO inductors, especially the one of theRF VCO. The shortest, straightest tracks shall be used toconnect the inductor to the SY1007, otherwise the desiredVCO frequency may not be attainable with any inductorvalue, or spurious oscillations, not defined by the VCO in-ductor, may result. The stray inductance of the PCB tracesconnecting the inductor to the RF VCO shall be evaluatedif inductors below about 2.7nH are required to reach theproper VCO operating frequency, or if the SY1007 RF PLLfails to lock or behaves in a strange manner. Please re-member that 1nH (about 1.2-1.5mm PCB track) and 1pF(a small PCB area, 2-3 footprints) at 1.6GHz are already areactance of 10Ω and 100Ω respectively.



13.3.7 RF and IF PLL Loop Filters

The loop filters for the RF and IF PLLs are external andshall be connected to pins RPLL and IPLL respectively. ACRC network, as shown in Figure 25, is recommended.The components can be calculated using the VCO sen-sitivity data and the desired division ratio. The nominalcurrent of the charge pump is 50µA.

R1

C1

C2

RPLL, IPLL

Figure 25: PLL loop filter schematic diagram.

The cut-off frequency of the loop filter is a trade-offbetween phase noise and spurious signals power, andshould therefore be dimensioned according to the needs ofthe given application. Figure 26 shows schematically theidealized behavior of the phase noise of the SY1007’s RFPLL for two different loop filter bandwidths (purple: wide-band, red: narrow band loop filter) as well as the contribu-tions of the VCO and the charge pump alone.

100 1k 10k 100k 1M

-100

-90

-80

-70

-60

-50

-110

Pha

se n

oise

[dB

c/H

z]

Frequency offset [Hz]

Charge pumpthermal noise

VCO phase noise(free running)

Charge pumpflicker noise

-3dB/oct.

-6dB/oct.

Figure 26: Phase noise of RF PLL (idealized).

A wide-band loop filter (faster PLL, purple curve) givesbetter phase noise performances at the expense of higherspurious signals. In contrast, a narrow-band loop filter at-tenuates the spurious signals to the detriment of the phasenoise performance (slower PLL, red curve). A phase mar-gin around 50-55 is recommended if fast lock time is de-sired, otherwise lower phase margins can be used if spu-rious signals have to be reduced. Examples of loop filterdesigns are shown in the application example (Section 16).

The loop filter – or at least C2 (in Figure 25) – shouldbe mounted close to the RPLL and IPLL pins in order toprovide a low inductance RF path to ground. PCB trackscarrying noisy signals (e.g. digital lines) should be keptaway from the loop filter, otherwise noise could be injectedinto the PLL, thus degrading phase noise performances bydirectly modulating the VCO.

13.3.8 External Local Oscillators

In applications that require better phase noise than theSY1007 can offer, the SY1007’s on-chip PLLs can be dis-abled by setting RENB or IENB to logic high and externaloscillators can be used instead. The signal of a balancedexternal oscillator shall be applied to pins RL1-RL2 (RF-VCO) and/or IL1-IL2 (IF-VCO). The external RF-VCO shallbe set to the desired RF-LO frequency, while the externalIF-VCO shall be set to twice the desired IF-LO frequencyto account for the dividing-by-two quadrature LO generator(see Section 10 and Figure 15).

1nFR1

C1

1nF

C2

SY

1007

SY

1007

xL1 xL2 xL1 xL2

100ΩTransmission line(balanced, 100Ω)

Figure 27: LO distribution (bridging).

The VCO inputs are high impedance and may be ter-minated with an inductor to compensate their input capac-itance if necessary. These inputs are internally biased toAVDD and shall not be forced. A termination resistor mayalso be used to properly terminate the LO transmissionline if necessary.

If an on-chip PLL is disabled no loop filter is requiredon its respective pin (RPLL or IPLL). In that case thesepins shall be left open and no connection shall be made tothem. Pins RPLL and IPLL are internally biased (to AVDD)when on-chip PLLs are disabled and shall not be forced.

In systems using many RF channels in parallel thatshare the same local oscillator frequencies, the local os-cillator signals can be distributed in a simple and effectiveway using a single transmission line as shown in Figure 27.This LO signal sharing structure is possible thanks to thehigh input impedance of the SY1007’s LO inputs.

The transmission line – e.g. 100Ω – shall be terminatedat its end, while the taps to the SY1007 shall be very shortto avoid stubs that would cause line mismatch. By bridgingmany SY1007 on the same transmission line lossy powersplitters are avoided and the LO power can be lower. Withcareful PCB layout, up to 4-5 SY1007 can be bridged ona single transmission line. Please observe the signal levelrequirements (Section 5 and Note 15).

13.4 Voltage Reference and Regulator

Biasing to the SY1007 is provided by an on-chip 1.17Vband-gap voltage reference and a 1.9V voltage regulator.These voltages are available on pins VBG and VB respec-tively. The 1.9V regulator provides power to the VCO.Both band-gap reference and voltage regulator are activein doze mode and up.

A capacitor of at least 1µF (ceramic X5R or X7R) isrequired for stability on both VBG and VB, which shallbe mounted close to the chip. To improve noise perfor-mances, in particular the phase noise of the VCO, a ca-pacitor of at least 33µF is recommended for VBG.



Both outputs may supply power to an external load ifdesired. The maximum available output current is 200µAand 1mA respectively. It is however important that theseloads, if used, do not introduce any noise into VBG andVB. In particular, noise into VBG may disturb the wholechip, while noise into VB may disturb especially VCO andPLL.

13.5 Power Supply

The SY1007 requires two power supplies: analog (AVDD)and digital (DVDD). The recommended ranges are shownin Table 16. The power supplies need not be well regu-lated but must be well filtered. This applies in particular tothe analog power supply AVDD. DVDD may be taken ei-ther from AVDD via an RC or LC network or from someother (clean) voltage. Using a general power supply –e.g. the power supply for some micro-controller or GNSSbase-band processor – as DVDD is not recommended, asdigital switching noise would be injected into the SY1007thus degrading its performance.

Power Supply Min MaxAVDD (Analog) 2.4V 3.6VDVDD (Digital) 2.2V AVDD+0.2V

Table 16: Power supply ranges.

No particular sequencing is needed while applyingpower to the SY1007. AVDD and DVDD may be appliedsimultaneously or in any order. Increasing DVDD aboveits maximum operating level (AVDD+0.2V) is not recom-mended except during the power on transient. This willnot cause any permanent damage, but the SY1007 will notoperate correctly if the condition is violated. Once DVDDis returned to the allowed range the SY1007 will resumeproper operation from itself while no data is lost if DVDD iskept above its minimum rating of 2.2V.

Signal voltages shall not be applied to the SY1007 be-fore the power supply is applied, otherwise the ESD pro-tection diodes may become forward biased and possiblybe damaged. Digital signals may track DVDD during powertransients, as long as the DVDD+0.2V condition is not vio-lated.

Power supply decoupling is always required. A 100nFceramic capacitor (X7R) mounted very close to the devicebody is recommended on each AVDD and DVDD pins. A2.2µF (or higher) ceramic or tantalum capacitor may be re-quired on AVDD, especially if AVDD is not well regulated.A 1nF capacitor has to be mounted very close to the LNAoutput matching network on the AVDD supply.

14 Handling Precautions

14.1 Hazardous Substances

The SY1007’s solder balls contain lead (Sn60-Pb40),therefore the SY1007 is not RoHS compliant and shallbe handled accordingly. Discarded SY1007 devices shallnot be dispersed into the environment or disposed of withcommon waste.

Apart from the lead contained in the solder balls,the SY1007 does not contain any other hazardous ma-terials, in particular no mercury (Hg), cadmium (Cd) or

hexavalent chromium (Cr6+), the flame retardants poly-brominated biphenyls (PBB) and polybrominated diphenylethers (PBDE), or berillium oxide (BeO) ceramic.

14.2 Storage

The SY1007 is packaged in a ceramic-metal package thatis not sensitive to humidity, however improper storage maycause contamination or oxidation of the solder balls thusimpacting solderability. The product shall not be exposedto high humidity or to direct sunlight, harmful/corrosivegases or dust. Also avoid storing it in locations where sud-den temperature changes may occur.

To ensure long shelf life, the product should be storedin a controlled temperature (≈20-25C) and humidity(<60%) environment, possibly in its original shipping bag.Do not open the bag until just before product’s use. If long-term storage of several years is anticipated, the productshould be stored in a dry cabinet.

15 Radiation Tolerance

The SY1007 is a rad-hard device and several countermea-sures have been taken during its design to achieve a highdegree of radiation tolerance. The extensive use of guardrings and other latch-up prevention techniques – espe-cially in the I/O area – yields excellent latch-up immunity.Heavy ion tests up to a LET of 45MeV cm2

mg have proven thechip’s robustness against both latch-up and SEU. SeveralDUTs have been tested at temperatures up to 85C and amaximum supply voltage of 3.6V until a cumulated fluenceof 1E+7 ions/cm2 without detecting any latch-up.

If requirements higher than 45MeV cm2

mg have to be ful-filled some latch-up protection is required. This may con-sist of a current limited (40-50mA) voltage regulator with afast acting disable function to release the latch-up. Spe-cific latch-up protection circuits are also available on themarket, which can be used with the SY1007. The total de-coupling capacitor on the SY1007’s power supply shall belimited to <10µF to avoid burn-out of the SY1007 due tothe capacitor surge.

All registers are protected against SEU with a Ham-ming error correction mechanism, while a parity bit pro-tects communications from the master device to theSY1007. It is however good practice not to rely on thebuilt-in SEU protection alone. It is recommended that af-ter a write operation a read operation to the same reg-ister is performed, while all registers should periodicallybe read back to check their contents. If corrupted datais found then re-read the register, if the data is still wrongthen rewrite the register and check it again. Checking backthe registers is the first thing to do in case of suspicion ofconfiguration loss of the device (e.g. if the receiver stopsworking suddenly). Since the RF-PLL register remains se-lected when the SY1007’s interface is idle, accessing itat the end of a register verification operation further mini-mizes risks of SEU.

The SY1007 comes into a ceramic-metal hermeticpackage containing no organic materials, while eutectic –rather than epoxy – die attach has been used. This devicewill therefore not decompose or release any substantialamount of gas or organic contaminants under vacuum orhigh radiation levels.



16 Application Example

Figure 28: Application example: top level.



Figure 29: Application example: RF section (SY1007).



Figure 30: Application example: AD-converter section (SY1017C).



17 Layout Recommendations

The SY1007 is a sensitive receiver. Although the IC israther robust and easy to use, an improper PCB layoutmay degrade its performance significantly.

The best performance is generally achieved when theSY1007 is placed over a solid ground plane with as little in-terruptions as possible. If a 2 layer PCB is used, the bestlayout would be to use the bottom layer as ground planewith all routing made on the top layer. A similar layout canbe used also in multilayer PCBs, where internal layers canbe used as ground plane instead of the bottom layer. Itis however recommended to leave some spacing (at least0.3mm) between the top layer and the ground plane, asthis reduces losses and stray capacitances. A core lami-nate rather than a pre-preg should be used in order to ob-tain a better control on thickness and thus on transmissionlines impedance.

Standard PCB materials such as FR4 can be used.Special low-loss substrates are in most cases not requiredto achieve proper performance, and would give only mod-erate performance improvements.

Proper connections are also important if good perfor-mance is to be achieved. The RF connections to the an-tenna and SAW filter shall be made with 50Ω striplines(unless their length does not exceed a couple mm), whilevias on all RF connections shall be avoided. Decouplingcapacitors – especially on AVDD and VB – shall be con-nected very close to the chip using traces as wide as pos-sible, with the other side of the capacitor well grounded (2-3 vias). AVSS and DVSS shall be connected to the groundplane as close to the chip package as possible.

In order to avoid interference to the receiver from digitalswitching noise all digital signals shall be routed away fromsensitive analog connections while some shielding is rec-ommended. In particular the SY1007 shall be placed in itsown shield or cavity, well separated from any digital com-ponent (including the SY1017C). The components mostsensitive to interference are the antenna and the LNA, fol-lowed by the IF filter.

18 PCB Recommendations

To guarantee proper mounting of the IC, the PCB land pat-tern shown in Figure 31a shall be used. In particular thefollowing requirements shall be adhered to:

• Non solder mask defined (NSMD) lands shall bepreferred.

• The width of the fan-out traces shall not exceed0.3mm and shall be symmetrical to avoid part ro-tation due to surface tension of solder.

• Vias inside PCB lands (preferred) shall be pluggedand metallized on top to prevent solder from wickingthrough the via hole. Unplugged vias inside PCBlands are not allowed.

• If used, a solder mask with tight openings is recom-mended to ensure that some solder mask remainsbetween the PCB lands. Traces passing betweenlands shall be completely covered with solder mask,otherwise short-circuits may easily develop. Puttingthe solder mask only under the SY1007 is also pos-sible if covering the whole PCB is not allowed.

• If PCB flexing is likely, the part should be placed onan unstressed area, away from the area of maxi-mum flexing, otherwise solder joints may crack.

• The PCB shall meet the solderability requirementsof IPC/JEDEC J-STD-003 and shall be flat to within0.1mm per cm. Surface finishes such as an organicsolderability preservative (OSP) coating or Sn andNi-Au finishes are fine, while hot air solder leveled(HASL) finish is not recommended.

• If a Ni-Au finish is chosen (electroplated Ni, immer-sion Au), Au thickness must be less than 0.2µm toavoid solder joint embrittlement.

PCB Gerber data is available and can be used as recom-mended layout. To request it please contact SAPHYRIONsupport team at [email protected].

a. b.

0.80

0.80

0.35

Stencil

0.80 BSC

U1-SY10xx

0.80

BS

C

Solder Mask

PCB Land

o0.4

5+ −0

.05

≅0.0

5

Figure 31: PCB land pattern and stencil openings: BGA, 6mm x 6mm, 36 balls.



19 Mounting Recommendations

The SY1007 is fitted with Sn 60%-Pb 40% solder balls(melting point = 183C). The device shall be mounted tothe PCB by reflow soldering. Infra-red (IR) reflow is thepreferred method, vapor-phase reflow may also be usedhowever. Please follow these recommendations:

• Stainless steel stencils with a thickness of 100-125µm are recommended for solder paste applica-tion. For improved solder paste release the wallsof the apertures should be tapered and the cornersrounded.

• The recommended stencil apertures are shown inFig. 31b. Use laser cutting followed by electro-polishing for stencil fabrication. Etched stencils arenot recommended.

• Use Type 3 (25µm to 45µm particle size range) orfiner solder paste for printing. (Near) eutectic Sn60-Pb40, Sn63-Pb37 or Sn62-Pb36-Ag2 solder pasteswith a melting point of 183C shall be used.

• The standard JEDEC (J-STD-020) reflow tempera-ture profile shown in Fig. 32 should be used. Therecommendations given by the solder paste manu-facturer should also be followed.

Typically, the area under the profile curve, bounded bythe liquidus temperature, defines the quality of the solderjoint. Too little area leads to cold solder joints, which area reliability risk. Too much area could result in undesirablemetallurgical issues, that could also be a reliability risk.Some experimentation may be necessary. A daisy-chaindevice that can be used to validate the soldering processfor the SY1007 is available.

After assembly the board shall be cleaned to removesolder flux residue. Solder flux residue between pads oron RF components may cause high leakages which mayincrease RF losses to an unacceptable level. Ultrasoniccleaning shall not be used since many parts – especiallycrystals, SAW filters and oscillators – may be damaged.No-clean solder flux may be used to minimize cleaning re-quirements.

Profile Feature Sn-Pb Eutectic AssemblyPreheat/soak:Temperature Min (TSmin) 100CTemperature Max (TSmax) 150CTime (tSmin to tSmax) 60s to 120sReflow:Ramp-up rate (TL to Tp) 3C/s max.Liquidus temperature (TL) 183CTime (tL) maintained above TL 60s to 150sPeak temperature (Tp) 240CTime whitin 5C of actual peak temperature Tp (tp) 10s to 30sRamp-down rate (Tp to TL) 6C/s max.Time 25C to peak temperature 6 minutes max.

Table 18: Reflow profile details (JEDEC J-STD-020).

T min

T

T

t t

Time [s]

Tem

pera

ture

[C

]

t 25[ C] to Peak Temperature

LS

S

T maxS

L

p

Ramp up Ramp down

t p

Figure 32: Recommended reflow profile.


DATA

SH

EE

TS

Y1007

GN

SS

RF

Front-End

20P

ackageD

rawing

A-A

1

1

2

2

3

3

4

4

5

5

6

6

A A

B B

C C

D D

Issue

Sheet

Scale

File name

NameCustomer

Drawing no.

Designed by

Checked byCONFIDENTIAL INFORMATIONALL RIGHTS RESERVED. PASSING ON AND COPYING OF THIS DOCUMENT,

USE AND COMMUNICATION OF ITS CONTENTS NOT PERMITTEDWITHOUT WRITTEN AUTHORIZATION FROM KYOCERA.

Date

0EUROPEAN DESIGN CENTREA3

David

2007037 - 36 csp -assy.iam

16:1

36 CSPKF-2007037-REF

1/130/03

/2007

A A

6 0.155.6 0.054.7 0.08 0.85 0.1 0.72 0.07

0.845x0.8=

SOLDER LID42 ALLOY / Solder KC-003

CERAMICKYOCERA A473

NOTES :1. CERAMIC MADE BASED ON KYOCERA DRWG KD-UA4K322. SODLER LID MADE BASED ON KYOCERA DRWG KKM-30017-013. BALL ARE FOR REFERENCE ONLY

Rev.

1.4,January31,2014

Saphyrion

Sagl

23


Glossary

Acronym Meaning Acronym MeaningAGC Automatic Gain Control LNA Low Noise AmplifierAGGA Advanced GPS/GLONASS ASIC LO Local Oscillator (down-converter)(C)BGA (Ceramic) Ball Grid Array NF Noise FigureEM/FM Engineering Model / Flight Model OCXO Oven Controlled Crystal OscillatorESA European Space Agency PCB Printed Circuit BoardESCC European Space Components Coordination PLL Phase-Locked LoopESD Electro-Static Discharge RF Radio FrequencyGLONASS GLObalnaya NAvigatsionnaya SAW Surface Acoustic Wave

Sputnikovaya Sistema SEL Single Event Latch-upGNSS Global Navigation Satellite System SET Single Event TransientGPS Global Positioning System (NAVSTAR) SEU Single Event UpsetHBM Human Body Model (ESD) SiGe Silicon-Germanium (HBT)HBT Heterojunction Bipolar Transistor TCXO Temp. Compensated Crystal OscillatorIF Intermediate Frequency VCA Voltage Controlled AmplifierLET Linear Energy Transfer VCO Voltage Control Oscillator

Ordering Information

Part Description Package Temperature Pack RoHSSY1007R GNSS receiver RF front-end IC, Ceramic BGA −55 to +125C Tray No

rad-hard. 36 ballsSY1007S GNSS receiver RF front-end IC, Ceramic BGA −55 to +125C Tray No

space qualified, ESCC9000. 36 balls

Related ProductsPart Description CommentsSY1008 GNSS receiver RF front-end IC. Higher integration level, no external LO inductors.SY1017C AD/DA-converter/interface IC. 3-bit I/Q AD-converter, 8-bit DA-converter (AGC).Daisy-Chain Daisy-chain CBGA package. To develop and validate the soldering process.

Via della Posta 10B6934 BioggioSwitzerland

Phone +41 91 220 1100Fax +41 91 220 1101http://www.saphyrion.ch

DISCLAIMER

SAPHYRION PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICESOR IN APPLICATIONS WHICH INVOLVE POTENTIAL RISK OF DEATH, PERSONAL INJURY OR SEVERE PROPERTYOR ENVIRONMENTAL DAMAGE IN CASE OF FAILURE OR MALFUNCTION OF THE PRODUCT.IN CASES WHERE EXTREMELY HIGH RELIABILITY IS REQUIRED (SUCH AS USE IN NUCLEAR POWER CONTROL,AEROSPACE AND AVIATION, TRAFFIC EQUIPMENT, MEDICAL EQUIPMENT, AND SAFETY EQUIPMENT), SAFETYSHOULD BE ENSURED BY USING SEMICONDUCTOR DEVICES THAT FEATURE ASSURED SAFETY OR BY MEANSOF USERS’ FAIL-SAFE PRECAUTIONS OR OTHER ARRANGEMENT. IN NO EVENT SHALL SAPHYRION BE LIABLEFOR ANY DAMAGES THAT MAY RESULT FROM AN ACCIDENT OR ANY OTHER CAUSE DURING OPERATION OF THEUSER’S UNITS ACCORDING TO THE DATASHEET(S).


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