GM8126 CAPTURE - Open IP Cam v1.1/Docs/Softw… · Path 0: Grab the left half side of an image ....
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GM8126 GM8126 CAPTURE User Guide Rev.: 1.2 Issue Date: June 2011
Transcript of GM8126 CAPTURE - Open IP Cam v1.1/Docs/Softw… · Path 0: Grab the left half side of an image ....
GM8126
GM8126 CAPTURE User Guide Rev.: 1.2 Issue Date: June 2011
REVISION HISTORY
GM8126 Capture User Guide
Date Rev. From To
Nov. 2010 1.0 - Original
Jan. 2011 1.1 - Updated the module parameters in Chapter 3
Jun. 2011 1.2 - • Added the OV7720 and HM2055 sensor module parameters
• Updated the TW9910 codec module parameter
• Updated the MT9V136 sensor module parameter
• Added the /proc/vcap_drv/property usage
• Added a table for the default OSD font database
Copyright © 2011 Grain Media, Inc.
All Rights Reserved.
Printed in Taiwan 2011
Grain Media and the Grain Media Logo are trademarks of Grain Media, Inc. in Taiwan and/or other countries.Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support application where malfunction may result in injury or death to persons . The information contained in this document does not affect or change Grain Media’s product specification or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Grain Media or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will Grain Media be liable for damages arising directly or indirectly from any use of the information contained in this document.
Grain Media, Inc.5F, No. 5, Li-Hsin Road III, Hsinchu Science Park, Hsinchu City, Taiwan 300, R.O.C. Grain Media's home page can be found at:http://www.grain-media.com
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TABLE OF CONTENTS
Chapter 1 Introduction............................................................................................................................ 1 1.1 Overview..................................................................................................................... 2 1.2 Features ..................................................................................................................... 2 1.3 Block Diagram ............................................................................................................ 3
Chapter 2 Capture Driver Module .......................................................................................................... 5 Chapter 3 Capture Module Parameters ................................................................................................. 7
3.1 fcap_common Module ................................................................................................ 8 3.2 fcap_common_v4l Module ......................................................................................... 8 3.3 fcapX Module ............................................................................................................. 8 3.4 Input Modules............................................................................................................. 9
Chapter 4 Capture Proc Nodes............................................................................................................ 19 4.1 /proc/vcap_drv Proc Nodes...................................................................................... 20 4.2 /proc/vcap_drv/fcap_devX Proc Nodes.................................................................... 26
Chapter 5 Capture Device Nodes for V4L ........................................................................................... 29 Chapter 6 Capture OSD and Mask ...................................................................................................... 31
6.1 OSD/Mask Device Nodes......................................................................................... 34
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LIST OF TABLES
Table 3-1. Parameters of fcap_common Module ................................................................................... 8 Table 3-2. Parameters of fcap_common_v41 Module ........................................................................... 8 Table 3-3. Parameters of fcapX Module................................................................................................. 8 Table 3-4. Parameters of fcap200_mt9d131 Module............................................................................. 9 Table 3-5. Parameters of fcap200_geninput Module ........................................................................... 10 Table 3-6. Parameters of fcap200_isp Module .................................................................................... 11 Table 3-7. Parameters of fcap200_tw9910 Module ............................................................................. 12 Table 3-8. Parameters of fcap200_ov7740 Module ............................................................................. 13 Table 3-9 Parameters of fcap200_poa030d Module........................................................................... 14 Table 3-10. Parameters of fcap200_ov10630 Module ........................................................................... 14 Table 3-11. Parameters of fcap200_ov7720 Module ............................................................................. 15 Table 3-12. Parameters of fcap200_hm2055 Module........................................................................... 16 Table 3-13. Parameters of fcap200_mt9v136 Module .......................................................................... 17
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LIST OF FIGURES
Figure 1-1. Capture 0 Block Diagram...................................................................................................... 3 Figure 1-2. Capture 1 Block Diagram...................................................................................................... 4 Figure 4-1. Proc Nodes of Capture Module........................................................................................... 19
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Chapter 1 Introduction
This chapter contains the following sections:
• 1.1 Overview
• 1.2 Features
• 1.3 Block Diagram
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1.1 Overview FTVCAP210 in GM8126 is used to capture the video data from various video interfaces and outputs data to
AMBA AHB. It provides the de-interlace function to reduce the video artifact of the interlace video. With the
ability of sizing down, users can individually reduce the image size to a specific resolution for two paths.
The Color OSD function helps user paste any character to the captured video. The window clipping function
is used to clip the interested region of an image before or after size down. The host processor interface is
compliant with AMBA AHB 2.0, which serves as an IP core for integrating into the AMBA system.
1.2 Features The capture contains the following features:
• Supports maximum capture resolution of up to 1920 x 1080
• Supports ITU-R BT.656 8-bit input interface
• Supports ITU-R BT.1120 16-bit input interface
• YCbCr 4:2:2 8-bit/16-bit with H/V reference control signal interface
• Supports one video capture input with data output paths
• Edge-based line average de-interlacer
• Includes embedded font RAM for color OSD for path 0 and path 1
• Supports up to eight mask windows with transparency degree control
• Supports individual image size-down function for two output paths
○ Path 0: Supports integer sizing down ratio
○ Path 1: Supports fraction sizing down ratio
• Supports individual frame-skip function at two output paths
• Supports individual even/odd field-sorting function for two output paths
• Supports VBI data extraction function
• Supports source and output target image crop function
• Uses YCbCr 4:2:2 output format for path 0 and path 1
• Uses DMA raster order output sequence to support output frame flip and mirror function
• Supports capture clock of up to 108 MHz and AHB clock of up to 240 MHz in 90 nm processes
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1.3 Block Diagram
Figure 1-1. Capture 0 Block Diagram
Figure 1-2. Capture 1 Block Diagram
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Chapter 2 Capture Driver Module
In the GM8126 SDK release package, users will find the source code and kernel module of the capture from
“/module/vcap200_v3”. The source code and kernel module of the sensor are placed in
“/module/vcap200_v3/input_module”.
The capture driver module contains the following parts.
• fcap_common.ko
This is the capture core for a video graph. It includes all capture flow controls and API.
• fcap_common_v4l.ko
This is the capture core for Video4Linux. It includes all capture flow controls and API.
• fcapX.ko
This contains the IP information. It includes the IP base address and IRQ number. In GM8126, X is
ranging from 0 to 1.
• fcap200_xxxx.ko
This contains the external input information. It includes the external sensor or codec initiation
information.
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Chapter 3 Capture Module Parameters
This chapter contains the following sections:
• 3.1 fcap_common Module
• 3.2 fcap_common_v4l Module
• 3.3 fcapX Module
• 3.4 Input Modules
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3.1 fcap_common Module Table 3-1. Parameters of fcap_common Module
Name Default Value Description
Max_LLI MAX_LLI_TABLE (10) Maximum LLI table length
The default value is MAX_LLI_TABLE, which is defined in vcap200_v3/config. Users can specify this value to improve the frame rate switch delay time (Need new DVR driver support).
This feature is supported on:
Vcap200_v3: V0.3.07
3.2 fcap_common_v4l Module Table 3-2 lists the module parameters while inserting this driver.
Table 3-2. Parameters of fcap_common_v41 Module
Name Default Value Description
max_width 720 Maximum width of the frame buffer
max_height 576 Maximum height of the frame buffer
buffer_number 5 Number of the frame buffers
3.3 fcapX Module Table 3-3 lists the module parameters while inserting this driver.
Table 3-3. Parameters of fcapX Module
Name Default Value Description
mode 0 0: Single-step fire mode
1: Link list mode
Driver supports two capture modes. One is the single-step fire mode and the other is the link list mode. The single-step fire mode uses CPU to trigger each frame; while the link list mode uses the hardware link list table to do the same operation.
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Name Default Value Description
album_mode 0 Use Path 0 and Path 1 to synchronously grab the image
0: None (Disable)
1: Mode_1
Path 0: Grab the left half side of an image
Path 1: Grab the right half side of an image
Support only in the single-step fire mode
3.4 Input Modules 3.4.1 fcap200_mt9d131 Module Table 3-4 lists the module parameters while inserting this driver.
Table 3-4. Parameters of fcap200_mt9d131 Module
Name Default Value Description
iaddr 0x90 I2C address for MT9D131
src 0 Number of the capture sources
src_x 3 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
src_y 4 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
bswap 0 Swap device Cb Cr
bv_polarity 1 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 1 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
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3.4.2 fcap200_geninput Module Table 3-5 lists the module parameters while inserting this driver.
Table 3-5. Parameters of fcap200_geninput Module
Name Default Value Description
src 0 Number of the capture sources
src_w 720 Width of the capture source
src_h 480 Height of the capture source
src_x 3 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
src_y 2 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
inv_clk 0 Invert clock
0: None
1: Invert
bv_polarity 0 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 0 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
vbi_en 0 VBI enable
vpif_format 0 Interface format of the video port
0: CCIR656 is the 8-bit interlace video port.
1: CCIR656 is the 8-bit progressive video port.
2: CCIR601 is the 8-bit progressive video port.
3: CCIR601 is the 16-bit progressive video port.
4: CCIR656 is the 16-bit interlace video port.
5: ISP210 is the 8-bit progressive video port.
6: TW2835 and CCIR656 are the 8-bit interlace video port.
7: Sony is 16-bit video port.
8: CCIR656 is the 16-bit progressive video port.
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Name Default Value Description
OData 0 0: Throughput of one data path at 27 MHz for the 1-channel video data
1: Throughput of one data path at 54 MHz for the 2-channel video data
2: Throughput of one data path at 108 MHz for the 4-channel video data
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_demuxclk {0, 0} Invert the demux pixel clock
Not used in GM8126
cfg_pmu_eclk 0 Configure the PMU external clock
Not used in GM8126
cfg_pmu_demux -1 0: demux 0
1: demux 1
-1: demux all
Not used in GM8126
cfg_channel_switch 0 0: Disable
1: Enable
Not used in GM8126
input_clk 27000000 The capture clock frequency is input from the sensor or decoder.
This feature is supported on:
Vcap200_v3: V0.3.07
Input API: V1.9.00
3.4.3 fcap200_isp Module Table 3-6 lists the module parameters while inserting this driver.
Table 3-6. Parameters of fcap200_isp Module
Name Default Value Description
src 0 Number of the capture sources
src_w 1280 Width of the capture source
src_h 720 Height of the capture source
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Name Default Value Description
src_x 3 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
src_y 2 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
inv_clk 0 Invert clock
0: None
1: Invert
bv_polarity 0 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 0 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
input_clk 27000000 The capture clock frequency is input from the sensor.
This feature is supported on:
Vcap200_v3: V0.3.07
Input API: V1.9.00
3.4.4 fcap200_tw9910 Module Table 3-7 lists the module parameters while inserting this driver.
Table 3-7. Parameters of fcap200_tw9910 Module
Name Default Value Description
chip_num 1 TW9910 chip number
iaddr { 0x8a, 0x88 } I2C address for TW9910
src 0 Number of the capture sources
inv_clk 1 Inverted clock
0: None
1: Invert
bUse_VFS 0 0: Use bit F as frame start
1: Use bit V as frame start
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Name Default Value Description
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
OData 0 0: Throughput of one data path at 27 MHz for the 1-channel video data
1: Throughput of one data path at 54 MHz for the 2-channel video data
2: Throughput of one data path at 108 MHz for the 4-channel video data
Not used in GM8126
inv_demuxclk {0, 0} Invert the demux pixel clock
Not used in GM8126
cfg_pmu_eclk 0 Configure the PMU external clock
Not used in GM8126
cfg_pmu_demux -1 0: demux 0
1: demux 1
-1: demux all
Not used in GM8126
cfg_channel_switch 0 0: Disable
1: Enable
Not used in GM8126
3.4.5 fcap200_ov7740 Module Table 3-8 lists the module parameters while inserting this driver.
Table 3-8. Parameters of fcap200_ov7740 Module
Name Default Value Description
iaddr 0x42 I2C address for OV7740
src 0 Number of the capture sources
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
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Name Default Value Description
1: Invert
bUse_VFS 0 0: Use bit F as frame start
1: Use bit V as frame start 3.4.6 fcap200_poa030d Module Table 3-9 lists the module parameters while inserting this driver.
Table 3-9 Parameters of fcap200_poa030d Module
Name Default Value Description
iaddr 0xdc I2C address for POA030D
src 0 Number of the capture sources
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
1: Invert
bUse_VFS 0 0: Use bit F as frame start
1: Use bit V as frame start
3.4.7 fcap200_ov10630 Module Table 3-10 lists the module parameters while inserting this driver.
Table 3-10. Parameters of fcap200_ov10630 Module
Name Default Value Description
iaddr 0x60 I2C address for OV10630
src 0 Number of the capture sources
src_x 4 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
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Name Default Value Description
src_y 3 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
bv_polarity 0 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 1 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
1: Invert
3.4.8 fcap200_ov7720 Module Table 3-11 lists the module parameters while inserting this driver.
Table 3-11. Parameters of fcap200_ov7720 Module
Name Default Value Description
iaddr 0x42 I2C address for OV7720
src 0 Number of the capture sources
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
1: Invert
bUse_VFS 0 0: Use bit F as frame start
1: Use bit V as frame start
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3.4.9 fcap200_hm2055 Module Table 3-12 lists the module parameters while inserting this driver.
Table 3-12. Parameters of fcap200_hm2055 Module
Name Default Value Description
iaddr 0x48 I2C address for OV10630
src 0 Number of the capture sources
src_x 3 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
src_y 4 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
bv_polarity 1 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 1 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
1: Invert
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3.4.10 fcap200_mt9v136 Module Table 3-13 lists the module parameters while inserting this driver.
Table 3-13. Parameters of fcap200_mt9v136 Module
Name Default Value Description
iaddr 0x90 I2C address for MT9V136
src 0 Number of the capture sources
src_x 3 Horizontal pixel capture start point of the source image
(Effect on VP_H_REF_DEF = 1 of the SRCIF[0x0044] register)
src_y 4 Vertical pixel capture start point of the source image
(Effect on VP_V_REF_DEF = 1 of the SRCIF[0x0044] register)
bv_polarity 1 0: Video port vertical control timing is active low.
1: Video port vertical control timing is active high.
bh_polarity 1 0: Video port horizontal control timing is active low.
1: Video port horizontal control timing is active high.
port_used -1 External signal connected to the chip port
Bit X = Port X
Not used in GM8126
inv_clk 0 Invert clock
0: None
1: Invert
pal 0 Analog output PAL mode (Need to switch the D_SLB0 jumper to PAL)
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Chapter 4 Capture Proc Nodes
The capture module provides the proc nodes. Users can read the captured information or enable the
debugging message through these nodes. A sample of these nodes is listed below.
Figure 4-1. Proc Nodes of Capture Module
/ # cat /proc/vcap_drv/
/proc/vcap_drv/AutoCheck_IN /proc/vcap_drv/cn_dbg_mask /proc/vcap_drv/input_module_table
/proc/vcap_drv/cn_TriggerMode /proc/vcap_drv/fcap_dev0/ /proc/vcap_drv/property
/proc/vcap_drv/cn_dbg_ch /proc/vcap_drv/fcap_dev1/
/ # cat /proc/vcap_drv/fcap_dev0/
/proc/vcap_drv/fcap_dev0/dump_lli /proc/vcap_drv/fcap_dev0/dump_reg /proc/vcap_drv/fcap_dev0/status
/ # cat /proc/vcap_drv/fcap_dev0/
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The following table shows the proc nodes of the capture module.
AutoCheck_IN
cn_TriggerMode
cn_dbg_ch
cn_dbg_mask
input_module_table
property
dump_lli
dump_reg
/proc/vcap_drv
fcap_devX
status
4.1 /proc/vcap_drv Proc Nodes 4.1.1 AutoCheck_IN User can use the /proc/vcap_drv/AutoCheck_IN node to disable/enable the automatic detection of the
input signal.
Usage:
• Get the current value
cat /proc/vcap_drv/AutoCheck_IN
• Set the signal detection period value (0: Disable)
echo [value (ms)] > /proc/vcap_drv/AutoCheck_IN
/ # cat /proc/vcap_drv/AutoCheck_IN
Auto check Input signal. 0: Disable
Current value is 1000 ms.
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4.1.2 cn_TriggerMode User can use the /proc/vcap_drv/cn_TriggerMode node to start/stop the operation of the capture debug
message.
Usage:
• Get the current value
cat /proc/vcap_drv/cn_TriggerMode
• Set the trigger mode value
echo [value] > /proc/vcap_drv/cn_TriggerMode
Value: 0x00000000 ~ 0xFFFFFFFF
Bit 0: Stop [0: Off, 1: On]
Bit 1: Start [0: Off, 1: On]
Others: Reserved
4.1.3 cn_dbg_ch User can use the /proc/vcap_drv/cn_dbg_ch node to disable/enable the operation of the capture debug
message for different channels.
Usage:
• Get the current value
cat /proc/vcap_drv/cn_dbg_ch
• Set the channel value
echo [value] > /proc/vcap_drv/cn_dbg_ch
Value: 0x00000000 ~ 0xFFFFFFFF
Bit X: Control the channel_X debugging message operation. Set to ‘0’ to enable and ‘1’ to disable.
/ # cat /proc/vcap_drv/cn_dbg_ch
cn_debug_ch=0x0
/ # cat /proc/vcap_drv/cn_TriggerMode
Trigger mode= [start(bit1) stop(bit0)] (31-2 reserve)
Mode=0x0
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4.1.4 cn_dbg_mask User can use the /proc/cn_dbg_mask node to trigger different capture debug messages for output.
Usage:
• Get the current value
cat /proc/vcap_drv/cn_dbg_mask
• Set the mask value of the debugging message
echo [value] > /proc/vcap_drv/cn_dbg_mask
Value: 0x00000000 ~ 0xFFFFFFFF
Bit Description Value
0 Function entry/leave 0: On, 1: Off
1 IOCTL name 0: On, 1: Off
2 IOCTL parameter 0: On, 1: Off
4 Driver state machine flow 0: On, 1: Off
5 Skip the function status trace 0: On, 1: Off
6 Buffer IN/OUT 0: On, 1: Off
7 DMA buffer information (Address, offset, and size)
0: On, 1: Off
8 Trace the link list table 0: On, 1: Off
9 Performance information 0: On, 1: Off
29 Memory pool trace of the link list table 0: On, 1: Off
30 Dump the register/LLI table when error occurs 0: On, 1: Off
31 Trace the link list table (Include all table contents)
0: On, 1: Off
/ # cat /proc/vcap_drv/cn_dbg_mask
cn_debug_mask=0xffffffff
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4.1.5 input_module_table User can use the /proc/vcap_drv/input_module_table node to display which input driver have been
installed. After insert the fcap200_xxx.ko input driver, the information of the input driver is shown in the
following table.
Item Description
name Name of the input module
grab type ID of the input module
Channel number ID assigned by the capture driver
source Number of the capture sources
Usage:
• Get the current value
cat /proc/vcap_dvr/input_module_table
/ # cat /proc/vcap_drv/input_module_table
Name Grab Type Channel Number Source
GENINPUT 42 0 0
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4.1.6 Property User can use the /proc/vcap_drv/property node to display all configuration property of each capture path.
User should specify the number of the capture paths before display.
Usage:
• Get the configuration property value of the current capture path
cat /proc/vcap_drv/property
/ # cat /proc/vcap_drv/property
Capture fd 0x0 property
========================
bg_x=0
bg_y=0
bg_width=352
bg_height=240
buf_y0=0
buf_u0=0
buf_v0=0
buf_y1=90112
buf_u1=0
buf_v1=0
width=352
height=240
DI_mode=0
color=2
mode=1
dma_order=0
scaler_indep=1
do_clamp=0
updata=0
start=0
stop=0
resume=0
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• Set the number of the capture paths for display
echo [capture-path] > /proc/vcap_drv/property
capture-path=>0xAB [ A: capture number, from 0~1, B: path number from 0~3 ]
pause=0
input_ch=0
input_mode=1
VG_E_header_size=0
buf_vbi0=0
buf_vbi1=0
bCrop=0
crop_x=0
crop_y=0
crop_w=0
crop_h=0
FrameRate_Numerator=30
FrameRate_Denominator=30
InputFrameRatio=0
SharePath=0
H_Flip=0
V_Flip=0
sharpness=0
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4.2 /proc/vcap_drv/fcap_devX Proc Nodes The following sections describe these proc nodes.
4.2.1 dump_lli User can use the /proc/vcap_drv/fcap_devX/dump_lli node to display the hardware link list table when
capture is set to the link list mode.
Usage:
• Get the current value
cat /proc/vcap_drv/fcap_devX/dump_lli
/ # cat /proc/vcap_drv/fcap_dev0/dump_lli[0]:P0 LinkList Table =========== [0]:[0:0x01d20b01](P0) [0]: (0) 0x83000032 [0]: (1) 0x81060400 [0]: (2) 0x81098800 [0]: (3) 0x810a6900 [0]: (4) 0x000f0218 [0]: (5) 0x00000280 [0]: (6) 0x0001003c [0]: (7) 0x00008180 [0]: (8) 0x00030040 [0]: (9) 0x00000000 [0]: (10) 0x00030004 [0]: (11) 0x00000101 [0]: (12) 0xc1d20901 [0]:[1:0x01d20901](P0) [0]: (0) 0x00000000 [0]: (1) 0x812e0400 [0]: (2) 0x81318800 [0]: (3) 0x81326900 [0]: (4) 0x000f0218 [0]: (5) 0x00000280 [0]: (6) 0x0001003c [0]: (7) 0x00008180 [0]: (8) 0x00030040 [0]: (9) 0x00000000 [0]: (10) 0x00030004 [0]: (11) 0x00000101 [0]: (12) 0xc1d20e81 [0]:[E:0x01d20e01] [0]: (0) 0x00000000
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4.2.2 dump_reg User can use the /proc/vcap_drv/fcap_devX/dump_reg node to display the register value of a capture.
Usage:
• Get the current value
cat /proc/vcap_drv/fcap_devX/dump_reg
/ # cat /proc/vcap_drv/fcap_dev0/dump_reg [0]:0x0000: 10028000 00000000 00000000 00000000 [0]:0x0010: 02d00500 00000000 02d00500 08000000 [0]:0x0020: 00f00140 00000000 00f00140 00f00140 [0]:0x0030: 00000000 00000000 00000505 00000100 [0]:0x0040: 00000000 00080000 00080000 00080000 [0]:0x0050: 02d00500 00000000 02d00500 02d00500 [0]:0x0060: 00000000 00000000 02d00500 00f00140 [0]:0x0100: 00000000 00000000 00000000 00000000 [0]:0x0110: 00000000 00000000 00000000 00000000 [0]:0x0120: 00000000 00000000 00000000 00000000 [0]:0x0130: 00000000 00000000 00000000 00000000 [0]:0x0140: 00000000 00000000 00000000 00000000 [0]:0x0150: 00000000 00000000 00000000 00000000 [0]:0x0160: 00000000 00000000 00000000 00000000 [0]:0x0170: 00000000 00000000 00000000 00000000 [0]:0x0180: 00000000 00000000 00000000 00000000 [0]:0x0190: 00000000 00000000 00000000 00000000 [0]:0x01a0: 00000000 00000000 00000000 00000000 [0]:0x01b0: 00000000 00000000 00000000 00000000 [0]:0x01c0: 00000000 00000000 00000000 00000000 [0]:0x01d0: 00000000 00000000 00000000 00000000 [0]:0x01e0: 3c140005 0000000f 0000000f 0000000f [0]:0x01f0: 00000000 00000000 00000000 00000000 [0]:0x0200: 40000001 40000001 00000000 00000000 [0]:0x0210: 00000000 00000000 00000280 000000a0 [0]:0x0220: 010e0400 00000000 00000000 00000000 [0]:0x0230: 01118800 00000000 00000000 00000000 [0]:0x0240: 01126900 00000000 00000000 00000000 [0]:0x0250: 01862e00 00000000 00000000 00000000 [0]:0x0260: 01867900 00000000 00000000 00000000 [0]:0x0270: 01868bc0 00000000 00000000 00000000 [0]:0x0280: 01d20e81 01d30b01 01d30b01 01d30b01
4.2.3 Status User can use the /proc/vcap_drv/fcap_devX/status node to display the machine state and FIFO status of
each driver for each path.
Usage:
• Get the current status
cat /proc/vcap_drv/fcap_devX/status
/ # cat /proc/vcap_drv/fcap_dev0/status
P0 ST fifo P1 ST fifo P2 ST fifo P3 ST fifo
0 0 0 0 0 0 0 0
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Chapter 5 Capture Device Nodes for V4L
GM8126 has two captures. Each capture has two paths. When using the V4L capture driver, the V4L
capture device node will be created in /dev/. The following table shows the device nodes in the single-step
fire mode and link list mode.
SSF Mode
Capture # Path # Device Node
Path_0 /dev/video0 Capture_0
Path_1 /dev/video1
Path_0 /dev/video2 Capture_1
Path_1 /dev/video3
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LLI Mode
Capture # Path # Device Node
Path_0
(HW Path_0)
/dev/video0
Path_1
(HW Path_1)
/dev/video1
Path 2
(Sub Path_0)
/dev/video2
Capture_0
Path 3
(Sub Path_1)
/dev/video3
Path_0
(HW Path_0)
/dev/video4
Path_1
(HW Path_1)
/dev/video5
Path 2
(Sub Path_0)
/dev/video6
Capture_1
Path 3
(Sub Path_1)
/dev/video7
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Chapter 6 Capture OSD and Mask
Each capture OSD supports four independent OSD windows. Users can get the maximum display fonts of
OSD. The maximum fonts are put in the capture from /module/vcap200_v3/config_8126. Each capture
has two paths. In GM8126, all paths support OSD, but the capabilities are different. The following table
shows the OSD capabilities.
Capture Path Font RAM Size (Bit) Display RAM Size (Bit) Font Number
CAP#0-PATH#0 2016 x 12 x 2 256 x 8 224
CAP#0-PATH#1 201 6x 12 x 1 128 x 8 112
CAP#1-PATH#0 2016 x 12 x 1 128 x 8 112
CAP#1-PATH#1 2016 x 12 x 1 128 x 8 112
The unit of fonts stored in the OSD RAM is 12 x 18. The following example is 12 x 12.
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The following table lists the default font database for each capture path.
Font Index
0 0x30
1 0x31
2 0x32
3 0x33
4 0x34
5 0x35
6 0x36
7 0x37
8 0x38
9 0x39
A 0x41
B 0x42
C 0x43
D 0x44
E 0x45
F 0x46
G 0x47
H 0x48
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Font Index
I 0x49
J 0x4A
K 0x4B
L 0x4C
M 0x4D
N 0x4E
O 0x4F
P 0x50
Q 0x51
R 0x52
S 0x53
T 0x54
U 0x55
V 0x56
W 0x57
X 0x58
Y 0x59
Z 0x5A
space 0x20
= 0x3D
, 0x2C
- 0x2D
/ 0x2F
: 0x3A
Capture also supports the video mask. Users can use it to mask any video region. It supports eight
independent mask windows. It includes all paths.
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6.1 OSD/Mask Device Nodes Users can use the capture OSD/Mask feature from the device nodes. The single-step fire mode and link list
mode have different reference nodes. The following table shows the OSD nodes in the SSF mode.
SSF Mode
Capture # Path # Device Node
Path_0 /dev/fosd00 Capture_0
Path_1 /dev/fosd01
Path_0 /dev/fosd10 Capture_1
Path_1 /dev/fosd11
The following table shows the OSD nodes in the LLI mode.
LLI Mode
Capture # Path # Device Node
Path_0
(HW Path_0)
/dev/fosd00
Path_1
(HW Path_1)
/dev/fosd01
Path 2
(Sub Path_0)
/dev/fosd02
Capture_0
Path 3
(Sub Path_1)
/dev/fosd03
Path_0
(HW Path_0)
/dev/fosd10
Path_1
(HW Path_1)
/dev/fosd11
Path 2
(Sub Path_0)
/dev/fosd12
Capture_1
Path 3
(Sub Path_1)
/dev/fosd13
