Global Routing - Indian Institute of Technology Madras€¦ · ¨ Routing capacity, timing and...

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Global Routing

Presented By:Sridhar H RangarajanIBM STG India Enterprise Systems Development

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Global Routing

IntroductionTerminology and DefinitionsOptimization GoalsRepresentations of Routing RegionsThe Global Routing FlowSingle-Net Routing

n Rectilinear Routingn Global Routing in a Connectivity Graphn Finding Shortest Paths with Dijkstra’s Algorithmn Finding Shortest Paths with A* Search

Full-Netlist Routingn Routing by Integer Linear Programmingn Rip-Up and Reroute (RRR)

Modern Global Routingn Pattern Routingn Negotiated-Congestion Routing

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Given a placement, a netlist and technology information, n determine the necessary wiring, e.g., net topologies and specific

routing segments, to connect these cells n while respecting constraints, e.g., design rules and routing resource

capacities, and n optimizing routing objectives, e.g., minimizing total wirelength and

maximizing timing slack.

Introduction

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Terminology:n Net: Set of two or more pins that have the same electric potentialn Netlist: Set of all nets. n Congestion: Where the shortest routes of several nets are

incompatible because they traverse the same tracks. n Fixed-die routing: Chip outline and routing resources are fixed.n Variable-die routing: New routing tracks can be added as needed.

Introduction

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130 nm 90 nm 65 nm 45 nm 32 nmM1M2M3M4M5B1B2

M1M2M3M4B1B2B3

E1

E2

M1M2M3M4

B1B2

C1C2

B3E1

U1

U2

M1M2M3M4

B1B2B3

E1

E2

M5

W1

W2

M1M2

M4M5M6

M3

Representative layer stacks for 130 nm - 32 nm technology nodes

Each layer has a preferred direction and alternates between layers

Introduction

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Introduction - Pitch

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1X

2X

4X

Introduction – Different wire sizes

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Introduction - Via

Top Metal Layer m3

Middle Via Layer v2

Bottom Metal Layer m2

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Gcells (Tiles) with macro cell layout

Metal1

Metal2

Metal3

Metal4 etc.

Introduction - GCell

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n Global tile node & global edgen Overflow: the amount of routing demand

that exceeds the given capacity

11

Global tilenode

Global edge

Tile

Tile boundary

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Ø Total Overflow

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C

D

A

B

43

214

3

4

1

1

654

Netlist:

N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4}N3 = {C2, D5}N4 = {B1, A1, C3}

Technology Information (Design Rules)

Placement result

Introduction: General Routing Problem

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Netlist:

N1 = {C4, D6, B3}N2 = {D4, B4, C1, A4}N3 = {C2, D5}N4 = {B1, A1, C3}



C

D

A

B

43

214

3

4

1

1

654

N1

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Netlist:

N1 = {C4, D6, B3}N2 = {D4, B4, C1, A4}N3 = {C2, D5}N4 = {B1, A1, C3}



C

D

A

B

43

214

3

4

1

1

654

N2 N3N4 N1

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Timing-Driven Routing

GlobalRouting

DetailedRouting

Large Single-Net Routing

Coarse-grain assignment of routes to routing regions

Fine-grain assignment of routes to routing tracks

Net topology optimization and resource allocation to critical nets

Power (VDD) and Ground (GND) routing

Routing

Geometric Techniques

Non-Manhattanand clock routing

Global Routing

Multi-Stage Routing of Signal Nets

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n Wire segments are tentatively assigned (embedded) within the chip layout

n Chip area is represented by a coarse routing gridn Available routing resources are represented by edges with

capacities in a grid graph Þ Nets are assigned to these routing resources

Global Routing

Introduction

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N3

N3

N1 N2N1

N3

N1 N2

N3

N3

N1 N2N1

N3

N1 N2

HorizontalSegment ViaVertical

Segment

Detailed Routing

Introduction

Global Routing

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5.1.2 Globalverdrahtung

Detailed Routing

Placement

Congestion Map

Wire Tracks

Global Routing

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Terminology and Definitions

• Routing Track: Horizontal wiring path

• Routing Column: Vertical wiring path

• Routing Region: Region that contains routing tracks or columns

• Uniform Routing Region: Evenly spaced horizontal/vertical grid

• Non-uniform Routing Region: Horizontal and vertical boundaries that are aligned to external pin connections or macro-cell boundaries resulting in routing regions that have differing sizes

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Channel

Standard cell layout (Two-layer routing)


Rectangular routing region with pins on two opposite sides

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Routing channel

Channel

Routing channel


Standard cell layout (Two-layer routing)

Rectangular routing region with pins on two opposite sides

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Capacity

A A

B B

B

B B

BC

C

DC

CD

dpitchh

Horizontal Routing Channel


Number of available routing tracks or columns

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n For single-layer routing, the capacity is the height h of the channel divided by the pitchdpitch

n For multilayer routing, the capacity σ is the sum of the capacities of all layers.

Capacity

åÎ ú

úû

ú

êêë

ê=

Layerslayer pitch layerdhLayersσ

)()(

A A

B B

B

B B

BC

C

DC

CD

dpitchh

Horizontal Routing Channel


Number of available routing tracks or columns

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A

B

BC

C

3B

AB

VerticalChannel

VerticalChannel

HorizontalChannel

HorizontalChannel

Switchbox (Two-layer macro cell layout)


Intersection of horizontal and vertical channels

Horizontal channel is routed after vertical channel is routed

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A BC

CB

AB

B C

VerticalChannel

HorizontalChannel

T-junction (Two-layer macro cell layout)


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2D and 3D Switchboxes

Metal5

Bottom pin connectionon 3D switchbox

3D switchbox

2D switchbox

Pin on channel boundary

Top pin connection on cell

Horizontalchannel

Metal4

Metal3Metal2Metal1

Vertical channel


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Metal1(Standard cells)

Metal2(Cell ports)

Metal3

Metal4 usw.


Gcells (Tiles) with standard cells

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Metal1(Back-to-back-standard cells)

Metal2(Cell ports)

Metal3

Metal4 etc.


Gcells (Tiles) with standard cells (back-to-back)

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n Global routing seeks to¨ determine whether a given placement is routable, and ¨ determine a coarse routing for all nets within available routing

regions

n Considers goals such as¨ minimizing total wirelength, and¨ reducing signal delays on critical nets

Optimization Goals

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Optimization Goals

Full-custom design

B

FA

C

D

E

H

V

H

A B

F

D H

V

C E

1

2

3

4

55

B

FA

C

D

E1 23

4

(2) Channel ordering

B

FA

C

D

E

(1) Types of channels

Layout is dominated by macro cells and routing regions are non-uniform

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Optimization Goals

Standard-cell design

A

A

A

A

A

Feedthroughcells

If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows

Variable-die,standard cell design:

Total height = ΣCell row heights + All channel heights

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Optimization Goals

Standard-cell design

Steiner tree solution with minimal wirelength

Steiner tree solution withfewest feedthrough cells

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n Routing regions are represented using efficient data structures

n Routing context is captured using a graph, where ¨ nodes represent routing regions and ¨ edges represent adjoining regions

n Capacities are associated with both edges and nodes to represent available routing resources

Representations of Routing Regions

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1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

Grid graph model

ggrid = (V,E), where the nodes v Î V represent the routing grid cells (gcells)and the edges represent connections of grid cell pairs (vi,vj)


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1 2 3

4

5

6

7

8

9 1 2 3

4

5

6

7

8

9

Channel connectivity graph

G = (V,E), where the nodes v Î V represent channels, and the edges E represent adjacencies of the channels


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1

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Switchbox connectivity graph

G = (V, E), where the nodes v Î V represent switchboxesand an edge exists between two nodes if the corresponding switchboxes are on opposite sides of the same channel


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The Global Routing Flow – General Idea1. Defining the routing regions (Region definition)

¨ Layout area is divided into routing regions

¨ Nets can also be routed over standard cells

¨ Regions, capacities and connections are represented by a graph

2. Mapping nets to the routing regions (Region assignment)

¨ Each net of the design is assigned to one or several routing regions to connect all of its pins

¨ Routing capacity, timing and congestion affect mapping

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B (2, 6)

A (2, 1)

C (6, 4)

B (2, 6)

A (2, 1)

C (6, 4)S (2, 4)

Rectilinear Steiner minimum tree (RSMT)

Rectilinear minimum spanning tree (RMST)

Rectilinear Routing

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Rectilinear Routing

• An RMST can be computed in O(p2) time, where p is the number of terminalsin the net using methods such as Prim’s Algorithm

• Prim’s Algorithm builds an MST by starting with a single terminal and greedily adding least-cost edges to the partially-constructed tree

• Advanced computational-geometric techniques reduce the runtime to O(p log p)

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Characteristics of an RSMTn An RSMT for a p-pin net has between 0 and p – 2 (inclusive) Steiner

pointsn The degree of any terminal pin is 1, 2, 3, or 4 n The degree of a Steiner point is either 3 or 4n A RSMT is always enclosed in the minimum bounding box (MBB) of

the netn The total edge length LRSMT of the RSMT is at least half the perimeter

of the minimum bounding box of the net: LRSMT ³ LMBB / 2

Rectilinear Routing

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Hanan grid

n Adding Steiner points to an RMST can significantly reduce the wirelength

n Maurice Hanan proved that for finding Steiner points, it suffices to consider only points located at the intersections of vertical and horizontal lines that pass through terminal pins

n The Hanan grid consists of the lines x = xp, y = yp that pass through the location (xp,yp) of each terminal pin p

n The Hanan grid contains at most (n2-n) candidate Steiner points (n = number of pins), thereby greatly reducing the solution space for finding an RSMT

Rectilinear Routing

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Hanan points ( ) RSMTIntersection linesTerminal pins

Rectilinear Routing

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Definining routing regions Pins assigned to grid cellsPin connections

Rectilinear Routing

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Pins assigned to grid cells Assigned routing regionsand feedthrough cells

A A

A

A

A A A

A

A

A A

Rectilinear Steiner minimum tree (RSMT)

Sequential Steiner Tree Heuristic

Rectilinear Routing

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A Sequential Steiner Tree Heuristic

1. Find the closest (in terms of rectilinear distance) pin pair, construct their minimum bounding box (MBB)

2. Find the closest point pair (pMBB,pC) between any point pMBB on the MBB and pC from the set of pins to consider

3. Construct the MBB of pMBB and pC

4. Add the L-shape that pMBB lies on to T (deleting the other L-shape). If pMBB is a pin, then add any L-shape of the MBB to T.

5. Goto step 2 until the set of pins to consider is empty

Rectilinear Routing

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1

Rectilinear Routing: Example Sequential Steiner Tree Heuristic

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1

2

1


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1

2

3

1


MBB

pc

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1

2

3 1

2

3

1 2 4


pMBB

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1

2

3 1

2

3

4

5

1

2

3

41 2 3


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1 2 3

4


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1 2 3

4 5


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4 5 6


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Switchboxconnectivity graph

Global Routing in a Connectivity Graph

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Switchboxconnectivity graph

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n Combines switchboxes and channels, handles non-rectangular block shapes

n Suitable for full-custom design and multi-chip modules

Overview:

Routing regions

1 2 3

4 5 6 7

8 9

10 11 12

B

A

B

A


Graph-based path search

2,2

4,2

1,2

2,7

4,2

0,1 1,2

3,1

2,2

4,24,2

0,4

Graph representation

1 2 3

4

2,2

4,2

1,2

2,7

4,2

1,2 1,2

5 68

4,2

7

2,2

4,2

9

10

4,2

1,5

11 12

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Horizontal macro-cell edges Vertical macro-cell edges

Defining the routing regions


+

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67

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101112

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1

Defining the connectivity graph


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1,2

Horizontal capacity of routing region 1

Vertical capacity of routing region 1

2 Tracks

1 Tr

ack

1


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101112

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2,2

2,2

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3,2

1,2

1,2

2,1

3,1

1,3

2,3

1,1

2,1

3,1 3,1

1,1

2,1

4,1

3,1

1,1

6,1

3,1

1,1

1,1

1,4

3,4

1,8

1


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Algorithm Overview 1. Define routing regions 2. Define connectivity graph 3. Determine net ordering4. Consider each net

a) Free corresponding tracks for net’s pins b) Decompose net into two-pin subnets c) Find shortest path for subnet connectivity graph d) If no shortest path exists, do not route, otherwise, assign subnet to the

nodes of shortest path and update routing capacities 5. If there are unrouted nets, goto Step 5, otherwise END


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l

1 2 3

4 5 6 7

8 9

10 11 12

B

A

B

Aw

1 2 3

4

2,2

4,2

1,2

2,7

4,2

1,2 1,2

5 68

4,2

7

2,2

4,2

9

10

4,2

1,5

11 12

Example

Global routing of the nets A-A and B-B

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l

1 2 3

4 5 6 7

8 9

10 11 12

B

A

B

Aw

1 2 3

4

2,2

4,2

1,2

2,7

4,2

1,2 1,2

5 68

4,2

7

2,2

4,2

9

10

4,2

1,5

11 12

B

AB

A

0,1

3,1

0,4

1 2 3

4

2,2

4,2

1,2

2,7

4,2

1,2

5 68

7

2,2

4,2

9

10

4,2

11 12

Example


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l

1 2 3

4 5 6 7

8 9

10 11 12

B

A

B

Aw

1 2 3

4

2,2

4,2

1,2

2,7

4,2

1,2 1,2

5 68

4,2

7

2,2

4,2

9

10

4,2

1,5

11 12

B

AB

A

B

AB

A

1 2 3

4

2,2

4,2

1,2

2,7

4,2

0,1 1,2

5 68

3,1

7

2,2

4,2

9

10

4,2

0,4

11 12

1

4 1,2 0,1

5 6

4,2

0,4

2 3

1,1

3,1

1,7

4,1

1,1

8

2,1

7

1,1

3,1

9

10

11 12

Example


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1 2 3

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B

A

B

Aw

B

AB

A

Example


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1 2 3

3,1 3,4 3,3

1,4 1,1 1,4 1,3

3,4 3,1 3,3

45 6 7

8 9 10

B

AB

A

4 5 7

8

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9 10

1 2 3Example

Determine routability of a placement

B

AB

A

4 5 7

8

6

9 10

1 2 3

?1 2 3

3,1 3,4 3,3

0,3 0,1 0,4 0,2

3,4 3,1 2,2

45 6 7

8 9 10

B

AB

A

4 5 7

8

6

9 10

1 2 3

1 2 3

3,1 3,4 3,3

0,3 0,1 0,4 0,2

3,4 3,1 2,2

45 6 7

8 9 10

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1 2 3

3,1 3,4 3,3

1,4 1,1 1,4 1,3

3,4 3,1 3,3

45 6 7

8 9 10

B

AB

A

4 5 7

8

6

9 10

1 2 3

B

AB

A

4 5 7

8

6

9 10

1 2 3

B

AB

A

4 5 7

8

6

9 10

1 2 3

1 2 3

3,1 3,4 3,3

0,3 0,1 0,4 0,2

3,4 3,1 2,2

45 6 7

8 9 10

1 2 3

2,0 2,3 3,3

0,2 0,0 0,3 0,2

2,3 2,0 2,2

45 6 7

8 9 10

Example


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B

AB

A

4 5 7

8

6

9 10

1 2 3

B

AB

A

4 5 7

8

6

9 10

1 2 3

Example


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Single-Source Shortest Path Problem

Single-Source Shortest Path Problem - The problem of finding shortest paths from a source vertex v to all other vertices in the graph.

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Dijkstra's algorithm Dijkstra's algorithm - is a solution to the single-source shortest path problem in graph theory.

Works on both directed and undirected graphs. However, all edges must have nonnegative weights.

Approach: Greedy

Input: Weighted graph G={E,V} and source vertex v∈V, such that all edge weights are nonnegative

Output: Lengths of shortest paths (or the shortest paths themselves) from a given source vertex v∈V to all other vertices

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Dijkstra's algorithm - Pseudocode

dist[s] ←0 (distance to source vertex is zero)for all v ∈ V–{s}

do dist[v] ←∞ (set all other distances to infinity) S←∅ (S, the set of visited vertices is initially empty) Q←V (Q, the queue initially contains all vertices) while Q ≠∅ (while the queue is not empty) do u ← mindistance(Q,dist) (select the element of Q with the min. distance)

S←S∪{u} (add u to list of visited vertices) for all v ∈ neighbors[u]

do if dist[v] > dist[u] + w(u, v) (if new shortest path found)then d[v] ←d[u] + w(u, v) (set new value of shortest path)

(if desired, add traceback code)return dist

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Dijkstra Example

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Finding Shortest Paths with A* Search

n A* search operates similarly to Dijkstra’s algorithm, but extends the cost function to include an estimated distance from the current node to the target

n Expands only the most promising nodes; its best-first search strategy eliminates a large portion of the solution space

A* search(exploring 6 nodes)

Dijkstra‘s algorithm(exploring 31 nodes)

12

34

1356

78

910

2911

12

1415

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18

19212022

2325

2627

2830

24

OOO31

12

43

5 O

O6O

s s

t ts Source

t

O

Target

Obstacle

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Finding Shortest Paths with A* Search

n Bidirectional A* search: nodes are expanded from both the source and target until the two expansion regions intersect

n Number of nodes considered can be reduced

Bidirectional A* search

12

43

5 O

OO 1

2

65

3 O

OO4

s s

t t

Unidirectional A* search

s Source

t

O

Target

Obstacle

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Full-Netlist Routing

n Global routers must properly match nets with routing resources, without oversubscribing resources in any part of the chip

n Signal nets are either routed ¨ simultaneously, e.g., by integer linear programming, or ¨ sequentially, e.g., one net at a time

n When certain nets cause resource contention or overflow for routing edges, sequential routing requires multiple iterations: rip-up and reroute

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Rip-Up and Reroute (RRR)

n Rip-up and reroute (RRR) framework: focuses on hard-to-route nets

n Idea: allow temporary violations, so that all nets are routed, but then iteratively remove some nets (rip-up), and route them differently (reroute)

D

BD’

A’

B’

C’C

A

D

B

C

AD’

A’

B’

C’

Routing without allowing violations

WL = 21

D

B

C

AD’

A’

B’

C’

Routing with allowing violations and RRR

WL = 19

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n General flow for modern global routers, where each router uses a unique set of optimizations:

Global Routing Instance

Net Decomposition Initial Routing

3D Layer Assignment

Final Improvements

no

yes

Rip-up and Reroute

Violations?

(optional)

Modern Global Routing

3D to 2D capacity mapping

Net Decomposition

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n Negotiated-Congestion Routing¨ Each edge e is assigned a cost value cost(e) that reflects the demand for

edge e¨ A segment from net net that is routed through e pays a cost of cost(e) ¨ Total cost of net is the sum of cost(e) values taken over all edges used

by net:

¨ The edge cost cost(e) is increased according to the edge congestion φ(e), defined as the total number of nets passing through e divided by the capacity of e:

¨ A higher cost(e) value discourages nets from using e and implicitly encourages nets to seek out other, less used edges

Þ Iterative routing approaches (Dijkstra’s algorithm, A* search, etc.) find routes with minimum cost while respecting edge capacities

åÎ

=nete

ecostnetcost )()(

)()()(eσeηeφ =

Modern Global Routing

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Summary

n Input: netlist, placement, obstacles + (usually) routing gridn Partitions the routing region (chip or block) into global routing cells

(gcells)n Considers the locations of cells within a region as identicaln Plans routes as sequences of gcellsn Minimizes total length of routes and, possibly, routed congestionn May fail if routing resources are insufficient

¨ Variable-die can expand the routing area, so can't usually fail¨ Fixed-die is more common today (cannot resize a block in a larger chip)

n Interpreting failures in global routing¨ Failure with many violations => must restructure the netlist

and/or redo global placement¨ Failure with few violations => detailed routing may be able to fix the

problems

Lien

ig 91

Summaryn Usually ~50% of the nets are two-pin nets, ~25% have three pins,

~12.5% have four, etc.¨ Two-pin nets can be routed as L-shapes or using maze search

(in a connectivity graph of the routing regions)¨ Three-pin nets usually have 0 or 1 branching point¨ Larger nets are more difficult to handle

n Pattern routing¨ For each net, considers only a small number of shapes (L, Z, U, T, E)¨ Very fast, but misses many opportunities¨ Good for initial routing, sometimes is sufficient

n Routing pin-to-pin connections¨ Breadth-first-search (when costs are uniform)¨ Dijkstra's algorithm (non-uniform costs)¨ A*-search (non-uniform costs and/or using additional distance information)

Global Routing - Indian Institute of Technology Madras€¦ · ¨ Routing capacity, timing and...

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