Getting Started with the Multi-Standard …cache.freescale.com/files/dsp/doc/quick_ref_guide/...DSPA...

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Freescale SemiconductorGetting Started Guide

The Freescale SPTWIMAXCC1E multi-standard baseband advanced mezzanine card (AMC) channel card is a development platform for rapid development of baseband functionality for various wireless air interface standards, including but not limited to IEEE® 802.16™ and wideband code division multiple access (WCDMA). The board includes a PowerQUICC™ MPC8555 processor, two MSC8126 DSPs, an EP2S180F1508C5N algorithmic FPGA, and an EP1SGX40DF1020C5N SERDES FPGA. This document assists the first-time board user in getting started using the channel card.

Contents

1 Channel Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Install and Configure CodeWarrior Development

Studio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32.1 Multiple CodeWarrior Installations . . . . . . . . . . . .32.2 Initial CodeWarrior Configuration . . . . . . . . . . . . .42.3 Parallel Port Configuration . . . . . . . . . . . . . . . . . . .4

3 Connect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power Up the Board. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Board Configuration Options . . . . . . . . . . . . . . . . .94.1.1 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94.1.2 MPC8555 Linux Boot . . . . . . . . . . . . . . . . . . . .104.1.3 DSP DSI Boot. . . . . . . . . . . . . . . . . . . . . . . . . . 104.1.4 Powerup Options . . . . . . . . . . . . . . . . . . . . . . . .114.2 Embedded Tests . . . . . . . . . . . . . . . . . . . . . . . . . .114.2.1 DSP DSI Self Test . . . . . . . . . . . . . . . . . . . . . . .114.2.2 FPGA DSI Test . . . . . . . . . . . . . . . . . . . . . . . . .124.2.3 MPC8555 Ethernet Test . . . . . . . . . . . . . . . . . . .124.2.4 DSP Ethernet Test . . . . . . . . . . . . . . . . . . . . . . .13

5 Connect to the Board with CodeWarrior . . . . . . . . . .145.1 CodeWarrior Project Creation for MPC8555 . . . .145.2 CodeWarrior Project Creation for MSC8126 . . . .14

6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Getting Started with the Multi-Standard SPTWIMAXCC1E AMC Channel Card

Document Number: SPTWIMAXCCPGAgile Number: 926-75937

Rev. 1, 02/2007

Getting Started with the Multi-Standard SPTWIMAXCC1E AMC Channel Card, Rev. 1

2 Freescale Semiconductor

Channel Card Layout

1 Channel Card LayoutFigure 1 and Figure 2 detail the board layout, highlighting the major configuration components.

Figure 1. Channel Card Layout, Top View

Figure 2. Channel Card Layout, Bottom View

ALGO FPGAFLASH JTAG[HD4]

PQIIIEthernet

DSPA Ethernet

DSPB Ethernet

AMCConnector[P1]

DDR2 Socket [P9]

DDR1 Socket [P4]

DSP JTAG [P7]

ADC Interface [P8]

PQIII JTAG [HD2]

multi-RS232 Interface [HD3]CPLD/FPGA

JTAG[HD5]

RESET CPLDJTAG [HD1]

ALGO FPGADISPLAY[LD19]

RESET CPLDSWITCH [SW5]

SERDES FPGASWITCH [SW8]

Power Socket [J5]

Power Reset [SW7]Board Reset [SW10]

SERDES [SW9]

ALGO [SW6]

RX ETH Port 4[LD2]TX ETH Port 4[LD4]RESET CPLD [LD5]RESET CPLD [LD6]RESET CPLD [LD7]RESET CPLD [LD8]DSP A [LD9]DSP B [LD10]ALGO FPGA [LD11]ALGO FPGA [LD15]ALGO FPGA [LD17]ALGO_FPGA [LD18]

LEDS

LB/DSI CPLD [LD1]LB/DSI CPLD [LD3]

SERDES FPGA[LD12] LD[13] LD[14] LD[16] ALGO FPGA

FLASH JTAG[HD4]

PQIIIEthernet

DSPA Ethernet

DSPB Ethernet

AMCConnector[P1]

DDR2 Socket [P9]

DDR1 Socket [P4]

DSP JTAG [P7]

ADC Interface [P8]

PQIII JTAG [HD2]

multi-RS232 Interface [HD3]CPLD/FPGA

JTAG[HD5]

RESET CPLDJTAG [HD1]

ALGO FPGADISPLAY[LD19]



Power Socket [J5]

Power Reset [SW7]Board Reset [SW10]

SERDES [SW9]

ALGO [SW6]

RX ETH Port 4[LD2]TX ETH Port 4[LD4]RESET CPLD [LD5]RESET CPLD [LD6]RESET CPLD [LD7]RESET CPLD [LD8]DSP A [LD9]DSP B [LD10]ALGO FPGA [LD11]ALGO FPGA [LD15]ALGO FPGA [LD17]ALGO_FPGA [LD18]

LEDS

LB/DSI CPLD [LD1]LB/DSI CPLD [LD3]

SERDES FPGA[LD12] LD[13] LD[14] LD[16]

DSP Configuration Switch [S1]

LB/DSI CPLDSWITCH[SW3]

PQII Configuration Switch [SW1]

Mictor Connector (Optional) [P2]

SERDES Configuration Switch [SW2]

ALGO Configuration Switch [SW4]














Freescale Semiconductor 3

Install and Configure CodeWarrior Development Studio

2 Install and Configure CodeWarrior Development StudioThe CodeWarrior Development Studio is the integrated development environment (IDE) to create and download applications to the board. If you are using PowerQUICC III tools, perform the following steps to install CodeWarrior Development Studio, PowerPC ISA, Communications Processors Edition:

1. Insert the CD into the CD-ROM drive

The CodeWarrior setup menu appears.

2. Click on LAUNCH THE INSTALLER.

The first page of the setup wizard appears.

3. Follow the wizard’s instructions, accepting default settings.

This guide relies on the user installing to the default location shown in the setup wizard.

4. When the installation finishes, reboot.

To use CodeWarrior Development Studio for PowerPC Comm Edition, a license is needed to unlock all features. To acquire a full 45-day evaluation license, or for any questions, email [email protected] with your request.

If you are using StarCore tools, perform the following steps to install CodeWarrior Development Studio for StarCore:

1. Click on LAUNCH THE INSTALLER.

The first page of the setup wizard appears.

2. Follow the wizard’s instructions, accepting the default installation folder. At the DSP Hardware Debugger Configuration page, select PARALLEL PORT COMMAND CONVERTER. The SmartDSP OS is not necessary for this getting started guide, but may be installed if desired. Reboot when finished.

This guide relies on the user installing to the default location shown in the setup wizard.

The CodeWarrior Development Studio for StarCore installer includes a 15-day license to allow the software to run with no restrictions. To acquire a full 45-day evaluation license, or for any questions, email [email protected] with your request.

2.1 Multiple CodeWarrior InstallationsIf multiple versions of CodeWarrior are installed on a single machine, it is necessary to ensure that certain DLLs are re-registered with Windows before the software is launched. Therefore, before running CodeWarrior, first run the \bin\regservers.bat script for the CodeWarrior version you plan to run.

For the PowerPC tools, this file is located at:

C:\Program Files\Freescale\CodeWarrior PowerPC Comm V8.6\bin\regservers.bat

For the StarCore tools, this file is located at:

C:\Program Files\Metrowerks\CodeWarrior\bin\regservers.bat

To simplify the process, add a line containing IDE.exe at the end of both regservers.bat files, causing the IDE to launch automatically when the shortcuts are run.

mailto:[email protected]

mailto:[email protected]



Connect the Board

2.2 Initial CodeWarrior ConfigurationOn the SPTWIMAXCC1 supplementary CD, there is a file named Channel Card Stationary.zip that contains the project stationery, or template projects, for both the PowerQUICC and StarCore architectures. Unzip this archive to a temporary folder. Then, depending on the software in use, run the batch file for the desired toolset to set up the stationery and copy important configuration files. For PowerPC, run Channelcard_MPC8555.bat. For StarCore, run Channelcard_MSC8126.bat.

NOTEThe scripts rely on the user installing to the default installation folders for both toolsets.

Additionally, if the StarCore tools are used, it is necessary to set up a remote debug connection for the SPTWIMAXCC1 board, as follows:

1. Open CodeWarrior for StarCore.

2. From the Edit menu, choose PREFERENCES.

3. In the new window, select REMOTE CONNECTIONS on the left side.

4. Click the ADD.. button to create a new connection type.

5. Name the connection StarCore CCS – SPTWIMAXCC1.

6. For CONNECTION TYPE, specify CCS Remote Connection.

7. Check the MULTI-CORE DEBUGGING checkbox.

8. For JTAG CONFIGURATION FILE, click CHOOSE and browse to:

C:\Program Files\Metrowerks\CodeWarrior\StarCore_Support\Initialization_Files\JTAGConfigFiles\ MSC8126jtagx2.cfg

9. Click OK to close, then click OK again in the previous window.

2.3 Parallel Port ConfigurationIt is sometimes necessary to reconfigure the parallel port settings in the BIOS of the host computer when the DSPCOMMPARALLEL command converter/wiggler is used. To do so, enter the BIOS menu of the computer by pressing the appropriate key on bootup (usually an F-key or delete). The options for parallel port settings vary from manufacturer to manufacturer. Successful operation can also depend on the manufacturer’s implementation of the modes. Therefore, it is not possible to specify one correct setting. If any error messages appear during an attempt to connect to the board, such as Cannot connect to CCS or Cannot reset target, reboot into the BIOS and try a different mode. Examples of parallel port modes are Standard, AT, Bidirectional, PS/2, ECP, and EEP.

3 Connect the BoardTo set up the channel card, perform the following steps:

1. Connect the power supply unit (PSU) to the PSU adapter card as shown in Figure 3.

2. Connect the adapter cable to the adapter board (J1) and the channel card power connector (J5).

3. Ensure that the adapter card jumper is in position pin 3-4 for CPLD controlled



Connect the Board

The power requirements of the power module are 12 VDC at 5A, If an alternative power module is used, take care to ensure that it meets the following requirements:

• If you are using the PowerQUICC III tools, first ensure that CodeWarrior Development Studio for PowerPC ISA, Communications Processors Edition is installed. Then connect the USB TAP between the host computer and the PowerQUICC III JTAG (HD2) header. Upon first connection, the computer reports the USB TAP as new hardware. Select NO to the request to connect to Windows Update to search for the driver. Then choose INSTALL THE SOFTWARE AUTOMATICALLY. The driver is then installed.

• If you are using the StarCore DSP tools, connect the DSPCOMMPARALLEL command converter (labeled OCDEMON MACRAIGOR SYSTEMS WIGGLER) between the host computer and the DSP JTAG (P7).

• If you are programming the algorithmic FPGA flash memory, connect the programming cable to the header HD4.

• If you are programming the SerDes FPGA or its associated flash memory, connect the programming cable to the header HD5.

Figure 3. Connecting the Channel Card

Multi-UART Cable(Optional Replacement for

a Single UART)Channel

Card

EthernetCable

JTAG Wiggler andParallel Cable for

MSC8126

JTAG USB TAPfor MPC8555

Single UART/RS-232Cable (MPC8555)

PSU AdapterCable

PSU AdapterCard

PSU



Power Up the Board

4 Power Up the BoardBefore powering up the channel card, set the switch settings as shown in Figure 4 and Figure 5. For details, see Table 1 through Table 6. Following are the default settings when the board is powered up:

• MPC8555 boot u-boot from flash memory disabled; operating frequency: 833 MHz core/333 MHz DDR (DDR1-333)

• MSC8126 boot standalone with default reset configuration word; operating frequency: 500 MHz core/166 MHz system bus

• Algorithmic FPGA. Bootstraps from EPROM and then it configures itself and runs a continual self test to prove the FPGA interfaces.

• SerDes FPGA. Bootstraps from EPROM and then configures itself and runs a continual self test to prove the FPGA interface

Switch on the power by connecting the power supply unit (PSU) to the PSU adapter card. With the default switch configuration, the Algorithmic and SerDes LEDs light to indicate a successful configuration and the start of the FPGA built-in self test. Additionally, the MPC8555 boots Linux from the preprogrammed flash image (see Section 4.1.2, “MPC8555 Linux Boot”). You can use the CodeWarrior tools to access the MPC8555 (see section 5.1). Next, you can use the CodeWarrior tools to access the MSC8126 DSPs, which are configured in a single JTAG chain (see section 5.2).

Figure 4. Top Switch Settings

PQIIIEthernet

DSPA Ethernet

DSPB Ethernet



ON

OFF

Switch Positions

ON

OFF

Switch Positions



Power Up the Board

Figure 5. Bottom Switch Settings

Table 1. MPC8555 Configuration

Switch Setting Description

SW1.1SW1.2SW1.3SW1.4

OFFON

OFFON

CCB Clock clock (System PLL) = x8System clock × System PLL

33 MHz × 10 =333 MHzDDR = CCB /2 => 333/2 = 166 MHz

SW1.5SW1.6

ONOFF

e500 Core: CCB Clock Ratio = x2.5333 MHz × 2.5 = 833 MHz

SW1.7SW1.8

OFF

OFF

Local bus output hold configuration

1 added buffer delay

Table 2. MSC8126 Standalone Mode

Feature Settings Description

S1.1 ON MODCK1= 0 For clock mode 0 MODCK2 = 0Core = 500 MHz, Bus = 166 MHz

S1.2 ON

S1.3 ON CNFGS=0

RSTCONF = 1 (Default reset configuration word 0x0 written after 1024 cycles if HRCW from external host is not received)

S1.4 OFF





OFF

ON

Switch Positions






OFF

ON

Switch Positions






OFF

ON

Switch Positions

OFF

ON

Switch Positions




Power Up the Board

S1.5 ON BM0

BM1BM2 (BM[0–2] = 001) Boot from external host

S1.6 ON

S1.7 OFF

S1.8 ON Set to Asynchronous DSI

Table 3. LB-DSI CPLD Switch Configuration


SW3.1 OFF Disable uboot.

SW3.2SW3.3SW3.4

OFFOFFOFF

Reserved for future use.

Table 4. Algorithmic FPGA Configuration



ONOFFONON

At powerup, download and run the image from EPROM using the 20 MHz AS configuration scheme.

Table 5. Reset CPLD Switch Configuration


SW5.1 ON DSPs in debug mode (EE0 = 1)

SW5.2 ON Switch on external PSU

SW5.3 ON Standalone mode

SW5.4 OFF Reserved for future use

Table 6. SERDES FPGA Configuration



ONOFFONOFF

At powerup, download and run image from microcontroller using the PS configuration scheme.

Table 7. Push Button Switches


SW7 Power reset Recycles all power on the board.

SW10 Board resets Resets all active devices (MPC8555, MSC8126, FPGAs, and so on).

Table 2. MSC8126 Standalone Mode (continued)

Feature Settings Description



Power Up the Board

4.1 Board Configuration OptionsThe board configuration options discussed in this section pertain to LEDs, PowerQUICC booting, DSP booting, powerup, and testing.

4.1.1 LED OperationMost LEDs are programmable and their operating mode depends on the user application. However, when the boards are first shipped the LEDS are pre-programmed as shown in Table 8.

SW8 ALGO reset Algorithmic FPGA resource (lights the ALGO LEDs when the test image is loaded).

SW9 SerDes reset SerDes FPGA resource (lights the SerDes LEDs when the test image is loaded).

Table 8. LED Settings at Shipment

Switch Color Description

RX ETH Port4 [LD2] Green Back plane Ethernet Rx

TX ETH Port 4[LD4] Green Back plane Ethernet Tx

RESET CPLD [LD5] Yellow on = IPMC voltage on

RESET CPLD [LD6] Yellow Not used

RESET CPLD [LD7] Yellow Not used

RESET CPLD [LD8] Yellow On = DSPs in debug mode (EE0 = 1)Off = DSPs in normal mode (EE0 = 0)

DSP A [LD9] Blue General-purpose DSP A (GPIO25)

DSP B [LD10] Blue General-purpose DSP B (GPIO25)

ALGO FPGA [LD11] Blue Built-in self test indicator. The LED stays off (production test).

ALGO FPGA [LD15] Red Built-in self test indicator. The LED stays on (production test).

ALGO FPGA [LD17] Green Built-in self test indicator. Flashes to indicate that the HSDI loopback test has passed.

ALGO_FPGA [LD18] Yellow Built-in self test indicator. Flashes to indicate that the DDR2 loopback test has passed.

LB/DSI CPLD [LD1] Green On = PQIII runs uBoot/Linux automatically

Off = PQIII jumps into empty flash memory (tools access to MPC8555)

LB/DSI CPLD [LD3] Yellow DSI activity indicator (HWS strobe)

SERDES FPGA [LD12] Yellow Not used

SERDES FPGA [LD13] Blue Not used

SERDES FPGA [LD14] Yellow Not used

SERDES FPGA [LD16] Blue Built-in self test indicator. Flashes to indicate that the FPGA is configured correctly.

Table 7. Push Button Switches (continued)




Power Up the Board

4.1.2 MPC8555 Linux BootThe SPTWIMAXCC1 kit comes with two serial cables. One is a 2 × 8 header to single DE-9 connector configured for communication with the MPC8555 UART. The other cable is a 2 × 8 header to multiple DE-9 connectors for communication with various device UARTS. For the multi-connection cable, the connector labeled PQIII-0 provides an interface with the Linux terminal. The procedure for booting the MPC8555 processor on Linux is as follows:

1. Connect either the single connector cable or the multiple connector cable between the serial port of the host computer and the RS-232 connector of the board (HD3).

2. Set the HyperTerminal (or equivalent) to 115200,8,n,1.

3. Set switch SW3.1 to ON.

4. Power up the board.

The uboot and Linux boot sequence now appear on the terminal window.

5. Log in with the user name root and password root to gain access to the Linux shell or press space during the uboot 10 second countdown to access the uboot environment.

4.1.3 DSP DSI BootThe DSPs can be bootstrapped over the DSI from the MPC8555 processor using either the Linux environment or tools. Set the switches to boot over DSI as shown in Table 10. Note the similar naming of switches S1 and SW1, taking care not to confuse the two.

Table 9. Tools/Linux MPC8555 Boot CPLD Switch Option


SW3.1 OFF uboot/Linux disabled

SW3.1 ON MPC8555 runs uboot/Linux

Table 10. MSC8126 DSI Mode

Feature Settings Comments

S1.1 ON MODCK1 = 0 for clock mode 0MODCK2=0S1.2 ON

S1.3 OFF DSI boot

S1.4 ON

S1.5 ON BM0BM1

BM2 BM[0–2] = 001 Boot from external hostS1.6 ON

S1.7 OFF

S1.8 ON Set to asynchronous DSI

SW5.1 OFF DSPs in normal mode (EE0 = 0)



Power Up the Board

4.1.4 Powerup OptionsThe two powerup options are as follows:

• Standalone mode. Power up the channel card within a lab or test environment (see Table 11).

• ATCA Chassis mode. The channel card is operational within a base station (see Table 12).

4.2 Embedded TestsThe channel card supports a number of embedded tests to allow self test and interface development. This section describes these tests.

4.2.1 DSP DSI Self TestThe DSI self test is essentially a DSP boot over DSI. The MPC8555 processor downloads a section of code over the DSI to the DSP. The DSP executes this code and flashes an LED several times to indicate a successful download. To test the DSI, perform the following steps:

1. If the DSPCOMMPARALLEL command converter is connected to P7 on the board, first remove it. The command converter prevents the DSP DSI bus from working properly.

2. Configure the MPC8555 processor to boot on Linux as described in Section 4.1.2, “MPC8555 Linux Boot.”

3. Configure the DSPs to boot over DSI as described in Section 4.1.3, “DSP DSI Boot,” paying attention to SW5 and S1 settings.


The uboot and Linux boot sequence now appears on the terminal window.

5. Log into the Linux shell with the user name root and password root to access the Linux shell.

6. To test the DSP A DSI, first change to the DSP utility directory (cd dsputils) and then type ./dsp download 0 flashled.s and press the <return> key.

The DSP flashes its LED to indicate a successful test.

7. To test the DSP B DSI, type ./dsp download 1 flashled.s and press the <return> key.

The DSP flashes its LED to indicate a successful test

Table 11. Standalone


SW5.2 ON Switch on external PSU

SW5.3 ON Stand Alone Mode

Table 12. ATCA Chassis


SW5.2 OFF Switch off external PSU

SW5.3 OFF select ATCA rack mode



Power Up the Board

4.2.2 FPGA DSI TestThe DSI interface to the algorithmic and SerDes FPGA can quickly be verified by performing the following steps. This test assumes that the FPGAs contains the original Freescale programmed FPGA test code:

1. Configure the MPC8555 to boot on Linux as described in Section 4.1.2, “MPC8555 Linux Boot.”

2. Press a key during the 10-second countdown to enter the uboot environment.

3. To verify the algorithmic FPGA DSI, enter md 0xc6000000. The following data should be displayed:

=> md 0xc6000000c6000000: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000010: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000020: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000030: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000040: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000050: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000060: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc6000070: .............

4. To verify the SerDes FPGA DSI, enter md 0xc8000000

The following data should be displayed:

=> md 0xc8000000c8000000: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000010: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000020: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000030: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000040: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000050: aaaaaaaa 00555555 aaaaaaaa 00555555 .....UUU.....UUUc8000060:...........

4.2.3 MPC8555 Ethernet TestThe MPC8555 Ethernet can be tested through a simple PING test, as follows:

1. Configure the MPC8555 to boot on Linux as described in Section 4.1.2, “MPC8555 Linux Boot.”

2. Connect an Ethernet cable from the MPC8555 RJ45 as shown in Figure 3 to a network interface of a computer.


The uboot and Linux boot sequence appears on the terminal window.

4. Log into the Linux shell with user name root and password root to gain access to the Linux shell.

5. Set the IP configuration to link with that of the host computer.

For example, if the host computer IP is 192.168.0.49, set the IP address of the MPC8555 processor to 192.168.0.50 using the following command: ifconfig eth0 192.168.0.50.

6. The MPC8555 processor links with the host as follows:

-sh-2.05b# ifconfig eth0 192.168.0.50-sh-2.05b# Trying 1000/FULLTrying 100/FULL



Power Up the Board

Trying 100/HALFPHY: 0:10 - Link is Up - 100/Half

7. From the Linux terminal window, ping the host: ping 192.168.0.49.

The MPC8555 processor responds with the following display, indicating a successful test:

64 bytes from 192.168.0.49: icmp_seq=0 ttl=128 time=0.848 ms64 bytes from 192.168.0.49: icmp_seq=1 ttl=128 time=0.336 ms64 bytes from 192.168.0.49: icmp_seq=2 ttl=128 time=0.251 ms--- 192.168.0.49 ping statistics ---

3 packets transmitted, 3 packets received, 0% packet lossround-trip min/avg/max/stddev = 0.251/0.478/0.848/0.264 ms-sh-2.05b#

8. Press Control-c to terminate the ping command.

4.2.4 DSP Ethernet Test

The DSP A Ethernet can be tested through a simple ping test, as follows:

1. Set the MPC8555 to boot through Linux, as described in Section 4.1.2, “MPC8555 Linux Boot.”

2. Set switches S1 and SW5 to boot the DSPs over the DSI, as shown in Table 10.

3. Connect an Ethernet cable from the PQIII RJ45 to the DSP A RJ45.


The uBoot and Linux boot sequence now appears on the terminal window.

5. Log into the Linux shell with user name root and password root to gain access to the Linux shell.

6. Set the IP configuration of the MPC8555 to 192.168.0.50 using the following command

ifconfig eth0 192.168.0.50

7. The MPC8555 links with the DSP as shown here:

-sh-2.05b# PHY: e00224520:10 - Link is Up - 100/Half

8. From the Linux terminal window, download the DSP Ethernet test

a. cd dsputils b. ./dsp download 0 ethadd_1.s

9. From the Linux terminal window, ping the MSC8126 DSP using the following command:

ping 192.168.0.10

The MPC8555 responds as follows to indicate a successful test:

64 bytes from 192.168.0.10: icmp_seq=0 ttl=128 time=0.848 ms64 bytes from 192.168.0.10: icmp_seq=1 ttl=128 time=0.336 ms64 bytes from 192.168.0.10: icmp_seq=2 ttl=128 time=0.251 ms

. . .

10. To terminate the test, press Control-c.

11. To test DSP B, disconnect the Ethernet cable from the DSP A RJ45 and connect to DSP B RJ45. The Linux terminal window responds with the following display:

sh-2.05b# PHY: e00224520:10 - Link is Downsh-2.05b# PHY: e00224520:10 - Link is Up - 100/Half

12. From the Linux terminal window, download the DSP Ethernet test:

a. ./dsp download 1 ethadd_2.s



Connect to the Board with CodeWarrior

13. From the Linux terminal window ping DSP B using the command ping 192.168.0.20.

The MPC8555 responds as follows to indicate a successful test:

64 bytes from 192.168.0.20: icmp_seq=0 ttl=128 time=0.848 ms64 bytes from 192.168.0.20: icmp_seq=1 ttl=128 time=0.336 ms64 bytes from 192.168.0.20: icmp_seq=2 ttl=128 time=0.251 ms

14. To terminate the test, press Control-c.

The DSP download program ethadd_1.s sets up either DSP with Ethernet address 192.168.0.10 while ethadd_2.s sets up either DSP with 192.168.0.20.

5 Connect to the Board with CodeWarriorCodeWarrior Development Studio can be used to download code to either the MPC8555 or the two MSC8126 DSPs. After performing the installation instructions in Section 2, “Install and Configure CodeWarrior Development Studio,” create and download a project for the desired target, as described here.

5.1 CodeWarrior Project Creation for MPC8555To create the CodeWarrior project, first ensure that the instructions in Section 2.2, “Initial CodeWarrior Configuration,” are completed. Then perform the following steps:

1. Open CodeWarrior Development Studio for PowerPC.

2. Configure the board according to the tables in Section 4, “Power Up the Board.”

3. Connect the USB TAP between the host computer USB port and HD2.

4. Power on the board, ensuring that J3 on the ATX Adapter board is set to 3-4.

5. From the File menu, click NEW.

6. Highlight SPTWIMAXCC1 STATIONERY.

7. Enter a project name and click OK.

8. In the next window, highlight MPC8555 and click OK.

The project is created. To download the code, press the DEBUG button in the project toolbar or select DEBUG from the Project menu. At this point, standard debug operations can be performed.

5.2 CodeWarrior Project Creation for MSC8126To create the CodeWarrior project, first ensure that the instructions in Section 2.2, “Initial CodeWarrior Configuration,” are completed. Then perform the following steps:

1. Open CodeWarrior Development Studio for StarCore.

2. Configure the board according to the tables in Section 4, “Power Up the Board.” Most importantly, ensure that SW5.1 is ON to put the DSPs into debug mode. Also, ensure that S1.3 is ON and S1.4 is OFF to put the DSPs into Standalone mode.

3. Connect the DSPCOMMPARALLEL (OCDemon Macraigor Systems Wiggler) between the host computer parallel port and P7 on the board.

4. Power on the board, ensuring that J3 on the ATX Adapter board is set to 3-4.

5. From the File menu, click NEW.



Revision History

6. Highlight SPTWIMAXCC1 STATIONERY.

7. Enter a project name and click OK.

8. In the next window, expand MSC8126CC”, HIGHLIGHT “C”, and click OK.

The project is created. To download the code, the proper remote connection must be selected:, as follows:

1. From the Edit menu, click CORE0 SETTINGS, or press Alt-F7.

2. In the new window, select the REMOTE DEBUGGING settings panel.

3. For CONNECTION, choose STARCORE CCS – SPTWIMAXCC1.

4. Choose the core to download to in the CORE INDEX field.

5. Click OK.

To download, press the DEBUG button in the project toolbar or select DEBUG from the Project menu. At this point, standard debug operations can be performed. The core of either DSP can be selected for downloading and debugging by referring to the last column of the listing of the JTAG configuration file:

C:\Program Files\Metrowerks\CodeWarrior\ StarCore_Support\Initialization_Files\JTAGConfigFiles\MSC8126jtagx2.cfg

MSC8102SyncMSC8102 # DSPB Core 0 1MSC8102 # DSPB Core 1 2MSC8102 # DSPB Core 2 3MSC8102 # DSPB Core 3 4MSC8102SyncMSC8102 # DSPA Core 0 6MSC8102 # DSPA Core 1 7MSC8102 # DSPA Core 2 8MSC8102 # DSPA Core 3 9

6 Revision History Table 13 provides a revision history for this document.

Table 13. Document Revision History

Rev.Number

Date Substantive Change(s)

0 02/09/2007 Initial release.

1 02/15/2007 Section 4, Changed first bullet to mention u-boot.

Section 4.1.3 Modified the section to emphasize that S1 and SW1 look very similar, and the reader should take care not to confuse them.

Section 2.3, “Parallel Port Configuration.” Added this new section.Section 4.2.4. Added a bullet between steps 1 and 2.

Document Number: SPTWIMAXCCPGRev. 102/2007

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