High-ImpedanceDifferential Relaying

GER-3184

TABLE OF CONTENTS

I Current Differential Protection with Overcurrent Relays ...............................

II CT Performance fbr an External Fault that Saturates the fault CT .......................

III Use of a High Impedance Relay in the Differential Scheme .............................

IV CT Performance for an Internal Fault with a High Impedance Burden .....................

V Overvoltage Protection in the High Impedance Relay ..................................

VI CT Application Considerations in Relation to High ImpedanceDifferential Relaying ..........................................................

VII Typical Applications ..........................................................

CURRENT DIFFERENTIAL PROTECTIONWITH OVERCURRENT RELAYS

The current-differential scheme of protection inwhich the differential relay current is proportionalto the vector difference between the currents en-tering and leaving the protected circuit is widelyapplied in various forms for the protection of dis-crete power system components. Each protectedcomponent (i.e. - generator, transformer, etc.)presents unique problems to the successful imple-mentation of the basic current-differential scheme,and unique solutions embodied in the design of theassociated relay are required. Usually there are alsorelated restrictions on the CT’s used in the scheme.

On a first look basis the protection of stationbuses would apear to ‘lend itself to the applica-tion of a current-differential scheme. Figure 1 is adifferential circuit for bus protection. It is assumedthat the differential relay employed is a low imped-ance unrestrained instantaneous overcurrent relay.If all the CT’s maintain the same nominal ratio forall external faults the assumed scheme is perfectlyvalid since no current can flow in the relay coil.However, when the instantaneous overcurrent relayis set low enough to give useful sensitivity to in-ternal faults the relay may in practice operatefalsely on external faults due to a reduction of thenominal ratio of the fault CT resulting from faultCT core saturation. This reduction of the faultCT nominal ratio results in a “false” differentialrelay current that may operate the instantaneousovercurrent relay.

The mechanism by which the fault CT core be-comes saturated for an external fault is attributa-ble to two factors: (1) the dc component of an off-set primary fault current and (2) residual magnetismin the core. The most onerous case occurs whenthe core fluxes produced by these two phenomenaare additive. An improvement of this instantaneousovercurrent scheme would be to utilize an inverse-time, induction-type overcurrent relay. The induc-tion principle makes this relay less responsive tothe dc and harmonic components of the “false”differential current resulting from CT errors due tosaturation. As well, the time delay can be set to

over-ride the dc transient allowing the “false”differential current to subside below the relay’spickup before operation is permitted. This approachusually results in objectionably long clearing times,and from an application viewpoint the complexityof calculations required to obtain an optimum timedelay is a predominant reason why this scheme isnot widely used for important buses.

An obvious solution to the problem of thesaturating fault CT is to design CT’s that cannotsaturate even for the worst external fault that canbe expected. This may be done in a number ofways. One method is to increase the core areaand/or reduce the length of the flux path (decreasethe mean diameter of a bushing CT). This is usuallynot practical from the standpoint of cost and spacerequirements.

The elegant resolution of this problem would beto utilize the fact that the fault CT may saturate asa basis for the solution. This is exactly what hasbeen accomplished. To gain an insight into thereasoning behind the solution it is necessary toexamine in more detail the cause and effect offault-CT saturation for an external fault.

DIFFERENTIALRELAY

FEEDERS \A

Figure 1

3

CT PERFORMANCE FOR AN EXTERNALFAULT THAT SATURATES THE FAULT CT

To prevent duplication of effort in analyzing CTresponse the burden of the differential relay, ZB,is assumed purely resistive throughout the follow-ing considerations. When the differential relay is anovercurrent type ZB will be closer to pure induct-ance. However, for a qualitative description of CTresponse the imposition of a resistive burden is notimpractical. Actually, foreknowledge that the relayutilized in the solution to this problem has a resist-ive burden dictates this choice. The magnetizationcharacteristic of the transformer core will be con-sidered to be as shown in Fig. 2. This characteristicassumes zero exciting current and is consequentlyunrealistic, but a qualitative picture of the CT satu-ration effect may be obtained. It is further assumedthat the CT is wound on a toroidal core resultingin negligible leakage reactance, and the equivalentcircuit of Fig. 3 is applicable. In Fig. 3:

X m =

R2 =

ZB =

Rp’ =

magnetizing inductance (infinite)

secondary winding resistance

resistive burden that includes the CT leadresistance

12

r\lRp = core loss-resistance (referred

to primary)

The secondary leakage reactance is negligible sincea fully distributed winding is assumed, and thecore-loss is assumed to be zero.

B

t

‘I*H

Figure 2

Figure 3

The foregoing assumptions imply that the sec-ondary current of the CT is an exact image of theprimary current while the core is unsaturated andthat no e.m.f. can be produced while the core isin the saturated state. During unsaturated periodsthe secondary voltage would be:

e2 = -il (R2 + ZB)/N (1)

With i 1 = 11 sin wt the secondary voltage becomes

During

e2= - I1 RS/N sin ot (2)

where RS = R2 + ZB

the saturated periods e2 would be zero.

The core flux variation is given by

Cp = -1 e2 dtN

(3)

@= -II RS cos ot (4)wN2

Equation 4 assumes no saturation. Figure 4 showsthe steady state current and flux variations. It ispossible although highly unlikely that saturationwill occur for a steady state sinusoidal primarycurrent. Should saturation be reached it must occurbefore the peak value of the flux wave of Fig. 4B.If at wt = wtl the saturation point is reached thenfor ot > otl no further e.m.f. will be producedand the secondary current will collapse instantly tozero. The core remains saturated until the excitingcurrent falls to its saturation value which in thisinstance is zero. The core cannot unsaturate beforethe primary current zero.

il t) wt

) wt

(A)

t@

@ . wt @SAT

i2.9 t

Figure 4

For this steady state saturation case themay be expressed as

lr@ = @SAT

at1

@ tit= @SAT-l, __% COSwt wt7f wN2 71

@ ot= @SAT+Il_RS (1 +cos ot)lr oN2

flux

RS@SAT= 11 - (cos tit1 - 1)

2wN2

(5)

A given CT will have a fixed value of @SAT and tojust avoid core saturation wtl must have a value of7r which results in a primary current given below.

II = wlv2 @SAT

(6) Rs

The above equation may be rewritten as

(7) RS@SAT = 11 -wN2

where in the above equations 7r < wt < (r + otl).Figure 5 shows the waveforms for this case. An ex-

Figure 5

pression for @SAT may be obtained by noting thatatwt=rr+otl,@==@SAT.

RSIOSAT = @SAT + 11 -wN2

1 + cos (n + wtl) (8)

(9)

with the realization that II is the dependentvariable.

5

ii t * wt

Figure 6

Assuming that

RS@‘SAT = 11 -

2wN2

means that wtl = 7~/2, and Fig. 6 shows the cur-rent and flux variations for this case. The second-ary current and voltage is cutoff past the saturationtime wtl for each half cycle. The preceding hasbeen a qualitative analysis concerned with steadystate sinusoidal primary currents, but as mentionedpreviously the primary cause of fault CT saturationis dc offset in the primary current.

Figure 7a shows a fully offset primary currentwave. It is assumed that

RS@SAT = 11 -UN2

so that in the steady state (no offset) full repro-duction of the primary current will take place. Theprimary current is given as

_ R’ tiI = II cos(wt+a-8) -E ;I;- cos (a -e)(lo)

where: a =

8 =

R’=

L’=

Q: after voltage peak at which faultoccurs

primary circuit phase angle

total resistance in power system

total inductance in power system

For the waveform of Fig. 7a it was assumed thatwL’/R’ = 8 and (a - 0) = 0. This results in

_ ot

il = II (cos wt - E (11)

The flux is then:

o = -1 RS

r\re2 dt = - _ il dt (12)

N2

wt- -cp=_l~ RS sin wt + 8 (E 8 - 1 ) (13)

,N2

ot

o = -@‘SAT sin wt +8 (E B - 1) (14)

Equation (14) is valid until the saturation point isreached. Once saturation is reached it is maintaineduntil the next primary current zero at which timedesaturation would begin. Upon desaturation theflux would change from the constant saturationvalue at the same rate it would have changed hadsaturation not occurred. This flux variation isshown in Fig. 7b. The resulting secondary currentis depicted in Fig. 7c.

It is now possible to qualitatively explain theappearance of a “false” differential current forthe case of a saturated fault CT during an externalfault. A fault at A is assumed as shown in Fig. 1.Figure 8 is a simplified diagram of the actual condi-tions where the CT lead resistances are neglected.

i2

wt

Figure 7

The sum of the two source CT secondary currents,iT, is assumed to be the fully-offset waveform ofFig. 7a referred to the secondary. This means thesource CT’s do not saturate. It is further assumedthat the fault CT saturates and its secondary cur-rent is as shown in Fig. 7c. During the periods thatthe fault CT is saturated the secondary source CTcurrent, it, will flow through the differential relaycoil provided its impedance is low compared withthe fault CT resistance. During the period that thefault CT is not saturated id = 0 since the fault CTis producing the required current. The consequenceis that a current waveform shown in Fig. 9b flows

through the low impedance relay. This “false”differential current decreases in magnitude andpulse width as the primary current waveform ap-proaches a sinusoidal steady state value sinceconcurrently the fault CT saturates for less of eachsucceeding negative primary current half cycle.For the example assumed the “false” differentialcurrent decays to zero in approximately fivecycles.

Had there been residual flux in the fault CT coreprior to the occurrence of the external fault the“false” differential current in the low impedance

7

DIFFERENTIAL RELAY

X

t ii

:+

- -_)

,tiT

4. if<*<

‘d

Figure 8

relay coil could have increased. Assume that aresidual flux equal to the previously stated satura-tion level, @SAT, was present and that its directionis such that it adds to the flux produced by thefirst half cycle of the fully offset primary current.

i2

The result is shown in Fig. 10. In this case theentire fully offset half cycle is reproduced as“false” differential current.

It is this “false” differential current flowing inthe low impedance coil of an instantaneous over-current relay that can cause false operation for anexternal fault. Figure 11 is an actual oscillogramfor a fully offset external fault current with severalsource CT’s feeding the fault and with a low im-pedance overcurrent relay as the differential relay.Trace A shows the fully offset primary current inthe fault CT and trace B is the total current fromall source CT’s fed into the differential junction,also fully offset. Trace C shows the secondary cur-rent in the fault CT which can be assumed to betransformed current since the differential relayimpedance is very low compared with the faultCT resistance. The differential current is repre-sented by trace D and shows that the initial cycleis nearly a fully offset wave. Trace C is a good illus-tration of the current in the secondary of a satu-rated CT as shown in Figs. 7c and lob.

id

t

8

7r 2n 3n 4n 5rr 6n 7n 871

- 9a -

A__- wt

- 9b -

Figure 9

USE OF A HIGH IMPEDANCE RELAY INTHE DIFFERENTIAL SCHEME

i IF+ uzz u

G!E p

k2 a

0 0FLUX AND

CURRENT VARIATIONS IN FAULT CURRENT

TRANSFORMER

Figure 10

If the relay coil is a high impedance in relationto the fault CT secondary winding resistance the“false” d i f ferent ia l current would then f lowthrough the secondary of the fault CT. A corres-ponding “error” voltage, VE, would appear acrossthe saturated CT secondary and across the highimpedance relay coil connected to this CT. Thisvoltage magnitude across the high impedance relaywould be

VE = id Rc (15)

where Rc = secondary winding resistance of faultCT plus CT lead resistance from faultCT to relay

id = “false” differential current

VE would have a waveshape like that shown in Fig.11d.

The high impedance relay would have to be setsuch that it would not operate for the maximum

A. PRIMARY CURRENT. B. SECONDARY CURRENT FROMSOURCE CT’S. C. SECONDARY CURRENT FAULT CT. D.

DIFFERENTIAL CURRENT

Figure 11

“error” voltage expected. The maximum errorwould occur when the fault CT reached full satura-tion and the source CT’s did not saturate at all.For a worst case analysis it is assumed that thefully offset primary current has no exponentialdecay component and that the fault CT remainscompletely saturated. The “false” differentialcurrent through the secondary winding of thefault CT under these unrealistic conditions wouldbe as shown in Fig. 12. The peak voltage betweenthe junction points is:

VE (pk) = 2 lD Rc (16)

VE (pk) = 2 ‘FRc (17)N

where IF = peak value of maximum externalfault current

id1Figure 12

9

f

(1)

1 L

-C

T

RELAYCOIL‘i(2)

Figure 13

In the actual design of the high impedance relay,type PVD, a resonant circuit tuned to 60 hertz isplaced in series with the operating coil. This isshown in Fig. 13.

The operating unit is isolated within a full waverectifier so that changes in its inductive reactance

due to adjustment changes will not disturb thetuning of the resonant circuit. This circuit designmeans the unit tends to respond more to theRMS 60 Hz component of whatever waveshape isapplied than to the peak value. Consequently forthe waveform of Fig. I2 the relay would be set foran RMS value given by equation (18)

vE= -IF RC= ~F(RMS)RC(18)

d/2NN

Actually a safety factor of 2 is incorporated intothe setting.

PICKUP SETTING = 2 IF(RMS) RC(19)

N

With a voltage setting on the high impedance dif-ferential relay as determined by equation (19) thescheme is now secure against operation on externalfaults. If for all internal faults the voltage acrossthe relay circuit exceeds the setting as determinedby equation (19) then this approach will be applic-able. It is necessary to investigate CT performancewith a high impedance burden to ascertain whatthe voltage across the relay will be for an internalfault.

CT PERFORMANCE FOR AN INTERNALFAULT WITH A HIGH IMPEDANCE BURDEN

The ultimate high impedance burden is the opensecondary condition. It is common knowledge thatcurrent transformers are not to be operated withtheir secondary windings open-circuited because ofthe high-peak voltages that result. When the sec-ondary is open-circuited the primary side ampere-turns provide excitation only, and at all reasonablecurrent levels the core is in saturation except forshort periods near the current zeroes. Since themagnetization characteristic of the assumed corematerial dictates that the magnetizing inductanceis infinite the core-loss resistance referred to thesecondary, Rp, must now be assumed to be somevalue less than infinity to provide for a realisticequivalent circuit for open secondary conditions.Figure 14 shows this equivalent circuit referred tothe primary.

For unsaturated conditions the secondary volt-age will be:

e2 = - NeI = - (Iv) iE 1 2

NRp (20)

e2 = - i!-Rp I 1 sin wt (21)N

The core flux variation will be:

o=_ 1 1

r\le2dt =

ZRp 11 sin ot(22)

If at wt = 0, @ = - (PSAT then for wt > 0 equation(23) is valid up to the point where @ = + @SAT.

@=-@SAT+ I-Rp I1(I - cos wt) (23)wN2

IO

il+

iE

- 1

cJ* Rpt

e,=. “2

N N

Rp < m

Figure 14

The flux and secondary voltage variation withprimary current is as shown in Fig. 15. These wave-forms are similar to those in Fig. 6 except that thecore saturates sooner and consequently the second-ary voltage approaches a pulse. The peak magni-tude of the secondary voltage is much higher forthe open circuited condition because Rp % RS.

If at wt = wt2, C$ = + @SAT, then

LRp II (I - cos wt2) = 2 @SAT.wN2

C O S Cdt2 =d 1 _ sin2 at-2 = 1 -2@SAT wN2

sin2 ot2 = 1-

sin wt2 = I=

sin wt2 =

II Rp

l _ 2@SAT oN2

11 Rp

l _ 2*SAT wN2 2

11 Rp

I_~ + @‘SAT wN2

11 Rp

2@SAT tiN2 2

II Rp

sin wt2 2 2 @SAT aN2

11 Rp

l/2

l/2

2

l/2

(24)

+*SAT -> *

6T

) t

-@SAT -& 4 -

e2I

t

E2 (pk)

Figure 15

From equation (21) the peak secondary voltage is

E2(pk)=-lRpl, 2 *SAT wN2 l/2

N 11 Rp

E2 (pk) = 2 wRp 11 @SAT l/2 (25)

In actuality the current transformer is not opencircuited but rather shunted by the high impedanceof the differential relay. If Rp % ZB then Rp inequation (25) may be replaced with ZB.

E2 (pk) = 2 OZB 11 @‘SAT l/2 (26)

11

An example follows to show the relative magni-tude of peak voltage across the high impedancedifferential relay coil for internal versus externalfaults. The following values are assumed:

Rc = 1.7 Q

l’F = 14,500 a (RMS)

N = 240 (1200/5 CT)

ZB = 2600 fi

For an external fault the error voltage is given byequation (18).

vE= lr\l

l’F Rc = 102 VRMS

For an internal fault of the same magnitude thevoltage across the high impedance relay is given byequation (26).

The flux saturation level,as in equation (27) whereent variable.

+SAT=Qll

where 0 < q < 1

The peak voltage

E2 (pk) = 2

IOSAT, may be expressed11 is actually the depend-

ZB (27)WN2

may now be expressed as

l/2WZB ll. _.ZBII rl =

mN2

2dYj-. zsN

Since it is known that the core saturates quickly avalue of v = 10-4 might be assumed.

E2 (pk) = 2fizBfi l’FN

E2 (pk) = 4440 v

Although there is a wide divergence between maxi-mum “error” voltage during an external fault andpeak voltage during an internal fault for faults of

the same current magnitude, the actual margin ofoperation for the relay is less since the relay doesnot respond to peak voltage values. When deter-mining the sensitivity of a high impedance differ-ential relay for a given situation the minimum in-ternal fault current required to operate the relayat its pickup setting (determined from equation(19)) is calculated. With a fault on the bus of Fig.1 the equivalent circuit will be that of Fig. 16 inwhich the secondary winding resistances have beenneglected. The minimum primary internal faultcurrent necessary to operate the relay is given byequation (28).

XiF (MIN) = N iMlN = N iEn + iR (28)

n=1

where: iR = PICKUP SETTING/ZB

X = number of CT’s connected to relay

The excitation current, iE, of each CT is deter-mined from its associated secondary excitationcurve by finding the exciting current correspondingto the voltage pickup setting of the relay. Theidealized B-H characteristic of Fig. 2 is now re-placed with a more realistic characteristic to pro-duce secondary characteristics as shown in Fig. 17.If the calculated current from equation (28) is lessthan the minimum internal fault current expectedthe application is sound.

To insure a substantial margin of operation thehigh impedance relay pickup setting should not begreater than the knee voltage, ES, of the poorestCT connected to the relay. A significant increasein voltage across the high impedance relay overthe pickup value should be realized for internalfault currents that exceed 2 to 3 times that cal-culated from equation (28). With the pickup volt-age at or above the knee point of the worst excita-tion characteristic an increase in internal faultcurrent above the minimum value may not producean appreciable increase in secondary RMS voltage.This may be verified by referring to Fig. 17.

Figure 16

12

CT SECONDARY EXCITATION CHARACTERISTICS

vst

--_-___ xb

Es

‘e

a

‘e, ‘E* ‘e

‘e2

b

Figure 17

In Fig. 17a point a is located by plotting thepickup voltage, and lel is the corresponding excita-

tion current. It is assumed that some multiple ofminimum internal fault current will cause theexcitation current to increase to le2 which estab-lishes point b. Figure 17b is similarly constructedexcept that point a is located below the knee ofthe curve. There is a greater increment in RMSsecondary voltage in 17b than in 17a. For the sameincrease in internal fault current above the mini-mum value the pickup setting as shown in Fig. 17bwill provide a greater margin of operation (incre-ment in secondary voltage) than that shown inFig. 17a.

Should equation (19) yield a pickup setting ator above the knee point voltage it would be desir-able to decrease the setting to a value below theknee point. Usually it is possible to reduce thepickup setting determined by equation (19) bysome amount and still maintain security on ex-ternal faults. This is so because fault CT saturationdoes not exist throughout the entire current cycle,and the source CT’s usually saturate quickly reduc-ing the time that the relay must withstand the“error” voltage. The amount by which the settingdetermined from equation (19) may be reducedhas been empirically determined for bushing CT’sutilized in GE switchgear and is published in theinstruction book for the PVD relay. If this allow-able reduction results in a pickup setting belowthe knee point then scheme reliability is enhanced.

For the conditions depicted in Fig. 17b the min-imum internal fault current does not saturate thecore of the worst CT, but any significant increaseover minimum will saturate the core. For mostinternal faults high peak voltages will appearacross terminal points 1-2 of Fig. 13.

OVERVOLTAGE PROTECTION IN THEHIGH IMPEDANCE RELAY

To protect the various relay components and theassociated insulation from these potentially exces-sive voltages a Thyrite resistor is placed across therelay. The Thyrite is a non-linear resistor with anI-V characteristic as shown in Fig. 18.

The addition of the Thyrite resistor will desensi-tize the relay since it limits the peak voltage whichin turn decreases the RMS value. This desensitizingeffect may be taken into account by modifyingequation (28).

XiF(MIN) = N iEn + iR + iThyrite (29)

n=1

Equation (29) indicates that the minimum internalfault current necessary to operate the relay at itspickup setting has increased. The Thyrite current,iThyrite is determined from a published I-V charac-teristic similar to that of Fig. 18 evaluated at thepickup setting of the relay. In general this currentis quite small at the relay pickup voltage setting.

13

THYRITE I-V CHARACTERISTICS

IA V=AIX

O<x<I

In the application of the PVD high impedancerelay the contact of an auxiliary lockout relayshort circuits the Thyrite following relay operationto protect it from overheating. The Thyrite isshort-time rated in regards to heat dissipation, andthe shorting action of the lockout relay reduces theduty time of the Thyrite by an amount equal tothe difference between breaker operating time andauxiliary lockout operating time.

Figure 18

CT APPLICATION CONSIDERATIONS INRELATION TO HIGH-IMPEDANCE

DIFFERENTIAL RELAYING

Throughout all of the preceding considerationsthe use of CT’s with fully distributed windings on atoroidal core has been assumed. The result hasbeen that secondary leakage reactance was dis-regarded, and this fact is reflected in Figure 3 andequation (19). It is possible to apply the PVDrelay with CT’s that have significant secondaryleakage reactance, but accurate data must beavailable concerning this secondary leakage react-ance. Because there usually exists significant uncer-tainty regarding the true value of the secondaryleakage reactance the pickup setting of the PVDas determined from a modified equation (19)(RC replaced by RC + secondary leakage react-ance) will be uncertain. For this reason CT’s withsignificant secondary leakage reactance, such aswindow-type CT’s, are not generally recommendedfor application with the PVD relay. The recom-mended CT type is that which has its secondarywound on a toroidal core with the windings com-pletely distributed around the core (bushing type).Figure 19 illustrates the difference between a com-pletely distributed and a non-distributed secondarywinding.

14

In applications involving two different CT ratiosthe turns ratio of each CT connected to the PVDrelay must be identical requiring the higher ratioCT’s to be used on a lower tap. An initial restric-tion on this mixed ratio CT application is thatthe lower tap on the higher ratio CT must be fullydistributed. This is a necessary but not sufficientcondition to insure a satisfactory scheme utilizingmixed ratio CT’s.

Assuming that the requirement for a fully distri-buted tap is met the other consideration is theauto-transformer effect in the higher ratio CT’sduring an internal fault. A 1200/5 CT used on itsfully distributed 600/5 tap will have a high second-ary voltage appear across its full winding during aninternal fault. The Thyrite units in the PVD willlimit the voltage across the 600/5 portion of thewinding but this voltage is amplified by a factorof 2 when it appears across the 1200/5 winding.This higher voltage may exceed the capability ofthe insulation in the circuit connected across thefull winding. The basic problem is to limit this

voltage to safe values without doing thermal dam-age to the Thyrite units. The difficulty is ascertain-ing these two conditions is the primary reason whyuse of the PVD with different ratio CT’s is not rec-ommended. However, in those situations whereuse of different ratio CT’s cannot be avoided thereare certain connections that may be applicable.

each different CT core saturation level. However,a representative flux density at saturation, Bm,may be assumed.

An obvious approach might be to simply con-nect the PVD across the full winding of the lowerratio CT’s and the matching fully distributed tapsof the higher ratio CT’s. The peak voltage appear-ing across the full winding of the higher ratio CTwould then have to be calculated, and if it is deter-mined that this value is within the insulation capa-bility of the terminal blocks, leads, cables, etc.connected across the full winding of the higherratio CT then this connection is applicable pro-vided the ratings of the Thyrite unit are notexceeded.

It is now possible to obtain the peak voltageacross the PVD by simply knowing the maximuminternal fault current and the es value of thepoorest CT connected to it. This is accomplishedby determining the maximum value of ep fromeither Figure 20 or 21 and multiplying this valueby the number of disks in the stack. This voltageis then multiplied by the ratio of total turns toused turns to obtain the peak voltage developedacross the full winding of the higher ratio CT. Itthen must be determined whether the CT and itsassociated leads and terminal blocks are capableof withstanding this magnitude of peak voltage.

Plots of watt-seconds/half-cycle versus Es/Thyrite disk with internal fault current as theparametric quantity may be plotted as shown in

An approach to determining the safe operatinglimit of the Thyrite unit is outlined below. TheThyrite unit in the PVD relay is a stack comprisedof a number of disks placed in series. Each disk canwithstand a given crest voltage depending upon thenumber of disks in the stack. A higher crest voltagecan produce a punch-through effect which willdestroy the disk. Each Thyrite disk is capable ofdissipating 1800 watt-seconds of energy. Assuminga PVD operating time of 3 cycles and a lock outrelay time of 1 cycle, the Thyrite stack will be sub-jected to the total secondary fault current for 4cycles or 8 half cycles. Thus the maximum dissipa-tion per Thyrite disk should not exceed 225 watt-seconds per half cycle.

SEC

The magnitude of the peak voltage that can bedeveloped depends on the magnitude of the in-ternal fault, and on the excitation characteristic ofthe associated CT as well as the I-V characteristicof the Thyrite. Consequently, it is possible to plota family of curves of secondary peak voltage, ep,versus Es/per Thyrite disk with internal fault cur-rent magnitude as the parameter. Peak voltage istaken as the drop necessary to force through theThyrite the total current that flows at the peak ofthe sinusoidal fault current (90o) or at the pointwhere the core saturates if this occurs before thefault current peak. The same type of plot is con-structed for a fully-offset internal fault current.Figures 20 and 21 are representative curves forsinusoidal and fully-offset internal fault currentsrespectively. This data is computed analytically

SECD

and a different set of curves will be obtained for

COMPLETELY

DISTRIBUTED

PRIMARY

PRIMARY

Figure 19

15

BASED ON :SYMMETRICAL SINUSOIDALINTERNAL FAULT CURRENT

070 5 0 100 150 200 250

E, PER THYRITE DISK

Figure 20

BASED ON:COMPLETELY OFFSET SINUSOIDAL

INTERNAL FAULT CURRENT

P I0’ ,

0 50 100 150 200 250

E, PER THYRITE DISK

Figure 21

Figure 22. This information is obtained by meansof a numerical iterative technique that calculatesenergy dissipated in each Thyrite disk per halfcycle up to the point where the CT saturates andis based on symmetrical sine wave current. A sim-ilar curve may be plotted for a fully offset currentwave, but it has been found that this case is lesslimiting than the symmetrical current wave.

As stated previously the watt-second rating of aThyrite disk used in the PVD is 225 watt-seconds/half cycle. The safe peak voltage across the stack is2120 volts; 530 volts/disk for a 4 disk stack, 700volts/disk for a 3 disk stack and 1060 volts/diskfor a 2 disk stack. Assuming a 4 disk stack Figures20, 21 and 22 may be combined into Figure 23.The curves of Figure 23 provides the relation be-tween RMS symmetrical amperes and Es of the

16

BASED ON:SYMMETRICAL SINUSOIDALINTERNAL FAULT CURRENT

400w 200A

50A

0 50 100 150 200 250 300

E, PER THYRITE DISK

Figure 22

poorest CT that will not result in either the crestvoltage rating, 530 volts/disk, or heating limit ofthe Thyrite unit from being exceeded. As can beseen the crest voltage is actually the limiting factor.Figure 24 would be used to determine if the Thy-rite unit is within its rating and this informationcoupled with the previously determined peak volt-age across the full winding of the higher ratio CTwill determine if the previously mentioned connec-tion for a mixed ratio CT application is feasible.

The curves in Figures 20 through 23 are notaccurately plotted and should not be used to deter-mine actual values. Accurate plots are availableupon request.

SAFE OPERATING LIMITS

zi 4 DISK THYRITE STACK

SYMMETRICAL CURRENT

SYMMETRICAL

CURRENT

PEAK VOLTAGEOFFSET CURRENT

>VJ 0

0 200 400 600 800 1000 1200

E, OF CT (VOLTS)

Figure 23

LYYl

Figure 24

A better connection for a mixed ratio CT appli-cation might be to place the Thyrite unit acrossthe full winding of the higher ratio CT. There arenumerous connections that incorporate this fea-ture, but the particular connection shown inFigure 24 has a number of desirable features. Theconnection shown in Figure 24 does not requireany modification to the PVD nor does it requireany auxiliary CT’s. In fact the higher ratio CT’sserve as auxiliary CT’s as well as main CT’s, andany CT may be removed from service withoutremoving the differential protection.

A difficulty with this scheme is that of calculat-ing the voltage Vxyy for external faults. This comesabout because it is difficult, if not impossible, todetermine the current distribution in the CT sec-ondary jumpers. For example, for a fault on one ofthe 600/5 circuits, it would be difficult to deter-mine how much current would flow in leads Laand Lb, and how much current would flow in leadsLx and Ly. Since this information is required toestablish the Vxy voltage, and hence the PVDsetting, a problem exists.

Outlined below is a conservative approach forobtaining a safe PVD setting for this arrangement.Initially assume that all the lower ratio taps of allthe CT’s are connected in parallel, and the endwindings of the higher ratio CT’s are “floating”.Fig. 25 shows the arrangement for this assumption.Calculate the voltage across the full winding ofeach higher ratio CT for single phase to ground and

FAULT

R4

Y

CT 13+14=11

Figure 25

three phase faults just off the bus on each of thelower rated circuits in turn.

For the purpose of calculating Vxy or Vxdy’ it isassumed as usual that the fault CT saturates com-pletely. The voltage drop across A-B is therefore

VAB’II (RI +KRA) (30)

where:

II =

RA =

K =

secondary current being pushedthrough saturated fault CT

one-way lead resistance from faultCT to junction pts. A&B.

1 for three phase faults, and 2 forsingle phase to ground faults

The voltage across the taps of the higher ratio CT,VT, is then VAB plus the voltage drop in the con-necting leads.

V T (xv) = VAB + 13 (KRD) = (31)

II (RI + KRA) + 13 (KRD)

The internal voltage, V’i, that is amplified by thetotal turns/tap turns ratio is VT plus the voltagedrop in the secondary winding the xy CT. Conse-quently, the amplified internal voltage is:

V’i = P II(RI + KRA) + I3(R2 + KRD) (32)

where

P = total turns/tap turns

17

x

To obtain the external voltage across XY the volt-age drop across the secondary winding resistance,R2, must be subtracted from V’i.

Vx y = P ll(R1 + KRA) + (33)

l3(R2 + KRD) - 13 R2

Vxlyl = P II (RI + KRA) +

14 (R2 + KRc) -14 R2

(34)

Now assume that all the lower ratio CT’s do notexist, and all the higher voltage CT’s are connectedin parallel as shown in Figure 26. Calculate thevoltage across xy for three phase and single phaseto ground faults just off bus on each of the higherrated circuits in turn. This voltage is determinedby equation (35)

V,,= II (R2+ R3+ R4+2RC) (35)

where: Xl = number of lower ratio CT’s

11 = fault current beingsaturated fault CT.

pushed through K’ = the ratio of the lower to the higherCT rating

The pickup setting of the relay will be twice thehigher of the three voltages in equations (33), (34)and (35).

When calculating the minimum internal faultcurrent required to trip the relay equation (36)should be used.

XliF(min) = N’ jR + iThyrite + lEn + (36)

n=1

FAULT CT

Figure 26

where:

X2 = number of higher ratio CT’s

N’ = secondary turns of higher ratio CT’s

In this instance the pickup setting of the PVDmust not exceed the Es value of the poorest higherratio CT, nor l/K’ times the Es value of the poor-est lower ratio CT.

X2K’lEn

n=1

18

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