George Mason University FPGA Memories ECE 448 Lecture 13.
-
Upload
martina-hodge -
Category
Documents
-
view
217 -
download
0
Transcript of George Mason University FPGA Memories ECE 448 Lecture 13.
![Page 1: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/1.jpg)
George Mason University
FPGA Memories
ECE 448Lecture 13
![Page 2: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/2.jpg)
2
Recommended reading
• Spartan-6 FPGA Block RAM Resources: User Guide
Google search: UG383
• Spartan-6 FPGA Configurable Logic Block: User Guide
Google search: UG384
• Xilinx FPGA Embedded Memory Advantages: White Paper
Google search: WP360
![Page 3: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/3.jpg)
3
Recommended reading
• XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections:
• RAM HDL Coding Techniques
• ROM HDL Coding Techniques
•ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module
![Page 4: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/4.jpg)
4
Memory Types
![Page 5: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/5.jpg)
5
Memory Types
Memory
RAM ROM
Single port Dual port
With asynchronous
read
With synchronous
read
Memory
Memory
![Page 6: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/6.jpg)
6
Memory Types specific to Xilinx FPGAs
Memory
Distributed (MLUT-based)
Block RAM-based(BRAM-based)
Inferred Instantiated
Memory
Manually Using CORE Generator
![Page 7: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/7.jpg)
7
FPGA Distributed
Memory
![Page 8: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/8.jpg)
8
Location of Distributed RAMRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP units
RAM blocks
Logic resources
Logic resources(CLB slices)
![Page 9: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/9.jpg)
9
Three Different Types of Slices
50% 25% 25%
![Page 10: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/10.jpg)
10
16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Spartan-6 Multipurpose LUT (MLUT)
64 x 1 ROM
(logic)
64 x 1 RAM
32-bit SR
![Page 11: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/11.jpg)
11
Single-port 64 x 1-bit RAM
![Page 12: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/12.jpg)
12
Memories Built of Neighboring MLUTs
• Single-port 128 x 1-bit RAM: RAM128x1S• Dual-port 64 x 1-bit RAM : RAM64x1D
Memories built of 2 MLUTs:
Memories built of 4 MLUTs:
• Single-port 256 x 1-bit RAM: RAM256x1S• Dual-port 128 x 1-bit RAM: RAM128x1D• Quad-port 64 x 1-bit RAM: RAM64x1Q• Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP
(one address for read, one address for write)
![Page 13: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/13.jpg)
13
Dual-port 64 x 1 RAM
• Dual-port 64 x 1-bit RAM : 64x1D• Single-port 128 x 1-bit RAM: 128x1S
![Page 14: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/14.jpg)
14
Total Size of Distributed RAM
![Page 15: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/15.jpg)
15
FPGA Block RAM
![Page 16: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/16.jpg)
16
Location of Block RAMsRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP units
RAM blocks
Logic resources
Logic resources(CLB slices)
![Page 17: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/17.jpg)
17
Spartan-6 Block RAM Amounts
![Page 18: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/18.jpg)
18
Block RAM can have various configurations (port aspect ratios)
0
16,383
1
4,095
40
8,191
20
2047
8+10
1023
16+20
16k x 1
8k x 2 4k x 4
2k x (8+1)
1024 x (16+2)
![Page 19: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/19.jpg)
19
![Page 20: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/20.jpg)
20
![Page 21: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/21.jpg)
21
Block RAM Port Aspect Ratios
![Page 22: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/22.jpg)
22
Block RAM Interface
![Page 23: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/23.jpg)
23
Block RAM Ports
![Page 24: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/24.jpg)
24
Block RAM Waveforms – READ_FIRST mode
![Page 25: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/25.jpg)
25
Block RAM Waveforms – WRITE_FIRST mode
![Page 26: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/26.jpg)
26
Block RAM Waveforms – NO_CHANGE mode
![Page 27: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/27.jpg)
27
Features of Block RAMs in Spartan-6 FPGAs
![Page 28: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/28.jpg)
28
Inference vs.
Instantiation
![Page 29: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/29.jpg)
29
![Page 30: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/30.jpg)
30
Using
CORE
Generator
![Page 31: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/31.jpg)
31
CORE Generator
![Page 32: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/32.jpg)
32
CORE Generator
![Page 33: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/33.jpg)
33
Generic
Inferred
ROM
![Page 34: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/34.jpg)
34
Distributed ROM with asynchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM;
![Page 35: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/35.jpg)
35
Distributed ROM with asynchronous read
architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;
![Page 36: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/36.jpg)
36
Distributed ROM with asynchronous read
architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("0C4", "4D2", "4DB", "6C2", "0F1", "7D6", "4D0", "F9F"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;
![Page 37: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/37.jpg)
37
Generic
Inferred
RAM
![Page 38: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/38.jpg)
38
Distributed versus Block RAM Inference
Examples:1. Distributed single-port RAM with asynchronous read
2. Distributed dual-port RAM with asynchronous read
1. Block RAM with synchronous read (no version with asynchronous read!)
More excellent RAM examples from XST Coding Guidelines.
![Page 39: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/39.jpg)
39
Distributed single-port RAM with asynchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;
![Page 40: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/40.jpg)
40
Distributed single-port RAM with asynchronous read
architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;
![Page 41: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/41.jpg)
41
Distributed dual-port RAM with asynchronous read
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr;
![Page 42: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/42.jpg)
42
Distributed dual-port RAM with asynchronous read
architecture syn of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector
(w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn;
![Page 43: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/43.jpg)
43
Block RAM Waveforms – READ_FIRST mode
![Page 44: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/44.jpg)
44
Block RAM with synchronous read
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;
![Page 45: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/45.jpg)
45
Block RAM with synchronous read Read-First Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;
begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then do <= RAM(conv_integer(unsigned(addr))); if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; end if; end if; end if; end process; end behavioral;
![Page 46: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/46.jpg)
46
Block RAM Waveforms – WRITE_FIRST mode
![Page 47: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/47.jpg)
47
Block RAM with synchronous read Write-First Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;
begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di;
do <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral;
![Page 48: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/48.jpg)
48
Block RAM Waveforms – NO_CHANGE mode
![Page 49: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/49.jpg)
49
Block RAM with synchronous read No-Change Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;
begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral;
![Page 50: George Mason University FPGA Memories ECE 448 Lecture 13.](https://reader035.fdocuments.us/reader035/viewer/2022062423/56649e855503460f94b87821/html5/thumbnails/50.jpg)
50
Criteria for Implementing Inferred RAM in BRAMs