ECE 449 – Computer Design Lab George Mason University

Welcome to the ECE 449Computer Design Lab

Spring 2005

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Your TA – Monday & Tuesday section

Milind M. Parelkare-mail: mparelkar@gmu.edu

Office hours:

TBD

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Your TA – Thursday section

Kamal Sayeed

e-mail: ask4087@yahoo.com

Office hours:

Wednesday 7-9pm, Room 203

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Lab meetings

• Venue: ST-II, Room 203

• The first part of each class is reserved for a lecture given by the TA and the following hands-on session

• The second part of each class is reserved for the previous experiment demonstrations and the work on the new experiment

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Lab policies

• Please refer to class website:

ECE 449 Official Class Web Resources

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Lab experiments (Part I, Individual)

• Combinational Logic – 7 Segment LED, etc.• January 31- February 3

• Sequential Logic – Blinking LEDs (Simulation)• February 7-10

• Sequential Logic – Blinking LEDs (Testing)• February 14-17

• Finite State Machine – Sequence Detector • February 21-24

• Finite State Machine – Pump Controller• February 28-March 3

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Lab experiments (Part II, Dual)

• Programmable Pulse Generator • March 21-24• March 28-31

• VGA Signal Generator • April 4-7• April 11-14

• Microcontroller Core & Logic Analyzer• April 18-21• April 25-28• May 2-5

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Displaying Vertical Bars on the VGA screen

End of Screen

Color 1 Color 2 Color 64 ColorsRepeat

8 pixels 8 pixels

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4 lines

4 lines

Color 1

Color 2

Color 64

ColorsRepeat

4 lines

4 lines

Color 3

Color 4

Displaying Horizontal Bars on the VGA screen

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Horizontal TraceHorizontal Flyback

Vertical Flyback

0 628

479

0

Generating pixels on the VGA monitor screen

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VGA Control Signal Timing

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Experiment 7: Top level view of the implemented circuit

PICµController

FPGA

PORTB PORTA

7-Seg Decoder

PORTADisplay

PORTC= PORTC(0)STROBE

CLK

RESET

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PICROM256 x 12

Data

Addr

PROGRAM

PC

Instruction Decoder

W ALU

COMPUTATIONS

8

12

4CONSTANTS OPCODES

Address Bus

Data Bus

8

8

CONTROL UNIT

MCLR CLK

EXTENDEDALU PORTA PORTB PORTC

4 8 8

DATA

FSRDin Dout

REGFILE

R8

R31

Fsel

4 8 8

8

PIC Microcontroller Core

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Set Port Directions

RESET

Sum <= ‘0’Counter <= ‘0’

Wait for a rising edge at Port C(0)

Port B <= Port ASum <= Sum + Port A

Counter <= Counter + 1

Counter = 8?

N

Y

Wait for a rising edge at Port C(0)

Port B <= Sum(3 downto 0)

Wait for a rising edge at Port C(0)

Port B <= Sum(7 downto 4)

Flowchart of our PIC program

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Experiment 7-LA: Top level view of the implemented circuit

PICµController

FPGA

PORTB PORTA

7-Seg Decoder

PORTADisplay

PORTC= PORTC(0)STROBE

CLK

RESET

4

128

Addr Data

8

8

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Grading

• Lab Experiments (Part I) 30%

• Midterm exam 35%• March 7, 8, 10

• Lab Experiments (Part II) 35%

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Recommended Texts (1)

• Allen Dewey, Analysis and Design of Digital Systems with VHDL, 1997, PWS publishing, ISBN 0-534-95410-3

• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right

• Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill © 2000 Edition: 1 ISBN: 0072355964.

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Software

• ActiveHDL by Aldec• used for design entry and simulation

• Synplify Pro by Synplicity• used for logic synthesis

• Xilinx ISE by Xilinx Inc.• used for implementation in Xilinx FPGA

devices

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Hardware

• XSA-100 boards with Xilinx Spartan 2 FPGA 2S100tq144 used in Spring 2004

• New boards from Xilinx are likely to be used in Spring 2005

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