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Transcript of George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine...
![Page 1: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/1.jpg)
George Mason University
Design of Controllers
Finite State Machines andAlgorithmic State Machine (ASM) Charts
ECE 545Lecture 14
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2
Required reading
• P. Chu, RTL Hardware Design using VHDL
Chapter 10, Finite State Machine: Principle & Practice
Chapter 11, Register Transfer Methodology:
Principle
Chapter 12, Register Transfer Methodology:
Practice
![Page 3: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/3.jpg)
3
Slides based partially on
• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 8, Synchronous Sequential Circuits
Sections 8.1-8.5
Chapter 8.10, Algorithmic State Machine
(ASM) Charts
Chapter 10.2 Design Examples
![Page 4: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/4.jpg)
4ECE 448 – FPGA and ASIC Design with VHDL
Datapath
vs.
Controller
![Page 5: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/5.jpg)
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Structure of a Typical Digital System
Datapath(Execution
Unit)
Controller(Control
Unit)
Data Inputs
Data Outputs
Control Inputs
Control Outputs
Control Signals
StatusSignals
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Datapath (Execution Unit)
• Manipulates and processes data• Performs arithmetic and logic operations,
shifting, and other data-processing tasks• Is composed of registers, gates, multiplexers,
decoders, adders, comparators, ALUs, etc.• Provides all necessary resources and
interconnects among them to perform specified task
• Interprets control signals from the Controller and generates status signals for the Controller
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Controller (Control Unit)
• Controls data movements in the Datapath by switching multiplexers and enabling or disabling resources
Example: enable signals for registersExample: control signals for muxes
• Provides signals to activate various processing tasks in the Datapath
• Determines the sequence the operations performed by Datapath
• Follows Some ‘Program’ or Schedule
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Controller• Controller can be programmable or non-programmable• Programmable
• Has a program counter which points to next instruction• Instructions are held in a RAM or ROM externally• Microprocessor is an example of programmable
controller• Non-Programmable
• Once designed, implements the same functionality• Another term is a “hardwired state machine” or
“hardwired instructions”• In the following several lectures we will be
focusing on non-programmable controllers.
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Finite State Machines• Digital Systems and especially their Controllers can be
described as Finite State Machines (FSMs)• Finite State Machines can be represented using
• State Diagrams and State Tables - suitable for simple digital systems with a relatively few inputs and outputs
• Algorithmic State Machine (ASM) Charts - suitable for complex digital systems with a large number of inputs and outputs
• All these descriptions can be easily translated to the corresponding synthesizable VHDL code
![Page 10: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/10.jpg)
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Hardware Design with RTL VHDL
Pseudocode
Datapath Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code VHDL code VHDL code
Interface
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11ECE 448 – FPGA and ASIC Design with VHDL
Finite State Machines
Refresher
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Finite State Machines (FSMs)
• Any Circuit with Memory Is a Finite State Machine• Even computers can be viewed as huge FSMs
• Design of FSMs Involves• Defining states• Defining transitions between states• Optimization / minimization
• Manual Optimization/Minimization Is Practical for Small FSMs Only
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Moore FSM
• Output Is a Function of a Present State Only
Present Stateregister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clockreset
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Mealy FSM• Output Is a Function of a Present State and
Inputs
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present Stateregister
clockreset
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15ECE 448 – FPGA and ASIC Design with VHDL
State Diagrams
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Moore Machine
state 1 /output 1
state 2 /output 2
transitioncondition 1
transitioncondition 2
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Mealy Machine
state 1 state 2
transition condition 1 /output 1
transition condition 2 /output 2
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Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be Functionally Equivalent• Equivalent Mealy FSM can be derived from
Moore FSM and vice versa
• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States• Smaller circuit area
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Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as Inputs Change• Mealy FSM responds one clock cycle sooner
than equivalent Moore FSM
• Moore FSM Has No Combinational Path Between Inputs and Outputs• Moore FSM is more likely to have a shorter
critical path
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Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
![Page 22: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/22.jpg)
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Moore & Mealy FSMs – Example 1
clock
input
Moore
Mealy
0 1 0 0 0
S0 S1 S2 S0 S0
S0 S1 S0 S0 S0
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23ECE 448 – FPGA and ASIC Design with VHDL
Finite State Machines
in VHDL
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FSMs in VHDL
• Finite State Machines Can Be Easily Described With Processes
• Synthesis Tools Understand FSM Description if Certain Rules Are Followed• State transitions should be described in a
process sensitive to clock and asynchronous reset signals only
• Output function described using rules for combinational logic, i.e. as concurrent statements or a process with all inputs in the sensitivity list
![Page 25: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/25.jpg)
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Moore FSM
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
clockreset
process(clock, reset)
concurrent statements
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Mealy FSM
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clockreset
process(clock, reset)
concurrent statements
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Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
![Page 28: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/28.jpg)
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Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)BEGIN
IF(reset = ‘1’) THENMoore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS
WHEN S0 => IF input = ‘1’ THEN
Moore_state <= S1; ELSE Moore_state <= S0; END IF;
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Moore FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Moore_state <= S2; ELSE Moore_state <= S1; END IF;
WHEN S2 => IF input = ‘0’ THEN
Moore_state <= S0; ELSE
Moore_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
![Page 30: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/30.jpg)
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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
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Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)BEGIN
IF(reset = ‘1’) THENMealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS
WHEN S0 => IF input = ‘1’ THEN
Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
![Page 32: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/32.jpg)
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Mealy FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0; ELSE Mealy_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
![Page 33: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/33.jpg)
33ECE 448 – FPGA and ASIC Design with VHDL
Algorithmic State Machine (ASM)
Charts
![Page 34: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/34.jpg)
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Algorithmic State Machine
Algorithmic State Machine –
representation of a Finite State Machine
suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables.
![Page 35: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/35.jpg)
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Elements used in ASM charts (1)
Output signalsor actions
(Moore type)
State name
Condition expression
0 (False) 1 (True)
Conditional outputs or actions (Mealy type)
(a) State box (b) Decision box
(c) Conditional output box
![Page 36: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/36.jpg)
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State Box• State box – represents a state.• Equivalent to a node in a state diagram or a
row in a state table.• Contains register transfer actions or output
signals• Moore-type outputs are listed inside of
the box. • It is customary to write only the name of the
signal that has to be asserted in the given state, e.g., z instead of z<=1.
• Also, it might be useful to write an action to be taken, e.g., count <= count + 1, and only later translate it to asserting a control signal that causes a given action to take place (e.g., enable signal of a counter).
Output signalsor actions
(Moore type)
State name
![Page 37: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/37.jpg)
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Decision Box
• Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordingly
The condition expression may include one or more inputs to the FSM.
Condition expression
0 (False) 1 (True)
![Page 38: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/38.jpg)
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Conditional Output Box
• Conditional output box
• Denotes output signals that are of the Mealy type.
• The condition that determines whether such outputs are generated is specified in the decision box.
Conditional outputs or actions (Mealy type)
![Page 39: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/39.jpg)
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ASMs representing simple FSMs
• Algorithmic state machines can model both Mealy and Moore Finite State Machines
• They can also model machines that are of the mixed type
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Moore FSM – Example 2: State diagram
C z 1 =
Reset
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
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Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM – Example 2: State table
![Page 42: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/42.jpg)
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w
w
w 0 1
0
1
0
1
A
B
C
z
Reset
w
w
w 0 1
0
1
0
1
A
B
C
z
Reset
ASM Chart for Moore FSM – Example 2
![Page 43: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/43.jpg)
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USE ieee.std_logic_1164.all ;
ENTITY simple ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END simple ;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
Example 2: VHDL code (1)
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CASE y ISWHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;WHEN B =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;WHEN C =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;END CASE ;
Example 2: VHDL code (2)
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Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
![Page 46: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/46.jpg)
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset
w 1 = z 0 =
Mealy FSM – Example 3: State diagram
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ASM Chart for Mealy FSM – Example 3
w
w 0 1
0
1
A
B
Reset
z
![Page 48: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/48.jpg)
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LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END Mealy ;
ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
Example 3: VHDL code (1)
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Example 3: VHDL code (2)
CASE y IS WHEN A => IF w = '0' THEN
y <= A ;ELSE
y <= B ;END IF ;
WHEN B =>IF w = '0' THEN
y <= A ;ELSE
y <= B ; END IF ;END CASE ;
![Page 50: George Mason University Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts ECE 545 Lecture 14.](https://reader035.fdocuments.us/reader035/viewer/2022062321/56649ef15503460f94c0190d/html5/thumbnails/50.jpg)
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Example 3: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN (y = B) AND (w=‘1’) ELSE '0' ;
END Behavior ;
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Control Unit Example: Arbiter (1)
Arbiter
reset
r1
r2
r3
g1
g2
g3
clock
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Idle
000
1xx
Reset
gnt1 g 1 1 =
x1x
gnt2 g 2 1 =
xx1
gnt3 g 3 1 =
0xx 1xx
01x x0x
001 xx0
Control Unit Example: Arbiter (2)
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Control Unit Example: Arbiter (3)
r 1 r 2
r 1 r 2 r 3
Idle
Reset
gnt1 g 1 1 =
gnt2 g 2 1 =
gnt3 g 3 1 =
r 1 r 1
r 1
r 2
r 3
r 2
r 3
r 1 r 2 r 3
r 1 r 2
r 1 r 2 r 3
Idle
Reset
gnt1 g 1 1 =
gnt2 g 2 1 =
gnt3 g 3 1 =
r 1 r 1
r 1
r 2
r 3
r 2
r 3
r 1 r 2 r 3
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ASM Chart for Control Unit - Example 4
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
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Example 4: VHDL code (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY arbiter IS
PORT ( Clock, Resetn : IN STD_LOGIC ;
r : IN STD_LOGIC_VECTOR(1 TO 3) ;
g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;
END arbiter ;
ARCHITECTURE Behavior OF arbiter IS
TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;
SIGNAL y : State_type ;
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Example 4: VHDL code (2)BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= Idle ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN Idle =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSIF r(2) = '1' THEN y <= gnt2 ;
ELSIF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt1 =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt2 =>
IF r(2) = '1' THEN y <= gnt2 ;
ELSE y <= Idle ;
END IF ;
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57
Example 4: VHDL code (3)
WHEN gnt3 =>
IF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ;
g(2) <= '1' WHEN y = gnt2 ELSE '0' ;
g(3) <= '1' WHEN y = gnt3 ELSE '0' ;
END Behavior ;
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RTL Hardware Design by P. Chu
Chapter 10 58
1. Overview on FSM
• Contain “random” logic in next-state logic• Used mainly used as a controller in a
large system• Mealy vs Moore output
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RTL Hardware Design by P. Chu
Chapter 10 59
2. Representation of FSM
• State diagram
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RTL Hardware Design by P. Chu
Chapter 10 60
• E.g. a memory controller
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RTL Hardware Design by P. Chu
Chapter 10 61
• ASM (algorithmic state machine) chart – Flowchart-like diagram – Provide the same info as an FSM– More descriptive, better for complex
description– ASM block
• One state box• One ore more optional decision boxes: with T or F
exit path• One or more conditional output boxes: for Mealy
output
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RTL Hardware Design by P. Chu
Chapter 10 62
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RTL Hardware Design by P. Chu
Chapter 10 63
State diagram and ASM chart conversion• E.g. 1.
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RTL Hardware Design by P. Chu
Chapter 10 64
• E.g. 2.
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RTL Hardware Design by P. Chu
Chapter 10 65
• E.g. 3.
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RTL Hardware Design by P. Chu
Chapter 10 66
• E.g. 4.
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RTL Hardware Design by P. Chu
Chapter 10 67
• E.g. 6.
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RTL Hardware Design by P. Chu
Chapter 10 68
• Difference between a regular flowchart and ASM chart:– Transition governed by clock – Transition done between ASM blocks
• Basic rules:– For a given input combination, there is one
unique exit path from the current ASM block– The exit path of an ASM block must always
lead to a state box. The state box can be the state box of the current ASM block or a state box of another ASM block.
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RTL Hardware Design by P. Chu
Chapter 10 69
• Incorrect ASM charts:
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RTL Hardware Design by P. Chu
Chapter 10 70
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RTL Hardware Design by P. Chu
Chapter 10 71
4. Moore vs Mealy output
• Moore machine: – output is a function of state
• Mealy machine: – output function of state and output
• From theoretical point of view– Both machines have similar “computation
capability”
• Implication of FSM as a controller?
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RTL Hardware Design by P. Chu
Chapter 10 72
• E.g., edge detection circuit– A circuit to detect the rising edge of a slow
“strobe” input and generate a “short” (about 1-clock period) output pulse.
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RTL Hardware Design by P. Chu
Chapter 10 73
• Three designs:
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RTL Hardware Design by P. Chu
Chapter 10 74
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RTL Hardware Design by P. Chu
Chapter 10 75
• Comparison– Mealy machine uses fewer states– Mealy machine responds faster– Mealy machine may be transparent to glitches
• Which one is better?• Types of control signal
– Edge sensitive• E.g., enable signal of counter• Both can be used but Mealy is faster
– Level sensitive• E.g., write enable signal of SRAM• Moore is preferred
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RTL Hardware Design by P. Chu
Chapter 10 76
VHDL Description of FSM
• Follow the basic block diagram
• Code the next-state/output logic according to the state diagram/ASM chart
• Use enumerate data type for states
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RTL Hardware Design by P. Chu
Chapter 10 77
• E.g. 6.
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RTL Hardware Design by P. Chu
Chapter 10 78
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RTL Hardware Design by P. Chu
Chapter 10 79
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RTL Hardware Design by P. Chu
Chapter 10 80
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RTL Hardware Design by P. Chu
Chapter 10 81
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RTL Hardware Design by P. Chu
Chapter 10 82
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RTL Hardware Design by P. Chu
Chapter 10 83
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RTL Hardware Design by P. Chu
Chapter 10 84
• Combine next-state/output logic together
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RTL Hardware Design by P. Chu
Chapter 10 85
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RTL Hardware Design by P. Chu
Chapter 10 86
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sorting
example
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Sorting - Required Interface
Sort
Clock
Resetn
DataInN
DataOut
N
DoneRAdd
L
WrInit
S(0=initialization 1=computations)
Rd
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Sorting - Required Interface
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Simulation results for the sort operation (1)Loading memory and starting sorting
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Simulation results for the sort operation (2)Completing sorting and reading out memory
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Before
sorting
During Sorting After
sorting
Address
0
1
2
3
3 3 2 2 1 1 1 1
2 2 3 3 3 3 2 2
4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
i=0 i=0 i=0 i=1 i=1 i=2
j=1 j=2 j=3 j=2 j=3 j=3
MiMj
Legend:position of memory
indexed by i
position of memory
indexed by j
Sorting - Example
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Pseudocode
for i = 0 tok 2 doA = M i ; for j = i + 1 tok 1 do
B = M j ; if B < A then
M i = B ; M j = A ; A = M i ;
endif ; endfor;
endfor;
–
–[load input data]
[read output data]
for i = 0 to 2 doA = M i ; for j = i + 1 to3 do
B = M j ; if B < A then
M i = B ; M j = A ; A = M i ;
endif ; endfor;
endfor;
[load input data]
[read output data]
FOR k = 4 FOR any k ≥ 2
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Pseudocode
wait for s=1for i=0 to k-2 do
A = Mi
for j=i+1 to k-1 doB = Mj
if A > B thenMi = BMj = AA = Mi
end ifend for
end forDonewait for s=0go to the beginning
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DIN
DOUT
ADDR
WE
CLK
ENCLK RST
ENCLK RST
A>B
10 WrInit
WrInit
Clock
Clock
Clock
Resetn Resetn
Wr
1 0 Bout
EA EB
AgtB
Addr
Int
0
10
1
DataIn RAdd
Rdout
DataOut
Csel
ENCLK
LDRST
Resetn
ENCLK
LDRST
Resetn
LiEi
Clock
LjEj
Clock
= k-2 = k-1
zi zj
NL
L
LL
N N
N
N
N
ABMux
A B
i
j
Mij
Din
We
0
L
+1
Block diagram of the Execution Unit
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N
Clock Resetn
DataOut
N
WrInit s
Done
Int
Wr
Li
Ei
Lj
Ej
EA
EB
Bout
Csel
Rdout
Datapath Controller
RAddr
L
zizj
Interface with the division into the Datapath and the Controller
DataIn Rd
AgtB