General Purpose Input Output GPIO ECE 699: Lecture 3.
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Transcript of General Purpose Input Output GPIO ECE 699: Lecture 3.
General Purpose Input OutputGPIO
ECE 699: Lecture 3
Required Reading
• Chapter 2: The Zynq Device (“What is it?)
The ZYNQ Book
• Tutorial 1: First Designs on ZYNQ• Tutorial 2: Next Steps in Zynq SoC Design
The ZYNQ Book Tutorials
• Section 13: Basic I/O
ZYBO Reference Manual
LogiCORE IP AXI GPIO Product Specification
LogiCORE IP AXI GPIO v2.0 Product Guide
ZYBO Board
Source: ZYBO Reference Manual
ZYBO Board Components
Source: ZYBO Reference Manual
Source: The Zynq Book Tutorials
ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual
Mapping of an Embedded SoC Hardware Architecture to Zynq
Source: Xilinx White Paper: Extensible Processing Platform
Mapping of an Embedded SoC Hardware Architecture to Zynq
Source: The Zynq Book
A Simplified Model of the Zynq Architecture
Source: The Zynq Book
Source: The Zynq Book Tutorials
Source: The Zynq Book Tutorials
Source: The Zynq Book Tutorials
ZYBO Board
Source: ZYBO Reference Manual
ZYBO Board Components
Source: ZYBO Reference Manual
The Zynq Processing System
Source: The Zynq Book
Simplified Block Diagram ofthe Application Processing Unit (APU)
Source: The Zynq Book
AXI GPIO Features
• Configurable single or dual GPIO channel(s)
• Each channel configurable to have from 1 to 32 bits
• Dynamic programming of each GPIO bit as
input or output
• Individual configuration of each channel
• Independent reset values for each bit of all registers
• Optional interrupt request generation
• AXI4-Lite interface to Processing System
Block Diagram of AXI GPIO
IPIC – IP Interconnect interface
enabled only when the C_INTERRUPT_PRESENTgeneric set to 1
Source: LogiCORE IP AXI GPIO: Product Specification
GPIO Core
Source: LogiCORE IP AXI GPIO: Product Specification
Source: LogiCORE IP AXI GPIO: Product Specification
GPIO Core Parameters
Setting GPIO Core Parameters in Vivado
Setting GPIO Core Parameters in Vivado
GPIO_DATA and GPIO2_DATA Registers
Source: LogiCORE IP AXI GPIO: Product Specification
GPIO_TRI and GPIO2_TRI Registers
Source: LogiCORE IP AXI GPIO: Product Specification
C_HIGHADDR – C_BASEADDR ≥ 0xFFF
AXI GPIO System Parameters
Source: LogiCORE IP AXI GPIO: Product Specification
Source: LogiCORE IP AXI GPIO: Product Specification
Addresses of AXI GPIO Registers
Address Editor in Vivado
AXI Interconnects and Interfaces
Source: The Zynq Book
/* Include Files */
#include "xparameters.h"#include "xgpio.h"#include "xstatus.h"#include "xil_printf.h"
/* Definitions */#define GPIO_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID/* GPIO device that LEDs are connected to */#define LED 0x03 /* Initial LED value */#define LED_DELAY 10000000 /* Software delay length */#define LED_CHANNEL 1 /* GPIO port for LEDs */#define printf xil_printf /* smaller, optimized printf */
C Program (1)
XGpio Gpio; /* GPIO Device driver instance */
int LEDOutputExample(void){
volatile int Delay; int Status; int led = LED; /* Hold current LED value. Initialize to LED definition */
/* GPIO driver initialization */ Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID); if (Status != XST_SUCCESS) {
return XST_FAILURE; }
/*Set the direction for the LEDs to output. */ XGpio_SetDataDirection(&Gpio, LED_CHANNEL, 0x00);
C Program (2)
/* Loop forever blinking the LED. */ while (1) { /* Write output to the LEDs. */ XGpio_DiscreteWrite(&Gpio, LED_CHANNEL, led);
/* Flip LEDs. */ led = ~led;
/* Wait a small amount of time so that the LED blinking is visible. */ for (Delay = 0; Delay < LED_DELAY; Delay++); }
return XST_SUCCESS; /* Ideally unreachable */}
C Program (3)
/* Main function. */int main(void){
int Status;
/* Execute the LED output. */Status = LEDOutputExample();if (Status != XST_SUCCESS) {
xil_printf("GPIO output to the LEDs failed!\r\n");}
return 0;}
C Program (4)
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
xparameters.h
Source: LogiCORE IP AXI GPIO: Product Specification
Constraints File
ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual
entity design_1_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; leds_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ) );end design_1_wrapper;
design_1_i: component design_1 port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, leds_tri_o(3 downto 0) => leds_tri_o(3 downto 0) );
##LEDs##IO_L23P_T3_35set_property PACKAGE_PIN M14 [get_ports {leds_tri_o[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[0]}]
##IO_L23N_T3_35set_property PACKAGE_PIN M15 [get_ports {leds_tri_o[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[1]}]
##IO_0_35set_property PACKAGE_PIN G14 [get_ports {leds_tri_o[2]}]set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[2]}]
##IO_L3N_T0_DQS_AD1N_35set_property PACKAGE_PIN D18 [get_ports {leds_tri_o[3]}]set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[3]}]
ZYBO_Master.xdc (1)
ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual
##Switches##IO_L19N_T3_VREF_35#set_property PACKAGE_PIN G15 [get_ports {sw[0]}]#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
##IO_L24P_T3_34#set_property PACKAGE_PIN P15 [get_ports {sw[1]}]#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
##IO_L4N_T0_34#set_property PACKAGE_PIN W13 [get_ports {sw[2]}]#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
##IO_L9P_T1_DQS_34#set_property PACKAGE_PIN T16 [get_ports {sw[3]}]#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
ZYBO_Master.xdc (2)
##Buttons##IO_L20N_T3_34#set_property PACKAGE_PIN R18 [get_ports {btn[0]}]#set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
##IO_L24N_T3_34#set_property PACKAGE_PIN P16 [get_ports {btn[1]}]#set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
##IO_L18P_T2_34#set_property PACKAGE_PIN V16 [get_ports {btn[2]}]#set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
##IO_L7P_T1_34#set_property PACKAGE_PIN Y16 [get_ports {btn[3]}]#set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
ZYBO_Master.xdc (3)