Gd tCGraduate Course on Embedded Control Systems… · Embedded Control Systems:Embedded Control...

G d t CGraduate Course onEmbedded Control Systems:Embedded Control Systems:

Theory and Practice

Scuola Superiore Sant’Anna, Pisa8-12 June 2009

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 1

Program at glanceg g• Day 1: Mon. July 8 – Real-Time Day• Day 1: Mon. July 8 Real Time Day

• Day 2: Tue. July 9 – Platform Dayy y y

• Day 3: Wed. July 10 – Control Day

• Day 4: Thu. July 11 – Networks Day

• Day 5: Fri. July 12 – Judgment Day


Mon July 8 – Real-Time DayMon. July 8 Real Time Day09:00 Introduction to real-time systems (Giorgio Buttazzo)y ( g )

10:30 Coffee Break

11:00 Real-time scheduling and resource management

13:00 Lunch Break13:00 Lunch Break

14:00 Aperiodic Scheduling and Reservations

16:00 Break

16:30 dsPic architecture: overview (Mauro Marinoni)16:30 dsPic architecture: overview (Mauro Marinoni)

18:30 End of Session


Tue July 9 – Platform DayTue. July 9 Platform Day08:30 Operating systems for micro-controllers (Paolo Gai)p g y ( )

10:30 Coffee Break

11:00 The OSEK standard (Paolo Gai)


14:00 The Erika kernel (Paolo Gai)

16:00 Break

16:30 Lab practice on Flex and Erika (Mauro Marinoni)16:30 Lab practice on Flex and Erika (Mauro Marinoni)



Wed July 10 – Control DayWed. July 10 Control Day08:30 Integrated control and scheduling (Karl-Erik Arzen)g g ( )

10:30 Coffee Break

11:00 Control of computing systems (Karl-Erik Arzen)


14:00 Lab practice on control (Anton Cervin)

16:00 Break

16:30 Lab practice on control (Anton Cervin)16:30 Lab practice on control (Anton Cervin)



Thu July 11 – Network DayThu. July 11 Network Day08:30 Real-Time Networks (Luis Almeida)( )

10:30 Coffee Break

11:00 Medium Access Control (Luis Almeida)


14:00 Networked control systems (Anton Cervin)

16:00 Break

16:30 Lab practice on networks (Anton Cervin)16:30 Lab practice on networks (Anton Cervin)



Fri July 12 – Judgment DayFri. July 12 Judgment Day

09:00 Final Exam (3 credits)

13:00 Lunch Break

14:00 Lab practice

18:00 Closing remarks and certificatesg


Real-TimeReal-Time SchedulingScheduling

Giorgio Buttazzo

Scuola Superiore Sant’Anna, Pisa

E-mail: [email protected]

GoalGoalProvide some background of RT theory that

l f i l ti RT t lyou can apply for implementing RT controlapplications:

• Terminology and models

• Basic results on periodic scheduling

A i di k h dli• Aperiodic task handling

• Inter-task communication• Inter-task communication

• Overload and QoS managementGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 9

R l Ti tReal-Time system

Real-Timeevent

Real-TimeSystem action

A computing system able to respond toevents within precise timing constraints.p g


R l Ti tReal-Time system

EnvironmentRT systemx (t)

y

yt

(t+Δ)y (t+Δ)

It is a system in which the correctness dependsnot only on the output values, but also on thetime at which results are produced.


Typical applicationsy• flight control systems• robotics• automotive applicationsautomotive applications• multimedia systems• virtual reality• small embedded devices

⇒ cell phones⇒ digital TV⇒ digital TV⇒ videogames⇒ intelligent toysg y

ImplicationsImplicationsTi i t i t i d b th• Timing constraints are imposed by thedynamics of the environment.

• The tight interaction with the environmentrequires the system to react to events withinrequires the system to react to events withinprecise timing constraints.

The operating system is responsible forThe operating system is responsible forenforcing such constraints on task execution.


Multi-level feedback controlF3

S3 A3F2

S i Control

S2 A2F1

Sensing Control

F1

Environment

S1 A1


Software VisionSoftware Visioncomputercomputer

actuatorsD/A

Environment

sensorsA/D

Thread (task) Resource


Traditional ApproachTraditional Approach• In spite of this large application domain most• In spite of this large application domain, most

of RT applications are designed usingempirical techniques:empirical techniques:– assembly programming

– timing through dedicated timers

– control through driver programmingcontrol through driver programming

– priority manipulations

The resulting SW can be very efficient, but … Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 16

Disadvantages

1. Tedious programming which heavilydepends on programmer’s abilitydepends on programmer s ability

2 Difficult code understanding2. Difficult code understanding

Readability ∝1

efficiencyefficiency


An efficient C programAn efficient C programint a[1817];main(z,p,q,r){{for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)for(z=9;z ;)q=3&(r=time(0)+r*57)/7,q=q?q-1?

q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,

q?!a[p+q*2]?a[p+=a[p+=q]=q]=q :0:0;f ( ++ 1817 )for(;q++-1817;)printf(q%79?"%c":"%c\n"," Û"[!a[q-1]]);

}Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 18

}

DisadvantagesDisadvantages3. Difficult software maintainability

• Complex appl s consists of millions lines of code• Complex appl.s consists of millions lines of code

• Code understanding takes more that re-writing

• But re-writing is VERY expensive and bug prone

4. Difficult to verify timing constraints withoutexplicit support from the OS and thep pplanguage


ImplicationsImplications

• Such a way of programming RT applicationsis very dangerous.

• It may work in most situations, but the risk off il i hi ha failure is high.

• When the system fails is very difficult to• When the system fails is very difficult tounderstand why.

low reliability


Real-Time ≠ FastReal-Time ≠ Fast

τ1

τ2

double speed deadline miss

τ1

τ2


Speed vs PredictabilitySpeed vs. PredictabilityTh bj ti f l ti t i t• The objective of a real-time system is toguarantee the timing behavior of eachi di id l t kindividual task.

• The objective of a fast system is to minimize• The objective of a fast system is to minimizethe average response time of a task set.

ButBut …

D ’t t t h h tDon’t trust average when you have toguarantee individual performance


L l dLessons learnedT t t h f l ti t• Tests are not enough for real-time systems

• Intuitive solutions do not always worky

• Delay should not be used in real-time tasks

A safe approach:pp♦ use predictable kernel mechanisms

l th t t di t it b h i♦ analyze the system to predict its behavior


A hi i di t bilitAchieving predictability• The operating system is the part most

responsible for a predictable behavior.p p

• Concurrency control must be enforced by:⇒ appropriate scheduling algorithms

⇒ appropriate syncronization protocols⇒ appropriate syncronization protocols

⇒ efficient communication mechanisms

di t bl i t t h dli⇒ predictable interrupt handling

⇒ overload management


Let’s review the mainLet s review the mainh d li lscheduling results


TerminologyTerminology• Task (or thread)• Task (or thread)

is a sequence of instructions that in theabsence of other activities is continuouslyabsence of other activities is continuouslyexecuted by the processor until completion.

task τirelease time

Cicomputation time

task τistart time tri si fi

finishing timerelease timeactivation timearrival time


arrival time

T k d j bTasks and jobs

A task is an infinite sequence of instances(jobs):(jobs)

Job 1τi,1 τi,2 τi,3

Job 2 Job 3

τiCi

ri,k ri,k+1t

τi

ri,1


Activation modes

• Time driven: periodic tasksthe task is automatically activated by thekernel at regular intervals.g

• Event driven: aperiodic taskspthe task is activated upon the arrival of anevent or through an explicit invocation ofevent or through an explicit invocation ofthe activation primitive.


P i di t k d lPeriodic task modelr = Φri1 = Φi

ri,k+1 = ri,k + Ti

Ti

C

τi (Ci , Ti , Di )

r r t

Ci

r Φ ri,k ri,k+1 tri,1 = Φi

r = Φ + (k 1) T ftri,k = Φi + (k−1) Ti

di,k = ri,k + Di

oftenDi = Ti


, ,

Aperiodic task model

• Aperiodic: ri,k+1 > ri,kp , ,

• Sporadic: ri k+1 ≥ ri k + Ti• Sporadic: ri,k+1 ≥ ri,k + Ti

Job 1 Job 2 Job 3

τiCi

Job 2 Job 3

ri,k ri,k+1t

i

ri,1


S h d liScheduling• A scheduling algorithm is said to be:

– preemptive: if the running task can betemporarely suspended in the ready queueto execute a more important task.

– non preemptive: if the running task cannotnon preemptive: if the running task cannotbe suspended until completion.


ScheduleA schedule is a particular assignment of tasksto the processor.

Given a task set Γ = {τ1, …, τn}, a schedule is amapping σ : R+ → N such that ∀t ∈ R+, ∃t1, t2 :mapping σ : R → N such that ∀t ∈ R , ∃t1, t2 :

t ∈ [t1, t2) e ∀t’ ∈ [t1, t2) : σ(t) = σ(t’)

k > 0 if τk is runningσ(t) = k g

0 if the processor is idle


A l h d lA sample schedule

σ(t)

τ1 τ2 τ3 idleidle

( )3

2

1

0tt ttt tt3 t4t2t1

At time t t t e t a context switch is performedAt time t1, t2, t3, e t4 a context switch is performed.

Each interval [ti, ti+1) is called a time slice.Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 33

A ti h d lA preemptive schedule

τ1

τ2

τ3

σ(t)

τ3

3

2

1

0 t


Definitions• A schedule σ is said to be feasible if all

the tasks are able to complete within athe tasks are able to complete within aset of constraints.

• A set of tasks Γ is said to beh d l bl if th i t f iblschedulable if there exists a feasible

schedule for it.


Types of constraints• Timing constraints

– activation, completion, jitter., p , j

• Precedence constraints– they impose an ordering in the execution.

R t i t• Resource constraints– they enforce a synchronization in the

access of mutually exclusive resources.


Precedence graphPrecedence graph

acq1 acq2

edge1 edge2

shapedisp pp

d thdepth

rec


Resource constraintsTo preserve data consistency, shared resourcesmust be accessed in mutual exclusion:

x = 3τ τx 3y = 5

τW τRx = 1y = 8

x = 1y = 5

τWx=1

y

y=8

τRread


Mutual exclusionHowever, mutual exclusion introduces extra delays:

x = 3y = 5x = 1 x = 1

τW τRyx 1y = 8

x 1y = 8

τWx = 1 y = 8

τR

Δ

read


Δ

Timing constraintsCan be explicit or implicit.

E li it t i t• Explicit constraints– Are included in the specification of the

system activities.

E amplesExamples– open the valve in 10 seconds– send the position within 40 ms– read the altimeter every 200 ms


read the altimeter every 200 ms

Real-Time tasksDi

tτi

Ci

l ti ( i l ti )

ri si fi dit

ri release time (arrival time ai )si start timeCi worst-case execution time (wcet)di absolute deadlineDi relative deadlinefi finishing time


i g

Other parameters

tτi

ci(t) slack

ri si fi dit

f d

t

Lateness: Li = fi − di

Tardiness: max(0 L )Tardiness: max(0, Li)

Residual wcet: ci(t) ci(ri) = Cii( ) i( i) i

Laxity (o slack): di − t − ci(t)


JitterJitterIt is the time variation of a periodic event:It is the time variation of a periodic event:

Finishing-time JitterFinishing time Jitter

fi,1

τifi,2 fi,3

Absolute: max (fi,k – ri,k) – min (fi,k – ri,k)k kk k

Relative: max | (fi,k – ri,k) – (fi,k-1 – ri,k-1) |k


Other types of JitterOther types of JitterStart-time Jitter

si 1

τi

si 2 si 3si,1 si,2 si,3

Completion-time Jitter (I/O jitter)Completion time Jitter (I/O jitter)

τi

si,1

τi

si,2 si,3fi,2fi,1 fi,3


Task CriticalityHARD tasks

Task CriticalityHARD tasks

All jobs must meet their deadlines. Missing adeadline may cause catastrophical effects.

SOFT tasksMissing deadlines is not desired but causesgonly a performace degradation.

An operating system able to handle hardtasks is called a hard real-time system.


Typical HARD taskssensory acquisition– sensory acquisition

– low-level controlt l i– sensory-motor planning

T pical SOFT tasksTypical SOFT tasks– reading data from the keyboard– user command interpretation– message displaying– graphical activities


• Implicit constraints– do not appear in the system specification,

but must be respected to meet the requirements.

Example

What’s the time validity of a sensory data?What s the time validity of a sensory data?

t0 ?Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 47

0

Example: automatic breaking

obstaclev

Dsensor visibility

DashboardControls BRAKEShuman Distribution

Unit

di iemergency

conditionchecker

sensors stop


Worst case reasoningTacq.

Worst-case reasoningTs

acq.task

T Δ TTs Δ Tb

v

obstacle in obstacle brake train

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 49the field detected pressed stopped

D i ibiliD = sensor visibility

( )v(Ts + Δ) + Xb < D

a = μ g2

2

21 atvtX b −=

gvX b μ

=2

22v = a t

gμ2

2

Dg

vTv s <+Δ+μ2

)(2


gμ

Δ−−<vDTs 2 gv μ2

TmaxggDgv μΔ−μ+μΔ= 2)( 2

max ggDgv μΔμ+μΔ 2)(max

D2

T

gDv μ≅ 2max

dv

Ts

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 51speedvmaxv

Example 2: contour followingExample 2: contour following

v

F

GoalGoalMove at velocity v along the surfacet t ti f F F ltangent, exerting a force F < Fmax alongits normal direction.


Worst-case reasoninggv

acq.task

F(t-1) F(t) F(t+1)

Ts

task

Ts τdv

v = v0 e–(t/τd)

force notd d

trajectorydifi d

robotd


detected modified stopped

Lenght covered by the robot after the contact:Lenght covered by the robot after the contact:

L = vT + xL = vTs + xf

t dd τ 0/ )()( ∞∞∞

∫∫ ddt

f veevdtevdttvx d τττ0

000

/00

)()( =−−=== ∞−−∫∫L = v(Ts + τd)

Force on the robot tool: (K = elastic coefficient)

F = KL = v(Ts + τd) < Fmax


Condition on the sampling period:

FT τ−< maxds Kv

T τ<0

TTmax

⎟⎟⎞

⎜⎜⎛

−= dFT τmax

max ⎟⎠

⎜⎝

dKv0max

F

T dKFv

τmax

max =

speedvv0

Ts


speedvmaxv0

The generalThe generalscheduling problemscheduling problem

Given a set Γ of n tasks, a set P of m processors, anda set R of r resources, find an assignment of P and Rto Γ which produces a feasible schedule.

SchedulingΓ

Schedulingalgorithm

RP σ

feasibleGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 56

R

Complexity

• In 1975, Garey and Johnson showed thatthe general scheduling problem is NP hard.

H l i l ti l ith b• However, polynomial time algorithms can befound under particular conditions.


ComplexityComplexity

It’s important to find polynomial time algorithms.

number of tasks n = 30elementary step = 1μs

• Alg 1: O(n)

y p μ

30 μs• Alg. 1: O(n)• Alg. 2: O(n6)

30 μs12 min

• Alg. 3: O(6n) 7 billions of years


Simplifying assumptions

• Single processor

• Omogeneous task sets

F ll ti t k• Fully preemptive tasks

• Simultanoeus activations• Simultanoeus activations

• No precedence constraintsp

• No resource constraints


Periodic TaskPeriodic Task S h d liScheduling

Problem formulationτi (Ci, Ti) job τik

rik dik

For each periodic task, guarantee that:

ik ik

• each job τik is activated at rik = (k−1)Ti

h j b l t ithi d + D• each job τik completes within dik = rik + Di


Ti li S h d liTimeline Scheduling(cyclic scheduling)(cyclic scheduling)

It has been used for 30 years in militaryIt has been used for 30 years in militarysystems, navigation, and monitoring systems.

Examples– Air traffic control

– Space Shuttle

– Boeing 777


Timeline Scheduling

• The time axis is divided in intervals of equal

Method• The time axis is divided in intervals of equal

length (time slots).

• Each task is statically allocated in a slot inorder to meet the desired request rate.

• The execution in each slot is activated by atimer.


Examplep

40 H 25 msf T

A

task

Δ GCD40 Hz

20 Hz

25 ms

50 ms

A

BΔ = GCD (minor cycle)

T = lcm (major cycle)10 Hz 100 msC

TΔ TΔ

0 25 50 75 100 125 150 175 200

C C ≤ ΔCA + CB ≤ ΔCA + CC ≤ Δ

Guarantee:


Implementationptimer

AB

minorcycle

AC

timer

majorC

Atimer

majorcycle

AB

iA

timer


Timeline schedulingAdvantages

• Simple implementation (no real-timeoperating system is required)operating system is required).

• Low run-time overhead.Low run time overhead.

• It allows jitter control.


Timeline schedulingDisadvantages

• It is not robust during overloads.

• It is difficult to expand the schedule.

• It is not easy to handle aperiodic activities.


Problems during overloadsWhat do we do during task overruns?

• Let the task continue– we can have a domino effect on all the otherwe can have a domino effect on all the other

tasks (timeline break)

Abort the task• Abort the task– the system can remain in inconsistent states.


ExpandibilityIf one or more tasks need to be upgraded,we may have to re-design the wholee ay a e to e des g t e o eschedule again.

Example: B is updated but CA + CB > Δ

ΔΔ

A B0 25

A B


Expandibility• We have to split task B in two subtasks

(B1 B2) and re-build the schedule:(B1, B2) and re build the schedule:

0 25 50 75 100

B1 B1B2 B2A A A AC• • •

0 25 50 75 100

C + C ≤ ΔCA + CB1 ≤ ΔCA + CB2 + CC ≤ Δ

Guarantee:


ExpandibilityExpandibilityIf the frequency of some task is changedIf the frequency of some task is changed,the impact can be even more significant:

25 ms 25 msT T

A

task

50 ms

100 ms

40 ms

100 ms

B

C 100 ms 100 msC

before after

Δ = 25 Δ = 5T = 100 T = 200

minor cycle:major cycle:

40 sync.per cycle!


j y

E lExample

TΔ

0 25 50 75 100 125 150 175 200

Δ

0 25 50 75 100 125 150 175 200

T


Priority Scheduling

Each task is assigned a priority based on its

Method• Each task is assigned a priority based on its

timing constraints.

• We verify the feasibility of the schedule usinganalytical techniques.y q

• Tasks are executed on a priority-basedkernelkernel.


Priority AssignmentsPriority AssignmentsTiτi (Ci , Ti , Di ) Ti

Ci

τi (Ci , i , i )

ri,k ri,k+1 tri,1 = 0

• Rate Monotonic (RM): Di = Ti

pi ∝ 1/Ti (static)

E li t D dli Fi t (EDF)• Earliest Deadline First (EDF):pi ∝ 1/di (dynamic) di,k = ri,k + Di


i,k i,k i

R t M t i (RM)Rate Monotonic (RM)Each task is assigned a fixed priority• Each task is assigned a fixed priorityproportional to its rate.

τA500 10025 75

τB0

τB40 80

0τC

100


How can we verify feasibility?• Each task uses the processor for a fraction of

time: C

i

ii T

CU =

• Hence the total processor utilization is:

∑=

=n

i i

ip T

CU1=i i1

• Up is a misure of the processor loadGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 76

A necessary condition

If Up > 1 the processor is overloaded hencep pthe task set cannot be schedulable.

However, there are cases in which Up < 1but the task is not schedulable by RM.


An unfeasible RM schedule

944.094

63

=+=pU96

6 120 183 9 15τ1

0 9 183 6 12 15τ2

0 9 183 6 12 15

deadline miss


Utilization upper boundUtilization upper bound33 833.093

63

=+=pU

τ16 120 183 9 15

τ20 9 183 6 12 15

τ2

NOTE: If C1 or C2 is increased,τ2 will miss its deadline!


A diff t b dA different upper bound

184

42

=+=pU84

τ14 120 8 16

τ1

0τ2

4 128 16

The upper bound Uub depends on thespecific task set.


spec c tas set

The least upper bound

1

Uub

1

Ulub

. . .

ΓGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 81

Γ

A sufficient conditionA sufficient condition

If Up ≤ Ulub the task set is certainlyh d l bl ith th RM l ithschedulable with the RM algorithm.

NOTEIf Ulub < Up ≤ 1 we cannot say anything

NOTE

about the feasibility of that task set.


Basic results

A tiIndependent tasks

Assumptions:Di = TiΦi = 0

In 1973, Liu & Layland proved that a set of nperiodic tasks can be feasibly scheduled

( )121≤∑ nn

iCunder RM

p y

if ( )121

−≤∑=

n

i i

i nT

under RM if

if and only ifunder EDF 11

≤∑n

i i

i

TC


1=i iT

RM b d f lRM bound for large n

( )( )12 /1lub −= nRM nU

for n → ∞ Ulub → ln 2


Schedulability boundSchedulability boundRM EDF

CPU%RM EDF

8090

100

506070 69%

304050

01020

nGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 85

1 2 3 4 5 6 7 8 9 10 n

A special caseA special case

If tasks have harmonic periods Ulub = 1.

184

42

=+=pU84p

4 120 8 16τ1

0τ2

4 128 16


0 4 128 16

Schedulability regiony g

1U1 The U-space

11

1≤∑

=

n

iiU

0.83

)12( /1 −≤∑ nn

i nU

1=i

)(1

∑=i

i

RM

EDF

UGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 87

U210.83


1U1 The U-space

1Ci Ti

0.83 τ1

τ2

3

4

6

9

94.043=+=U

1/2

RM

EDF94.0

96+pU


U210.834/9

Schedule

τ16 120 183 9 15

τ1

EDF

0 9 183 6 12 15τ2

τ1

RM 6 120 183 9 15τ1

τ0 9 183 6 12 15

deadline miss

τ2


deadline miss

RM OptimalityRM OptimalityRM is optimal among all fixed priorityRM is optimal among all fixed priorityalgorithms:

If there exists a fixed priority assignmentwhich leads to a feasible schedule for Γ,,then the RM assignment is feasible for Γ.

If Γ is not schedulable by RM then itIf Γ is not schedulable by RM, then itcannot be scheduled by any fixed priorityassignment


assignment.

EDF OptimalityEDF Optimality

EDF is optimal among all algorithms:

If there exists a feasible schedule for Γ,th EDF ill t f ibl h d lthen EDF will generate a feasible schedule.

If Γ is not schedulable by EDF, then itcannot be scheduled by any algorithm.


Critical InstantFor any task τi, the longest response time occurs when itarrives together with all higher priority tasksarrives together with all higher priority tasks.

τ1τ1

τ2

R2

τ1

τ2

R2


2

Th H b li B dThe Hyperbolic Bound

• In 2000, Bini et al. proved that a set of nperiodic tasks is schedulable with RM if:pe od c tas s s sc edu ab e t

2)1( ≤+∏n

U 2)1(1

≤+∏=i

iU



1U1 The U-space

11

1≤∑

=

n

iiU

0.83

)12( /1 −≤∑ nn

i nU

1=i

)(1

∑=i

i

RM

EDF


U210.83


1U1 The U-space

11

1≤∑

=

n

iiU

0.83

)12( /1 −≤∑ nn

i nU

1=i

)(1

∑=i

i

∏n

2)1(1

≤+∏=i

iU

RM

EDF


U210.83

E t i t t k ith D TExtension to tasks with D < TTi

Di

Ti

Ciτi

ri,k di,k tri,k+1

• Deadline Monotonic: p ∝ 1/D (static)

Scheduling algorithms• Deadline Monotonic: pi ∝ 1/Di (static)

• Earliest Deadline First: pi ∝ 1/di (dynamic)


Deadline MonotonicDeadline Monotonic

τ1

τ20 4 8 12 16 20 24 280 4 8 12 16 20 24 28

Problem with the Utilization Bound

116.163

32

>=+== ∑n

ip D

CU631

∑=i i

p D

but the task set is schedulableGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 97

but the task set is schedulable.

How to guarantee feasibility?How to guarantee feasibility?Ti

Di

Ti

Ciτi

ri,k di,k tri,k+1

• Fixed priority: Response Time Analysis (RTA)

• EDF: Processor Demand Criterion (PDC)


Response Time Analysisp y[Audsley ‘90]

• For each task τi compute the interferencedue to higher priority tasks:due to higher priority tasks:

∑= ki CI

• compute its response time as

∑< ik DD

ki

• compute its response time asRi = Ci + Ii

• verify if Ri ≤ Di


Computing the interferenceComputing the interferenceτkτk

0 Ri

τi

Interference of τk on τiin the interval [0 R ]: k

iik C

TRI =in the interval [0, Ri]: k

kik T

1Interference of highpriority tasks on τi: k

ii

i CTRI ∑

−

=1

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 100kk T=1

Computing the response timep g pi R−1

kk

i

kii C

TRCR ∑

=

+=1

Iterative solution:Iterative solution:

CR0

si

i R )1(1 −−

∑ii CR =

iterate until)1( −> ss RR

kk

i

ki

si C

TRCR

1=∑+=

)1(> si

si RR


Processor Demand CriterionProcessor Demand Criterion[Baruah, Howell, Rosier 1990][ ]

I i t l f ti th t tiIn any interval of time, the computationdemanded by the task set must be no greaterthan the available time.

)(),(,0, 122121 ttttgtt −≤>∀ )(),(,0, 122121 ttttgtt ≤>∀


Processor DemandProcessor Demand

t1 t2

Th d d i [t t ] i th t ti ti fThe demand in [t1, t2] is the computation time ofthose jobs started at or after t1 with deadline lessth l t t

≤td

than or equal to t2:

∑≤

=2

),( 21

td

i

i

CttgGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 103

∑≥ 1tri

Processor DemandFor synchronous task sets we can only analyze intervals [0,L]

τi

0 L

g(0, L) ∑ +−=

n

ii

i

ii CT

TDL1

g(0, L)=i iT1

LGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 104

LDi Ti + Di 2Ti + Di 3Ti + Di

P D d TProcessor Demand Test

TDLn + LCT

TDLLn

ii

ii ≤+−

>∀ ∑1

0Ti i=1

Question

How can we bound the number of intervals inwhich the test has to be performed?


ExampleExampleτ1

τ

1

τ20 2 6 124 8 10 14 16

8

g(0, L) L

4

6

0

2

LGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 106

Bounding complexityBounding complexity• Since g(0,L) is a step function, we can checkSince g(0,L) is a step function, we can check

feasibility only at deadline points.

• If tasks are synchronous and Up < 1, we cancheck feasiblity up to the hyperperiod H:check feasiblity up to the hyperperiod H:

H = lcm(T1, … , Tn)Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 107

1 n

Bounding complexityg p y• Moreover we note that: g(0, L) ≤ G(0, L)g( ) ( )

∑ ⎟⎞

⎜⎛ −+n

ii CDTLLG )0( ∑=

⎟⎟⎠

⎜⎜⎝

=i

ii

ii CT

LG1

),0(

in

ii

ni

TCDT

TCL ∑∑ −+= )(

iiii

i i TT ∑∑== 11

n

∑=

−+=n

iiii UDTLU

1)(


Limiting LLimiting Ln

G(0, L)∑

=

−+=n

iiii UDTLULG

1)(),0( L

g(0, L)

( , )

UDTL

n

iiii −

=∑

=

)(1*

UL

−=

1

for L > L*

g(0 L) ≤ G(0 L) < LL

L*

g(0,L) ≤ G(0,L) < L


L

Processor Demand Test

A set of n periodic tasks with D ≤ T is schedulable by

TDLn +−∑

p yEDF if and only if

LCT

TDLLi

ii

ii ≤+

>∀ ∑=1

0U < 1 AND

D = {dk | dk ≤ min (H, L* )}

H = lcm(T1, … , Tn)n

U

UDTL

n

iiii −

=∑

=

1

)(1*


U−1

Summarizing: RM vs. EDFgDi = Ti Di ≤ Ti

Σpseudo-polynomialSuff.: polynomial O(n)Response Time Analysis

RMLL: ΣUi ≤ n(21/n –1)

HB: Π(Ui+1) ≤ 2∀i Ri ≤ Di

1

Response Time Analysis

(

kk

ii

kii C

TRCR ∑

−

=

+=1

1RTAExact pseudo-polynomial

O(n) pseudo-polynomialpolynomial:

RTA

P D d A l iEDFΣUi ≤ 1 LLgL ≤>∀ ),0(,0

( )p y Processor Demand Analysis


QuestionsQuestions• If EDF is more efficient than RM, whyIf EDF is more efficient than RM, why

commercial RT systems are still based on RM?

Main reason

• RM is simpler to implement on top ofcommercial (fixed priority) kernels.( p y)

• EDF requires explicit kernel support for deadlineh d li b t i th d tscheduling, but gives other advantages.


Advantages of EDFAdvantages of EDFH EDF ff th f ll i d tHowever, EDF offers the following advantageswith respect to RM:

• Less overhaed due to preemptions;

• More flexible behavior in overload situations;

More uniform jitter control;• More uniform jitter control;

• Better aperiodic responsiveness.Better aperiodic responsiveness.


Handling shared gresources

Problems caused byProblems caused bymutual exclusion

C i i l iCritical sections τ2τ1 τ2τ1

globlalgmemory buffer

write read3; 1i

wait(s) wait(s)write readx = 3;

y = 5;a = x+1;b = y+2;

int x;int y;

c = x+y;signal(s)

signal(s)signal(s)


Blocking on a semaphoreBlocking on a semaphore

τ1 τ2

p1 > p2Δ1 2

τ1

CS CS τ2

It seems that the maximum blockingtime for τ1 is equal to the length of thecritical section of τ2, but …


S h d l ith fli tSchedule with no conflicts

τpriority

τ1

τ2

τ3


C fli t iti l tiConflict on a critical section

priority B

ττ1

τ2

τ3


Priority Inversion

A high priority task is blocked by a lowerA high priority task is blocked by a lower-priority task a for an unbounded interval oftimetime.

SolutionIntroduce a concurrency control protocol for t oduce a co cu e cy co t o p otoco oaccessing critical sections.


Resource Access Protocols

Under fixed priorities• Non Preemptive Protocol (NPP)• Highest Locker Priority (HLP)• Priority Inheritance Protocol (PIP)• Priority Ceiling Protocol (PCP)y g ( )

Under EDF• Stack Resource Policy (SRP)


Non Preemptive Protocol• Preemption is forbidden in critical sections.

I l t ti h t k t CS it• Implementation: when a task enters a CS, its priority is increased at the maximum value.

ADVANTAGES i li it

PROBLEMS hi h i it t k th t d

ADVANTAGES: simplicity

PROBLEMS: high priority tasks that donot use CS may also block


C fli t iti l tiConflict on critical section

priority B

τ1

τ2

τ3


S h d l ith NPPSchedule with NPP

priority

τ1

τ2

τ3

PCS = max{P1, … Pn}Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 124

CS { 1, n}

P bl ith NPPProblem with NPP

priority uselessblockingτ1blocking

τ2

τ3

τ1 cannot preemt, although it couldGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 125

Highest Locker Priority

A task in a CS gets the highest priorityamong the tasks that use it.

FEATURES:

• Simple implementation.

• A task is blocked when attempting to preempt, p g p p ,not when entering the CS.


S h d l ith HLPSchedule with HLPprioritypriority

τ1

τ2

τ3

PCS = max {Pk | τk uses CS}

τ2 is blocked, but τ1 can preempt within a CS

CS { k | k }


2 , 1 p p

Problem with HLP

τ1 τ2 τ1 blocks just in case ...

test τ1

CS CS

1

τ2τ2

p1p2


Priority Inheritance Protocol[Sha Rajkumar Lehoczky 90][Sha, Rajkumar, Lehoczky, 90]

• A task in a CS increases its priority only if itblocks other tasks.

• A task in a CS inherits the highest priorityamong those tasks it blocksamong those tasks it blocks.

PCS = max {Pk | τk blocked on CS}


S h d l ith PIPSchedule with PIPpriority

τ1

direct blockingτ1

τpush-through blocking

τ2

τ3

p1

p3


p3

Types of blockingyp g• Direct blockingect b oc g

A task blocks on a locked semaphore

• Push-through blockingA task blocks because a lower priority task inherited a higher priority.

BLOCKING:BLOCKING:a delay caused by a lower priority task


Identifying blocking resourcesy g g• A task τi can be blocked by those

semaphores used by lower priority tasks and• directly shared with τi (direct blocking) ordirectly shared with τi (direct blocking) or

• shared with tasks having priority higher than τi(push-through blocking)(push through blocking).

Theorem: τi can be blocked at most onceTheorem: τi can be blocked at most onceby each of such semaphores

Theorem: τi can be blocked at most onceby each lower priority task


by each lower priority task

B di bl ki iBounding blocking times• If n is the number of tasks with priority less

than τii

• and m is the number of semaphores onwhich τ can be blocked thenwhich τi can be blocked, then

Theorem: τi can be blocked at most forthe duration of min(n m) criticalthe duration of min(n,m) criticalsections


E lExamplepriority

τ1

τ

A B C

τ2

τ3 B D A

A DC

τ3

• τ can be blocked once by τ (on A or C ) and

B D A

• τ1 can be blocked once by τ2 (on A2 or C2) andonce by τ3 (on A3 or B3)

• τ2 can be blocked once by τ3 (on A3, B3 or D3)

• τ cannot be blockedGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 134

• τ3 cannot be blocked

E lExamplepriority

τ1

τ

A B C

τ2

τ3 B D A

A DC

• B = δ(C ) + δ(B )

τ3 B D A

• B1 = δ(C2) + δ(B3)

• B2 = δ(D3)2 ( 3)

• B3 = 0


S h d l ith PIPSchedule with PIPpriority

τ1τ1

τP1

τ2

P2τ3P2

τ4


R k PIPRemarks on PIPADVANTAGES• It is transparent to the programmer• It is transparent to the programmer.

• It bounds priority inversion.

PROBLEMSIt does not avoid deadlocks and• It does not avoid deadlocks andchained blocking.


Chained blocking with PIPChained blocking with PIPpriority B B BB1

τ1

B2 B3

τ2

τ3

τ4

Theorem: τi can be blocked at most onceby each lower priority task


y p y

Priority Ceiling Protocol

• Can be viewed as PIP + access test.

• A task can enter a CS only if it is free and there is no risk of chained blocking.g

To prevent chained blocking, a task may stop at the entrance of a free CS (ceiling blocking)the entrance of a free CS (ceiling blocking).


Resource Ceilings

• Each semaphore sk is assigned a ceiling:

C(sk) = max {Pj : τj uses sk}

A t k t CS l if

{ ( ) }

• A task τi can enter a CS only if

Pi > max {C(sk) : sk locked by tasks ≠ τi}


Schedule with PCPSchedule with PCPs1 C(s1) = P1

s2 C(s2) = P1priority

τ1

ττ2

ττ3t1

t1: τ2 is blocked by the PCP, since P2 < C(s1)Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 141

R k PCPRemarks on PCPADVANTAGES• Blocking is reduced to only one CS• Blocking is reduced to only one CS

• It prevents deadlocks

PROBLEMSIt is not transparent to the programmer:• It is not transparent to the programmer:semaphores need ceilings


Typical DeadlockTypical Deadlockτ ττ1 τ2

P1 > P2

τ1blocked

1

τ2blocked

A

B

B

A τ2B A


Deadlock avoidance with PCPDeadlock avoidance with PCPτ τ C = Pτ1 τ2

P1 > P2

CA = P1

CB = P1

τ1

ceiling blocking

1

τ2

A

B

B

A τ2B A


G t ithGuarantee with resource constraintsconstraints

• We select a scheduling algorithm and aWe select a scheduling algorithm and aresource access protocol.

• We compute the maximum blocking times(Bi) for each task.

• We perform the guarantee test including thebl ki tblocking terms.


G t ith RMGuarantee with RM (D = T)

tipreemptionby HP tasks

ττi

blocking byLP tasksBy LL test:

( )1211

−≤+

+∀ ∑−

/iiii

k iBCCi ( )1

∑= ik k

iTT

i


G t ith RMGuarantee with RM (D ≤ T)

tipreemptionby HP tasks

ττi

blocking byLP tasks

∀i Ri ≤ DiBy RTA test:

ii R∑−1

kk

i

kiii C

TRBCR ∑

=

++=1


Stack Resource Policy [Baker 1990]Stack Resource Policy [Baker 1990]

• It works both with fixed and dynamic prioritypriority

• It limits blocking to 1 critical section

• It prevents deadlock

• It supports multi-unit resources

• It allows stack sharing• It allows stack sharing

• It is easy to implementGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 148

y p

Stack Resource Policy [Baker 90]y [ ]

• For each resource Rk: Nk

⇒ Maximum units: Nk

⇒ Available units: nk

Rk⇒ Available units: nk nk

• For each task τ the system keeps:• For each task τi the system keeps:

⇒ its resource requirements: μi(Rk)

⇒ a priority pi: ii Tp 1∝ ii dp 1∝RM EDFp y pi

⇒ a static preemption level: ii D1∝π


p p ii

Stack Resource Policy [Baker 90]

Resource ceiling

)(:max)( kjkjjkk RnnC μπ <=

System ceiling { })(max kk nC=ΠSystem ceiling { })(max kkks nCΠ

SRP Rule

A job cannot preempt untilA job cannot preempt untilpi is the highest and πi > Πs


ExampleExampleπ

τ1

πi

3

τ22

τ3

Π

1

Πs

123

t01


SRP: NotesSRP: Notes• Blocking always occurs at preemption• Blocking always occurs at preemption

time

• A task never blocks on a wait primitive(semaphore queues are not needed)(semaphore queues are not needed)

• Semaphores are still needed to update• Semaphores are still needed to updatethe system ceiling

• Early blocking allows stack sharing


EDF G t (D T )EDF Guarantee (Di = Ti)tipreemption

by HP tasksττi

blocking byLP tasks

11

≤+

+∀ ∑−

iii

k BCCi1

∑= ik k TT

i


EDF Guarantee: PD test (Di ≤ Ti )( i i )

τ1.

τi

..

τi

τkτk

τnn

Tasks are ordered by decreasing preemption levelGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 154

Tasks are ordered by decreasing preemption level

Schedulability Analysis y yunder EDF

When Di ≤ Ti

A task set is schedulable if U < 1 and ∀L ∈ D

DTLnkk −+∑ LC

TDTLB

kk

k

kki ≤

++ ∑

=1

∀i

where D = {dk | dk ≤ min (H, L* )}e e D {dk | dk ≤ min (H, L )}

H l (T T )UDT

L

n

iiii −∑

=

)(1*H = lcm(T1, … , Tn) U

L i

−= =

11

Stack SharinggEach task normally uses a private stack for

• saving context (register values)• managing functionsmanaging functions• storing local variables

k iPUSH

stack pointer

POP

t kstack

Stack SharinggWhy stack cannot be normally shared?

Suppose tasks share a resource: A

SP1blocked

big problems

τ1

SP1

τ2SP2

stack

Stack SharinggWhy stack can be shared under SRP?

SP1τ1

SP2

SP2

stack

τ2

stack

Saving Stack SizegTo really save stack size, we should use a small number of preemption levels.

100 tasks

10 Kb stack per taskstack size = 1 Mb

10 Kb stack per task

10 preemption levels

10 tasks per groupstack size = 100 Kb

10 tasks per groupstack saving = 90 %

NOTE on SRPSRP for fixed priorities and single-unit resourcesis equivalent to Higher Locker Priorityis equivalent to Higher Locker Priority.

It is also referred to as Immediate Priority Ceilingy g

τ1 A

τ2 BA

τ3 B B

Πsπ3

π2

π1

Non-preemtive schedulingp gIt is a special case of preemptive scheduling whereall tasks share a single resource for their entireall tasks share a single resource for their entireduration.

τ1 R

τ2

τR

τ3 R

The max blocking time for task τi is given by theThe max blocking time for task τi is given by thelargest Ck among the lowest priority tasks:

{C }Bi = max{Ck : Pk < Pi}

Advantages of NP scheduling• Reduces runtime overhead

Less context switches

No semaphores are needed for critical sections

• Reduces stack size, since no more than one taskb i tican be in execution.

• Preserves program locality improving the• Preserves program locality, improving theeffectiveness of

Cache memory

Pipeline mechanisms

Prefetch queues

Advantages of NP scheduling

• As a consequence task execution times are


• As a consequence, task execution times areSmaller

More predictable (less variable)

non-preemptive

preemptive

Cmin C


97042≅+U

In fixed priority systems can improve schedulabiilty:

τ1

RM 97.075

≅+=U

τ1

τ2

100 205 15 25 30 35

τ20 217 14 28 35

deadline miss

τ1

NP-RMdeadline miss

τ1

τ2

100 205 15 25 30 35

τ20 217 14 28 35

Disadvantages of NP scheduling• In general, NP scheduling reduces schedulability.

• The utilization bound under non preemptivescheduling drops to zero:

C1 = ε

scheduling drops to zero:

τ1

τ2 ∞T1

1

τ2 ∞T2C2 = T1

U = ε

T+

C2 0T1 ∞

Non preemptive scheduling anomaliesp p g

τ1τ1

τ2

τ3

deadline missdouble speed

τ1

ττ2

τ33

Trade-off solutionsPreemption thresholdsEach task has two priorities:

• Nominal priority (ready priority): used to enqueuep y ( y p y) qthe task in the ready queue

• Threshold priority: used for task executionThreshold priority: used for task execution

nominal priority ≤ threshold prioritynominal priority ≤ threshold priority

thresholdi lnominal

Trade-off solutionsDeferred preemptionEach task can defer preemption up to qEach task can defer preemption up to qi

NP regions are floating in the code

q2

q3 Bi = max {qk}i {qk}k>i

Trade-off solutionsFixed preemption pointsA task can only be preempted in fixed pointsA task can only be preempted in fixed points

and it is divided in mi chunks: qi,1 ... qi,mi

Bi = max {qkmax}Bi max {qk }

k>i

Interesting problemInteresting problem

Given a preemptively feasible task set, reduceGiven a preemptively feasible task set, reducepreemptions as much as possible still preservingschedulability.schedulability.

Reducing context switch costs and WCETs

This means finding the longest non-preemtivechunk for each task that can still preservechunk for each task that can still preserveschedulability.

U d EDF B h ECRTS 2005Under EDF

Under Fix. Pr. Yao et. al. - RTCSA 2009

Baruah - ECRTS 2005

H dli A i di T kHandling Aperiodic Tasks

Handling CriticalityHandling CriticalityA i di t k ith HARD d dli t b• Aperiodic tasks with HARD deadlines must beguaranteed under worst-case conditions.

• Off-line guarantee is only possible if we canbound interarrival times (sporadic tasks).

• Hence sporadic tasks can be guaranteed asperiodic tasks with Ci = WCETi and Ti = MITip i i i i

WCET = Worst-Case Execution TimeMIT = Minimum Interarrival Time


SOFT aperiodic tasks• Aperiodic tasks with SOFT deadlines should

be executed as soon as possible butbe executed as soon as possible, butwithout jeopardizing HARD tasks.

• We may be interested in

→ minimizing the average response time→ minimizing the average response time

→ performing an on-line guarantee


P i di S h d liPeriodic Scheduling(EDF)(EDF)

τC1 = 1

τ14 8

C2 = 3τ2

30 126

2

ape

0 4 8 1262 10


Immediate service

τC1 = 1

τ14 8

C2 = 3τ2

30 126

2

deadline missape

0 4 8 1262 10

deadline miss

Response Time = 3


Background service

τC1 = 1

τ14 8

C2 = 3τ2

30 126

2

ape

0 4 8 1262 10

Response Time = 10


Aperiodic ServersAperiodic Servers• A server is a kernel activity aimed at controlling• A server is a kernel activity aimed at controlling

the execution of aperiodic tasks.• Normally, a server is a periodic task having two

parameters:

Cs capacity (or budget)Ts server period

To preserve periodic tasks, no more than Csunits must be executed every period Ts


units must be executed every period Ts

A i di iAperiodic service queue

Service queueServer

aperiodicSOFT tasks

Service queue

periodic/sporadicHARD tasks CPU

READY queueHARD tasks CPU

• The server is scheduled as any periodic task.• Priority ties are broken in favor of the server• Priority ties are broken in favor of the server.• Aperiodic tasks can be selected using an arbitrary

queueing disciplineGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 178

queueing discipline.

Fixed-priority Servers

• Polling Server

• Deferrable Server

• Sporadic Server

• Slack Stealer


Dynamic-priority Servers

• Dynamic Polling Server

• Dynamic Sporadic Server

• Total Bandwidth Server

• Tunable Bandwidth Server

Constant Bandwidth Server• Constant Bandwidth Server


P lli S (PS)Polling Server (PS)• At the beginning of each period, the budget is

recharged at its maximum value.

• Budget is consumed during job execution.

• When the server becomes active and there areno pending jobs C is discharged to zerono pending jobs, Cs is discharged to zero.

• When the server becomes active and there arepending jobs, they are served until Cs > 0.


RM + Polling ServerRM Polling Serverτ

C1 = 2τ1

4 8C2 = 1

τ220 126

ape

0 4 8 1262 10PSPS

Cs = 1Ts = 5

0 5 10

Response Time = 8


PS propertiesPS propertiesI th t th PS b h i di• In the worst-case, the PS behaves as a periodictask with utilization Us = Cs/Ts .

• Aperiodic tasks execute at the highest priority ifTs = min(T1, … , Tn).s ( 1, , n)

• Liu & Layland analysis gives that:

⎤⎡ ⎞⎛1

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡−⎟⎟

⎠

⎞⎜⎜⎝

⎛+

+=+ 11

2)(lub

n

ss

PSRM

UnUnU

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 183⎦⎣ ⎠⎝ s

RM + PS schedulabilityRM + PS schedulability⎟⎞

⎜⎛+ 2l)(PSRM UU

1⎟⎟⎠

⎞⎜⎜⎝

⎛+

+=∞→+

1ln)(lub

ss

PSRM

UUnU

ln2ln2

)1()( /1lub −+=+ n

sPSRM KnUnU )()(lub s

2=K

Us1+sU

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 1840 1

Deferrable Server (DS)Deferrable Server (DS)I i il t th PS b t th b d t i t• Is similar to the PS, but the budget is notdischarged if there are no pending requests.

• Keeping the budget improves responsiveness,but decreases the utilization bound.

ape

0 4 8 1262 100 4 8 1262 10DS

Cs = 1T = 4

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 1850 4 8

Ts 4

RM + D f bl SRM + Deferrable ServerC = 2

τ14 8

C1 = 2

τ2

4

0

8

126

C2 = 1

ape20 126 1

0 4 8 1262 10DS

Cs = 1

0 5 10Ts = 5

Response Time = 4Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 186

Response Time = 4

Analysis of RM + DSAnalysis of RM + DS

DS Cs Cs

C Ts +Cs 2Ts+Cs

Cs

τ1C1

s s s s

C2T1

τ2C2

T2

⎥⎤

⎢⎡

⎟⎟⎞

⎜⎜⎛ +

++ 12)(1

nsDSRM UUU

⎥⎥

⎦⎢⎢

⎣−⎟⎟

⎠⎜⎜⎝ +

+=+ 112

)(lubs

ss

DSRM

UnUnU


RM + DS schedulabilityRM + DS schedulability)(+U DSRM

1)(lub ∞→+ nU DSRM

ln2PS

ln2DS

)1()( /1++ nPSRM KnUnU )1()(lub −+= s KnUnU

2K 2+sUKUs1+

=s

PS UK

12 +=

s

sDS U

K

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 1880 1

Designing server parametersDesigning server parameters

⎥⎥⎤

⎢⎢⎡

−⎟⎟⎠

⎞⎜⎜⎝

⎛ +≤ 1

122

1n

sp U

UnU• Determine Usmax from

⎥⎦

⎢⎣

⎟⎠

⎜⎝ +12 s

p Us

• Define U ≤ U max• Define Us ≤ Us

D fi T i (T T )• Define Ts = min (T1, …, Tn)

• Compute Cs = UsTs


T t l B d idth S (TBS)Total Bandwidth Server (TBS)• It is a dynamic priority server, used along with

EDF.

• Each aperiodic request is assigned a deadlineso that the server demand does not exceed aso that the server demand does not exceed agiven bandwidth Us .

• Aperiodic jobs are inserted in the ready queueand scheduled together with the HARD tasks.


The TBS mechanismThe TBS mechanismaperiodic Deadlinep

tasksDeadline

assignment

periodic/sporadictasks CPU

READY queue

D dli ti b k i f f th• Deadlines ties are broken in favor of the server.• Periodic tasks are guaranteed if and only if

Up + Us ≤ 1Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 191

Deadline assignment ruleg• Deadline has to be assigned not to jeopardizeDeadline has to be assigned not to jeopardize

periodic tasks.

• A safe relative deadline is equal to theminimum period that can be assigned to a newperiodic task with utilization U :periodic task with utilization Us:

Us = Ck / Tk Tk = dk − rk = Ck / Uss k k k k k k s

• Hence, the absolute deadline can be set as:

dk = rk + Ck / Us


Deadline assignment ruleDeadline assignment ruleC1/Us C2/Us

C1 C2

1 s 2 s

d1 d2r2r1

• To keep track of the bandwidth assigned toprevious jobs dk must be computed as:previous jobs, dk must be computed as:

dk = max (rk , dk-1) + Ck / Us


EDF + TBS scheduleτ1

C1 = 1

τ2

4 8C2 = 3

ape20 1261

0 4 8 1262 10d1 d2r1 r2

Us = 1 − Up = 1/4

d = r + C / U = 1 + 2 4 = 9d1 = r1 + C1 / Us = 1 + 2·4 = 9

d2 = max(r2 , d1) + C2 / Us = 9 + 1·4 = 13Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 194

2 ( 2 1) 2 s

Improving TBSImproving TBS• What’s the minimum deadline that can be

assigned to an aperiodic job?

τ1C1 = 1

τ2

4 8C2 = 3

ape20 126

0 4 8 1262 10d1r1


Improving TBSImproving TBS• If we freeze the schedule and advance d1 to 7,

no task misses its deadline, but the schedule isnot EDF:

τ1C1 = 1

τ2

4 8C2 = 3

ape20 126

0 4 8 1262 10d1r1

Feasible schedule ≠ EDFGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 196

Feasible schedule ≠ EDF

Improving TBSImproving TBS• However, since EDF is optimal, the schedule, p ,

produced by EDF is also feasible:

τ1C1 = 1

τ2

4 8C2 = 3

ape20 126

0 4 8 1262 10d1r1


Improving TBSImproving TBS• We can now apply the same argument, andpp y g ,

advance the deadline to t = 6:

τ1C1 = 1

τ2

4 8C2 = 3

ape20 126

0 4 8 1262 10d1r1


Improving TBSImproving TBS• Clearly, advancing the deadline now does noty, g

produce any enhancement:

τ1C1 = 1

τ2

4 8C2 = 3

ape20 126

0 4 8 1262 10d1r1


Computing the deadlineComputing the deadline• In general, the new deadline has to be set tog ,

the finishing time of the current job:

),max( 01

0−= kkk drd

)(1 skk

sk

sk dffd ==+

ape

dksfk

s


Computing the deadlineComputing the deadlineTh t l fi i hi ti b ti t d• The actual finishing time can be estimatedbased on the periodic interference:

),( skkk

sk drICf += ),( kkpkk drICf +

apeCk

dksfk

sIp


Periodic InterferenceUp = 1/2 + 1/3 = 5/6 Ck = 2

Us = 1 − Up = 1/6 dk = 3 + 2/ Us = 15

τ14 8 12 16 200

τ2

20 6 12 18

ape2

dk3

),(),(),( skf

ska

skp dtIdtIdtI +=

k


Computing interferenceComputing interferenceττ1

τ4 8 12 16 200

τ2

ape2

0 6 12 18

dk

ape

3

∑=active

iska

i

tcdtIτ

)(),( nexti(t) = next release time of task τi after t

i

∑ −ni

sks CtnextddtI )()(

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 204∑

=

=i

ii

ikkf C

TdtI

1),(

Computing interferenceComputing interferenceττ1

τ4 8 12 16 200

τ2

ape2

0 6 12 18

dk

ape

3

∑=active

iska

i

tcdtIτ

)(),( nexti(t) = next release time of task τi after t

i

∑ ⎟⎟⎞

⎜⎜⎛ −n

isks CtnextddtI 1)()(

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 205∑

=⎟⎟⎠

⎜⎜⎝

−=i

ii

ikkf C

TdtI

11),(

The Optimal Serverp),max( 0

10 = kkk drd compute the initial),max( 1−kkk drd

s = 0 deadline with TBS

),( skkpk

sk drICf +=

sk

sk fd =+1

advance deadlinekk fd

ss dd +1 sk

sk dd =+1s = s+1 EXIT

apeCk

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 206dksfk

sIp

Tunable Bandwidth Server TB(K)( )K = max number of steps

),max( 01

0−= kkk drd O(1)

)( ss df

s = 0( )

O( )),( skkpk

sk drICf +=

sk

sk fd =+1

O(n)O(Kn)polynomialkk f

ss dd +1+1 EXIT( ) OR ( K)

polynomial

kk dd =s = s+1 EXIT( ) OR (s = K)

Graduate Course on Embedded Control Systems - Pisa 8-12 June 2009 207TB(∞) = TB*TB(0) = TBS

Tuning performance vs. g poverhead

performanceTB*K = ∞

optimal server

K = 0

TBS

overhead


Aperiodic responsivenessp pAvg. Response Time Up = 0.85g espo se e

TB(0)9

10

7

8TB(1)

4

5

6TB(3)

TB(5)

2

3

4 TB(5)TB*

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 90

1


0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Relative Aperiodic Load: ρa/(1-Up)

Problems with the TBSProblems with the TBS• Without a budget management there is no• Without a budget management, there is no

protection against execution overruns.

• If a job executes more than expected, hardtasks could miss their deadlines.

C1 = 1 deadline missτ1

14 8

Us = 1/41

0 4 8 1262 10

overrun


S l ti t l i l tiSolution: temporal isolation• In the presence of overruns, only the faulty task

should be delayed.

• Each task τi should not demand more than itsd l d tili ti (U C /T )declared utilization (Ui = Ci/Ti).

• If a task executes more than expected its• If a task executes more than expected, itspriority should be decreased (i.e., its deadlinepostponed)postponed).


Achieving isolation• Isolation among tasks can be achieved through

a bandwidth reservationa bandwidth reservation.

• Each task is managed by a dedicated serverg yhaving bandwidth Us .

• The server assigns priorities (or deadlines) totasks so that they do not exceed the reservedbandwidth.


Resource ReservationResource Reservation

Resource partition Resource enforcement

10 %20 %

τ1τ4

25 %

τ1

τ2τ3A mechanism that prevents a45 % 25 % • A mechanism that prevents atask to consume more thanits reserved amount.

Each task receives a bandwidth Ui and behaves as it were executing alone on

• If a task executes more, it isdelayed, preserving the

f th th t kbehaves as it were executing alone on a slower processor of speed Ui

resource for the other tasks.

Priorities vs ReservationsPriorities vs. Reservations

τ1τ

τ1 τ2 τ3PrioritizedP1 READY QUEUE

τ2τ3

Access P2

P3

τ1τ2

τ1

τU2

U1

ResourceR ti

50%

30%τ2τ3

τ2τ3

2

U3Reservation 30%

20%

Implementation

serverτUs1

serverReady queue

τ1

Us2CPU

EDF

τ2

Us3

server

τ3

U + U + U ≤ 1

server

Us1 + Us2 + Us3 ≤ 1


C B d id h SConstant Bandwidth Server (CBS)(CBS)

• It assigns deadlines to tasks like the TBS but• It assigns deadlines to tasks like the TBS, butkeeps track of job executions through a budgetmechanismmechanism.

• When the budget is exhausted it is immediatelyreplenished, but the deadline is postponed tokeep the demand constant.


CBS tCBS parametersGiven by the user

• Maximum budget: Qsg Qs

• Server period: Ts

U Q / T ( b d idth)Us = Qs / Ts (server bandwidth)

Maintained by the serverMaintained by the server• Current budget: cs (initialized to 0)

• Server deadline: ds (initialized to 0)


B i CBS lBasic CBS rules• Arrival of job J ⇒ assign d• Arrival of job Jk ⇒ assign ds

if (rk + c /U ≤ d ) then recycle (c d )if (rk + cs /Us ≤ ds) then recycle (cs, ds )

else ds = rk + Ts

cs = Qs

• Budget exhausted ⇒ postpone ds

ds = ds + Ts

c = QGraduate Course on Embedded Control Systems - Pisa 8-12 June 2009 218

cs = Qs

Budget exhausted

5

0 12

5

630 12

3cs

Q 3

63

Qs = 3Ts = 6

1

0 123


EDF + CBS h d lEDF + CBS scheduleττ1

τ6 12 18 240

τ2

0 9 2718

d0 d1 d2 d3 d4

ape8 2714

03

1

r1

3

r2

1

r3 24188 2714cs

2418

CBS: Qs = 2, Ts = 6

0 2 4 6 8 10 12 14 16 18 20 22 24 26


CBS tiCBS properties• Bandwidth Isolation

If a task τi is served by a CBS withIf a task τi is served by a CBS withbandwidth Us then, in any interval Δt, τi willnever demand more than Us Δt.never demand more than Us Δt.

• Hard schedulabilityHard schedulabilityA hard task τi (Ci, Ti) is schedulable by a CBS with Q = Ci and T = Ti iff τ isCBS with Qs = Ci and Ts = Ti, iff τi is schedulable by EDF.


Selecting the most suitable service mechanism

performanceoptimal server (TB*)TB(k)

TBSSlack Stealer

CBS

DS

PS

SS

overhead

PS

Background

It depends on the price (overhead) we wantto pay to reduce task response times


to pay to reduce task response times

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