GAURAV MATHUR 319 Howell Avenue, Apt #4

Cincinnati (OH) – 45220 Phone: (513)-652-4052

Email: gaurav.ece1616@gmail.com

Career Objective: Passionate individual with an ambition to pursue a career in VLSI design/architecture/Embedded Systems, possessing a good knowledge of the fields gained through academic courses and projects in VLSI, Embedded Systems, Computer Architecture and individual research. Looking forth to put my honest and sincere efforts to work with an organization where performance is rewarded appropriately with new and challenging tasks, in order to utilize the acquired skill set and add to it while becoming an active contributor towards the growth of the organization.

Work Experience: Jan 2013 - June 2013 Assistant Systems Engineer (Trainee), Tata Consultancy Services Limited (TCSL), India. Responsibilities:

Acquiring and implementing the technical skills in JAVA-J2EE domain, to develop a website for an anonymous Hospital Management System that run on a local server with the help of web designing languages such as HTML, CSS, JSP, JavaScript and handles the day-to-day activities of a hospital under the supervision of a Technical Lead.

Working towards the website development in a small team so as to develop time management, resource management and team dynamics skills.

Developing interpersonal, team, communication and time management skills through group activities, individual and group presentations under the supervision of a Business Lead.

May 2011 - June 2011 Intern, Defense Research and Development Organization (DRDO), India. Responsibilities:

Gaining knowledge about the working of a radiation detector and its underlying principle i.e. the Geiger Muller (G.M.) tube.

Preparing a simulation system for the calibration of Geiger Muller (G.M.) tube radiation detector without exposing the tube to an external non-uniform radiation field using a microcontroller (8051) based circuit.

Academic Projects: Custom IC Design and Testing: 40 pin custom layout for Programmable Interconnect Network was designed

and fabricated (0.5um process) using VHDL, magic layout editor, HSPICE and IRSIM in a LINUX environment to maximize the throughput and frequency. Performed functional and scan chain testing using 16902A Logic Analyzer. The project was a part of Physical VLSI Design coursework.

Placement and Routing Tool: Implemented Force-Directed placement algorithm and Lee’s routing algorithm (2-layer) using C++ to place and route up to 1000 cells and 1000 nets as specified in the benchmark netlists.

Balanced Bi-Partitioning of a net-list (Algorithm-1): Implemented Kernighan-Lee circuit bi-partitioning algorithm with modifications to minimize the cut-set between the partitions. Achieved an optimal cut-set of

2624 for a benchmark netlist of 45000 nodes and 450000 nets within an hour. C++ was used to code the algorithm, to read input netlist file and write output file and a simple makefile was used to compile the program using GNU-GCC compiler.

Balanced Bi-Partitioning of a net-list (Algorithm-2): Implemented Simulated Annealing circuit bi-partitioning algorithm with modifications to minimize the cut-set between the partitions. Achieved an optimal cut-set of 2624 for a benchmark netlist of 45000 nodes and 450000 nets within twenty minutes. Python was used to code the algorithm, to read input netlist file and write output file.

Power estimation and optimization: Performed gate level synthesis, power optimization (using multi-threshold libraries), testing and P n R of a given Greatest Common Divisor (GCD) circuit in Verilog using the Synopsys design flow. Tools used for this project were Synopsys Design Compiler, ICC, Tetramax, DFT Compiler, Power Compiler, Prime Time PX, and BSD.

Low-Power Memory Design and Analysis: Designed a 4 KB (128 X 256) SRAM block using 6-T memory cells and performed read and write operations in it with a word size of 32 bits using magic layout editor, HSPICE and IRSIM.

Power Sources Analysis for an Inverter: Analyzed and reported various power sources for a CMOS inverter i.e. dynamic power, short circuit power, leakage power using the dummy circuit technique.

Energy Recovery Flip-Flop: Implemented PTERF energy recovery flip-flop scheme and compared its power consumption with a conventional D flip-flop.

Capstone Project: Completed a literature survey and critically analyzed various timing closure techniques and presented a report on “Timing Closure in Physical Design Flow”.

Brick Blaster Video Game: Developed using Verilog and C-language on the Altera’s DE-1FPGA board that used a NIOS-II processor. The salient features of the game were the color coding of the bricks, their geometry, menu, screen partition for timing and score which were all implemented using C-language.

Processor: A 9-bit processor implemented at the RTL using Verilog on the Altera’s DE-1FPGA board that performed basic operations using an Arithmetic Logical Unit along with a Finite State Machine.

Education: August 2013 - Present Master of Engineering in Electrical Engineering, University of Cincinnati Current GPA: 3.52 Expected Graduation Date: April 2015 September 2008 - July 2012 Bachelor of Engineering in Electronics & Communication Engineering, Rajasthan Technical University, India Graduation Date: July 2012 Honors: University Graduate Scholarship (UGS) awarded by the University of Cincinnati. Aug 2013

Received the 2nd prize for a paper presentation on Molecular Electronics in an inter-college symposium ‘Embryo’. Mar 2012

Certificate of Credit in Science by the esteemed University of New South Wales, Australia in an All India assessment. July 2005

Brilliant Student Medal by the State Governor. Jan 2003