Weatherspoon Food Desert Vegetable Elasticities - AgEcon Search: Home
Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H...
-
Upload
justina-hardy -
Category
Documents
-
view
213 -
download
0
Transcript of Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H...
![Page 1: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/1.jpg)
Gates and Logic
Hakim WeatherspoonCS 3410, Spring 2012
Computer ScienceCornell Universty
See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)
![Page 2: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/2.jpg)
2
What came was Von Neumann Architecture?
a) The calculatorb) The Bombec) The Colossusd) The ENIACe) All of the above
![Page 3: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/3.jpg)
3
What came was Von Neumann Architecture?
![Page 4: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/4.jpg)
4
A switch
• Acts as a conductor or insulator
• Can be used to build amazing things…
![Page 5: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/5.jpg)
5
Goals for today
To understand how to program, we will build a processor (i.e. a logic circuit)
Logic circuits• Use P- and N-transistors to implement NAND or NOR gates• Use NAND or NOR gates to implement the logic circuits• Build efficient logic circuits
![Page 6: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/6.jpg)
6
Better Switch
• One current controls another (larger) current
• Static Power:– Keeps consuming power
when in the ON state• Dynamic Power:
– Jump in power consumption when switching
![Page 7: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/7.jpg)
7
e
NP
NP
NPN
PN
PNP
NP
ee
e
e
e
e
e
e
e
e
e
e
ehole
Atoms
![Page 8: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/8.jpg)
8
Be
e
e
e Sie
e
e
Silicon PhosphorusBoron
e Pe
e
e
e
Elements
![Page 9: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/9.jpg)
9
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
e Sie
e
e
SiliconSilicon Crystal
![Page 10: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/10.jpg)
10
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
N-Type: Silicon + Phosphorus
e Pe
e
e
e
e Pe
e
e
e
e Pe
e
e
e
e Pe
e
e e
Phosphorus Doping
![Page 11: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/11.jpg)
11
Be
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
ee
e
e
P-Type: Silicon + Boron
Be
e
e
Be
e
e
Be
e
e
Boron Doping
![Page 12: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/12.jpg)
12
Semiconductors
Insulator
n-type (Si+Phosphorus)has mobile electrons:
p-type (Si+Boron)has mobile holes:
low voltage (mobile electrons) → conductorhigh voltage (depleted) → insulator
low voltage (depleted) → insulatorhigh voltage (mobile holes) → conductor
![Page 13: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/13.jpg)
13
P-Type N-Type
e
e
e
e
ee
e
ee
e
e
e
e
e
Bipolar Junction
low v → conductorhigh v → insulator
low v → insulatorhigh v → conductor
![Page 14: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/14.jpg)
14
P-Type N-Type
e
e
e
e
ee
e
e
e
e
e
e
e +–
Reverse Bias
low v → conductorhigh v → insulator
low v → insulatorhigh v → conductor
e
![Page 15: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/15.jpg)
15
P-Type N-Type
e
e
e
e
ee
e
ee
e
e
e
e
e e
e
e
e
e
e
e
e
–+
Forward Bias
low v → conductorhigh v → insulator
low v → insulatorhigh v → conductor
![Page 16: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/16.jpg)
16
Diodes
p-type n-type
PN Junction “Diode”
Conventions:vdd = vcc = +1.2v = +5v = hivss = vee = 0v = gnd
![Page 17: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/17.jpg)
17
PNP Junction
p-type p-typen-type
![Page 18: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/18.jpg)
18
Bipolar Junction Transistors
• Solid-state switch: The most amazing invention of the 1900s
Emitter = “input”, Base = “switch”, Collector = “output”
p n pC E=vdd
B
E
C
B
vdd
pnvss=E C
B
C
E
B
vss
n
PNP Transistor NPN Transistor
![Page 19: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/19.jpg)
19
Field Effect TransistorsP-type FET
• Connect Source to Drain when Gate = lo
• Drain must be vdd, or connected to source of another P-type transistor
N-type FET
• Connect Source to Drain when Gate = hi
• Source must be vss, or connected to drain of another N-type transistor
Drain = vdd
Source
Gate
Drain
Source = vss
Gate
![Page 20: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/20.jpg)
20
Multiple Transistors
In Out
voltage
Gate delay• transistor switching time• voltage, propagation,
fanout, temperature, …CMOS design
(complementary-symmetry metal–oxide–semiconductor)
Power consumption = dynamic + leakage
in out
Vdd
Vsst
0v
+5v
![Page 21: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/21.jpg)
21
Digital Logic
In Out+5v 0v
0v +5v
voltage
in out
Vdd
Vss t0v
+5v
+2v+0.5v
In Out
truth tableConventions:vdd = vcc = +1.2v = +5v = hi = true = 1vss = vee = 0v = gnd = false = 0
![Page 22: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/22.jpg)
22
NOT Gate (Inverter)
In Out0 11 0
in out
Truth table
Function: NOT Symbol:
in out
Vdd
Vss
![Page 23: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/23.jpg)
23
NAND Gate
A B out0 0 10 1 11 0 11 1 0
ba out
A
out
Vdd
Vss
B
BA
Vdd Function: NAND Symbol:
![Page 24: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/24.jpg)
24
NOR Gate
ba out
A
out
Vss
Vdd
B
BA
Vss
Function: NOR Symbol:
A B out
0 0 10 1 01 0 01 1 0
![Page 25: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/25.jpg)
25
Building Functions
• AND:
• OR:
• NOT:
![Page 26: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/26.jpg)
26
Universal Gates
NAND is universal (so is NOR)• Can implement any function with just NAND gates
– De Morgan’s laws are helpful (pushing bubbles)
• useful for manufacturing
E.g.: XOR (A, B) = A or B but not both (“exclusive or”)
Proof: ?
![Page 27: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/27.jpg)
27
AdministriviaMake sure you have access to CMS and Piazza.com
Lab Sections started this week• Lab0 turned in during Section• Bring laptop to section, if possible (not required)• Lab1 available Monday next week (due following Monday)• Group projects start in week 4 (partner in same section)
Homework1 available Monday• Due following Monday
Office hours start next week• More information available on website by this weekend
Clickers not required, bring to every lecture• Participation, not attendance
![Page 28: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/28.jpg)
28
Example: Big Picture
Computer System Organization and Programming platform from 10 years ago
• P- and N-transistors -> NAND and NOR gates -> logic circuit -> processor -> software -> applications (computers, cell phones, TVs, cars, airplanes, buildings, etc).
![Page 29: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/29.jpg)
29
Big Picture: Abstraction
Hide complexity through simple abstractions• Simplicity
– Box diagram represents inputs and outputs
• Complexity– Hides underlying P- and N-transistors and atomic interactions
in out
Vdd
Vss
in out outadb
a
b
d out
![Page 30: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/30.jpg)
30
Logic Equations
Some notation:• constants: true = 1, false = 0• variables: a, b, out, …• operators:
• AND(a, b) = a b = a & b = a b• OR(a, b) = a + b = a | b = a b• NOT(a) = ā = !a = a
![Page 31: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/31.jpg)
31
IdentitiesIdentities useful for manipulating logic equations
– For optimization & ease of implementation
a + 0 = a + 1 = a + ā = a 0 = a 1 = a ā = (a + b) = (a b) = a + a b = a(b+c) = a(b+c) =
a 1 1
0 a 0
a b a + b
a ab + ac a + bc
![Page 32: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/32.jpg)
32
Logic Manipulation• functions: gates ↔ truth tables ↔ equations• Example: (a+b)(a+c) = a + bc
a b c
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
![Page 33: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/33.jpg)
33
Logic Manipulation• functions: gates ↔ truth tables ↔ equations• Example: (a+b)(a+c) = a + bc
a b c
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
a+b a+c LHS
0 0 0
0 1 0
1 0 0
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
bc RHS
0 0
0 0
0 0
1 1
0 1
0 1
0 1
1 1
![Page 34: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/34.jpg)
34
![Page 35: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/35.jpg)
Predictive – logic minimization
• How to standardize minimizing logic circuits?
![Page 36: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/36.jpg)
Logic Minimization• A common problem is how to implement a desired
function most efficiently• One can derive the equation from the truth table
• How does one find the most efficient equation?– Manipulate algebraically until satisfied– Use Karnaugh maps (or K maps)
a b c minterm
0 0 0 abc
0 0 1 abc
0 1 0 abc
0 1 1 abc
1 0 0 abc
1 0 1 abc
1 1 0 abc
1 1 1 abc
for all outputs that are 1,take the correspondingmintermObtain the result in “sum of products” form
![Page 37: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/37.jpg)
Karnaugh maps
• Encoding of the truth table where adjacent cells differ in only one bit
a b out
0 0 0
0 1 0
1 0 0
1 1 1
0 0 1 0
00 01 11 10
truth tablefor AND
Corresponding Karnaugh map
ab
![Page 38: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/38.jpg)
Bigger Karnaugh Maps
3-inputfunc
a
b
c
y
00 01 11 10
0
1
abc
4-inputfunc
abc y
00 01 11 10
00
01
abcd
d
1110
![Page 39: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/39.jpg)
a b c out
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Sum of minterms yields abc + abc + abc + abc
Minimization with Karnaugh maps (1)
![Page 40: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/40.jpg)
a b c out
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Sum of minterms yields abc + abc + abc + abc
Karnaugh maps identify which inputs are (ir)relevant to the output
0 0 0 1
1 1 0 1
00 01 11 10
0
1
c ab
Minimization with Karnaugh maps (2)
![Page 41: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/41.jpg)
a b c out
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Sum of minterms yields abc + abc + abc + abc
Karnaugh map minimization Cover all 1’s Group adjacent blocks of
2n 1’s that yield a rectangular shape
Encode the common features of the rectangle out = ab + ac
0 0 0 1
1 1 0 1
00 01 11 10
0
1
c ab
Minimization with Karnaugh maps (2)
![Page 42: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/42.jpg)
Karnaugh Minimization Tricks (1)
0 1 1 1
0 0 1 0
00 01 11 10
0
1
c ab
1 1 1 1
0 0 1 0
00 01 11 10
0
1
cab
![Page 43: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/43.jpg)
Karnaugh Minimization Tricks (1)
Minterms can overlap out = bc + ac + ab
Minterms can span 2, 4, 8 or more cells out = c + ab
0 1 1 1
0 0 1 0
00 01 11 10
0
1
c ab
1 1 1 1
0 0 1 0
00 01 11 10
0
1
cab
![Page 44: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/44.jpg)
Karnaugh Minimization Tricks (2)
1 0 0 1
0 0 0 0
0 0 0 0
1 0 0 1
00 01 11 10
00
01
ab
cd
1110
0 0 0 0
1 0 0 1
1 0 0 1
0 0 0 0
00 01 11 10
00
01
ab
cd
1110
![Page 45: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/45.jpg)
Karnaugh Minimization Tricks (2)
• The map wraps around– out = bd
– out = bd1 0 0 1
0 0 0 0
0 0 0 0
1 0 0 1
00 01 11 10
00
01
ab
cd
1110
0 0 0 0
1 0 0 1
1 0 0 1
0 0 0 0
00 01 11 10
00
01
ab
cd
1110
![Page 46: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/46.jpg)
Karnaugh Minimization Tricks (3)
• “Don’t care” values can be interpreted individually in whatever way is convenient– assume all x’s = 1– out = d
– assume middle x’s = 0– assume 4th column x = 1– out = bd
1 0 0 x
0 x x 0
0 x x 0
1 0 0 1
00 01 11 10
00
01
ab
cd
1110
0 0 0 0
1 x x x
1 x x 1
0 0 0 0
00 01 11 10
00
01
ab
cd
1110
![Page 47: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/47.jpg)
Multiplexer• A multiplexer selects
between multiple inputs– out = a, if d = 0– out = b, if d = 1
• Build truth table• Minimize diagram• Derive logic diagram
a
b
d
![Page 48: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/48.jpg)
Multiplexer Implementation
a b d out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
• Build a truth table= abd + abd + a bd + a b d
a
b
d
![Page 49: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/49.jpg)
Multiplexer Implementation
a b d out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
• Build the Karnaugh mapa
b
d
0 0 1 1
0 1 1 0
00 01 11 10
0
1
d ab
![Page 50: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/50.jpg)
Multiplexer Implementation
a b d out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
• Derive Minimal Logic Equation
• out = ad + bd
a
b
d
0 0 1 1
0 1 1 0
00 01 11 10
0
1
d ab
![Page 51: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/51.jpg)
Multiplexer Implementation
d out
b
a
00 01 11 10
0
1
d ab
• Derive Minimal Logic Equation
• out = ad + bd
0 0 1 1
0 1 1 0
a b d out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
a
b
d
![Page 52: Gates and Logic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell Universty See: P&H Appendix C.2 and C.3 (Also, see C.0 and C.1)](https://reader036.fdocuments.us/reader036/viewer/2022062718/56649eab5503460f94bb1088/html5/thumbnails/52.jpg)
Summary
• We can now implement any logic circuit– Can do it efficiently, using Karnaugh maps to
find the minimal terms required– Can use either NAND or NOR gates to
implement the logic circuit– Can use P- and N-transistors to implement
NAND or NOR gates