GATE ARRAY S1L50000 SERIES DESIGN GUIDE - Epson · 6.7.3 Gate Count Estimation ... CMOS process...

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The information of the product number change Starting April 1, 2001 the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.

Configuration of product number

• DEVICES S1 L 60843 F 00A0 00

*1 : Model name

K Standard Cell L Gate Array X Embedded Array

*2 : Shape

B Assembled on board, COB, BGA

M Plastic SOP

C Plastic DIP R TAB-QFP D Bare Chip T Tape Carrier (TAB) F Plastic QFP 2 TSOP (Standard Bent) H Ceramic DIP 3 TSOP (Reverse Bent) L Ceramic QFP

Comparison table between new and previous number

Previous number New Number Previous number New Number SLA50000H series S1L50000 series SLA525TH S1L52503 SLA5028H S1L50282 SLA525QH S1L52504 SLA502TH S1L50283 SLA5335H S1L53352 SLA502QH S1L50284 SLA533TH S1L53353

− S1L50552 SLA533QH S1L53354 − S1L50553 SLA5442H S1L54422 − S1L50554 SLA544TH S1L54423

SLA5075H S1L50752 SLA544QH S1L54424 SLA507TH S1L50753 SLA5506H S1L55062 SLA507QH S1L50754 SLA550TH S1L55063 SLA5099H S1L50992 SLA550QH S1L55064 SLA509TH S1L50993 SLA5668H S1L56682 SLA509QH S1L50994 SLA566TH S1L56683 SLA5125H S1L51252 SLA566QH S1L56684 SLA512TH S1L51253 SLA5815H S1L58152 SLA512QH S1L51254 SLA581TH S1L58153 SLA5177H S1L51772 SLA581QH S1L58154 SLA517TH S1L51773 SLA517QH S1L51774 SLA5250H S1L52502

Packing specifications Specifications Shape (*2)

Model number

Model name (*1)

Product classification (S1:Semiconductors)

Table of Contents

GATE ARRAY S1L50000 SERIES EPSON i DESIGN GUIDE

S1L50000 SERIES Table of Contents

Chapter 1 Overview ..................................................................................................................................... 1

1.1 Features........................................................................................................................................... 1 1.2 Master Lineup ................................................................................................................................. 2 1.3 Electrical Characteristics and Specifications .................................................................................. 3 1.4 Outline of Gate Array Development Flow.................................................................................... 10

Chapter 2 Gate Count Estimation and Master Selection............................................................................ 12 2.1 Circuit Partitioning........................................................................................................................ 12 2.2 Gate Count Estimation.................................................................................................................. 12 2.3 IO Pin Count Estimation............................................................................................................... 12 2.4 Master Selection............................................................................................................................ 12 2.5 Estimation of Usable BC Count for the Circuit with RAM .......................................................... 13

Chapter 3 Design Restrictions and Limitations ......................................................................................... 14 3.1 Basic Design Techniques .............................................................................................................. 14

3.1.1 Insertion of IO buffers........................................................................................................... 14 3.1.2 Avoid Excessive Fanout........................................................................................................ 14 3.1.3 Wired logic is prohibited....................................................................................................... 15 3.1.4 Synchronous Design Techniques .......................................................................................... 15

3.2 Differentiating Circuits are Prohibited.......................................................................................... 16 3.3 Clock Tree Synthesis..................................................................................................................... 17

3.3.1 Outline .................................................................................................................................. 17 3.3.2 Design Flow.......................................................................................................................... 18 3.3.3 How to implement................................................................................................................. 19 3.3.4 Constraints and notes .......................................................................................................... 20 3.3.5 Clock Tree Synthesis Check Sheet........................................................................................ 22 3.3.6 Reference .............................................................................................................................. 23

3.4 Designing High-Speed Circuits .................................................................................................... 27 3.5 Metastable ..................................................................................................................................... 28 3.6 Internal Bus Configuration............................................................................................................ 29 3.7 Avoid Contention with External Bus ............................................................................................ 31 3.8 Solution for Hazards ..................................................................................................................... 32 3.9 Oscillator Circuits ......................................................................................................................... 32

3.9.1 Oscillator circuit configurations.......................................................................................... 32 3.9.2 Notes when using oscillator circuits ..................................................................................... 33

3.10 Constraints on Verilog-HDL/VHDL Netlists ............................................................................ 35 3.10.1 Constraints on Verilog-HDL/VHDL netlists ..................................................................... 35 3.10.2 Constraints on Verilog netlists .............................................................................................. 36 3.10.3 Constraints on VHDL netlists ............................................................................................... 37 3.10.4 About descriptions of oscillator cells and AC/DC test circuit cell (TCIR2) ......................... 37 3.10.5 About descriptions of clock root buffers............................................................................... 38

Chapter 4 Types of I/O Buffers and Notes on Use..................................................................................... 40 4.1 Types of I/O Buffers ..................................................................................................................... 40

4.1.1 Selection of I/O buffers......................................................................................................... 40 4.1.2 Bus Hold Circuit ................................................................................................................... 41

4.2 I/O Buffers for Single Power Supply Operation ........................................................................... 41 4.2.1 Input Buffers ......................................................................................................................... 41 4.2.2 Output Buffers....................................................................................................................... 43 4.2.3 Bi-Directional Buffers........................................................................................................... 46 4.2.4 Fail-Safe Cells....................................................................................................................... 49 4.2.5 Gated Cells............................................................................................................................ 52

4.3 I/O Buffers for Dual Power Supply Operation.............................................................................. 55 4.3.1 Input Buffers ......................................................................................................................... 55 4.3.2. Output Buffers....................................................................................................................... 58 4.3.3 Bi-Directional Buffers........................................................................................................... 64

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ii EPSON GATE ARRAY S1L50000 SERIES DESIGN GUIDE

4.3.4 Fail-Safe Cell .........................................................................................................................71 4.3.5 Gated Cells.............................................................................................................................72

4.4 Notes on the Use of Dual Power Supplies .....................................................................................74 4.4.1 To Implement Dual Power Supply Designs...........................................................................74 4.4.2 Power Supply for Dual Power Supply Designs .....................................................................74 4.4.3 Power On-Off Sequence ........................................................................................................74

Chapter 5 RAM ..........................................................................................................................................75 5.1 Features..........................................................................................................................................75 5.2 Word-bit Configurations and Simulation Models ..........................................................................75 5.3 RAM Size Estimation ....................................................................................................................76 5.4 Embeddable RAM Size .................................................................................................................77 5.5 Function Examples ........................................................................................................................78 5.6 Delay Parameters ...........................................................................................................................81 5.7 Timing Chart..................................................................................................................................97 5.8 Access to Invalid Addresses ..........................................................................................................99

Chapter 6 Design for Testability...............................................................................................................100 6.1 Circuit Initialization.....................................................................................................................100 6.2 Shortening the Test Patterns.........................................................................................................100 6.3 Special Test Circuit Provisions for AC and DC Tests..................................................................100

6.3.1 Test Circuit Configuration ...................................................................................................101 6.4 Test Circuit for Memory Blocks ..................................................................................................108

6.4.1 Test Patterns for RAM Blocks .............................................................................................108 6.5 Test Circuit for Function Cells.....................................................................................................111

6.5.1 Test Circuit Configuration ...................................................................................................111 6.5.2 Test Patterns.........................................................................................................................111 6.5.3 Test Circuit Information.......................................................................................................111

6.6 Scan Design .................................................................................................................................112 6.6.1 Scan Circuit .........................................................................................................................112 6.6.2 Scan Design Flow................................................................................................................112 6.6.3 Design Rules........................................................................................................................114

6.7 Boundary Scan Design ................................................................................................................123 6.7.1 Boundary Scan Design Flow ...............................................................................................123 6.7.2 Instructions ..........................................................................................................................124 6.7.3 Gate Count Estimation.........................................................................................................124 6.7.4 Design Rules........................................................................................................................124

Chapter 7 Propagation Delay and Timing.................................................................................................129 7.1 Relationship between Ta and Tj...................................................................................................129 7.2 Calculation of Propagation Delay................................................................................................129 7.3 Input Capacitance Load (Load A)................................................................................................132 7.4 Wire Capacitance Load (Load B) ................................................................................................133 7.5 Estimation of Propagation Delay Time........................................................................................133 7.6 Output Buffer Delay Estimation ..................................................................................................135 7.7 Setup and Hold Time for Flip-Flops ............................................................................................135

Chapter 8 Test Pattern Generation ............................................................................................................138 8.1 Testability Considerations............................................................................................................138 8.2 Usable Waveforms.......................................................................................................................138 8.3 Constraints on Test Patterns.........................................................................................................139

8.3.1 Test Rate and Event Count...................................................................................................139 8.3.2 Input Delay ..........................................................................................................................139 8.3.3 Pulse Width..........................................................................................................................139 8.3.4 Input Waveform Format.......................................................................................................139 8.3.5 Strobe...................................................................................................................................139

8.4 Notes on DC Test.........................................................................................................................140 8.5 Notes When Using Oscillator Circuit ..........................................................................................142 8.6 AC Test ........................................................................................................................................143

8.6.1 Constraints on Test Events...................................................................................................143 8.6.2 Constraints on AC Test Points .............................................................................................143

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GATE ARRAY S1L50000 SERIES EPSON iii DESIGN GUIDE

8.6.3 Constraints on Test Path Delay ........................................................................................... 143 8.6.4 Other Constraints ................................................................................................................ 143

8.7 Constraints on Test Patterns of Bi-directional Pin ...................................................................... 143 8.8 Notes on High-Impedance State.................................................................................................. 144

Chapter 9 Calculating Total Power Consumption.................................................................................... 145 9.1 Calculating Power Consumption ................................................................................................ 145

9.1.1 Internal Cell (Pint) .............................................................................................................. 145 9.1.2 Input Buffers (Pi) ................................................................................................................ 146 9.1.3 Output Buffers (Po)............................................................................................................. 146 9.1.4 Low Power Cells................................................................................................................. 147 9.1.5 Low Noise Cells.................................................................................................................. 147

9.2 Limit on Power Consumption ..................................................................................................... 148 Chapter 10 Pinout and Simultaneous Output Switching.......................................................................... 150

10.1 Estimating Power Supply Pin Count........................................................................................... 150 10.2 Simultaneous Switching and Power Supply Addition................................................................. 152 10.3 Notes on Pinout........................................................................................................................... 154

10.3.1 Power Supply Pins in Fixed Locations ............................................................................... 154 10.3.2 Notes on Pinout................................................................................................................... 154 10.3.3 Recommended Pinout ......................................................................................................... 159

Appendix A1 Input/Output Buffer Characteristic Graphs........................................................................ 161 A1.1 5.0-V operation ........................................................................................................................... 161 A1.2 3.3-V operation ........................................................................................................................... 170 A1.3 2.0-V operation ........................................................................................................................... 179

Table of Contents

iv EPSON GATE ARRAY S1L50000 SERIES DESIGN GUIDE

Chapter 1 Overview

GATE ARRAY S1L50000 SERIES EPSON 1 DESIGN GUIDE

Chapter 1 Overview The S1L50000 Series gate arrays featuring high speed and high integration are fabricated on a 0.35um CMOS process with “sea-of-gates” architecture.

1.1 Features • Maximum gate count 815,468 (2-input NAND gates)

• Operating speed Internal logic gates: 140ps (3.3V, typical conditions), 210ps (2.0V, typical conditions) (2-input power NAND, F/O = 2, typical wire load capacitance and conditions)

Input buffers: 380ps (5.0V, typical conditions) using level shifter 400ps (3.3V, typical conditions), 1.30ns (2.0V, typical conditions) (F/O = 2, typical wire load capacitance and conditions)

Output buffers: 2.12ns (5.0V, typical conditions) using level shifter 2.02ns (3.3V, typical conditions), 3.90ns (2.0V, typical conditions) (CL = 15pF, typical conditions)

• Process 0.35um, 2-, 3-, and 4-layer aluminum interconnect

• I/F levels IO TTL, COMS, and LVTTL compatible

• Input modes TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI, and fail-safe inputs With built-in pull-up and pull-down resistors (Each resistor has two resistance values)

• Output modes Normal, 3-state, bi-directional, PCI, and fail-safe outputs

• Output drive IOL = 0.1, 1, 3, 8, 12, 24mA selectable (when using 5.0V level shifter) IOL = 0.1, 1, 2, 6, 12mA selectable (at 3.3V) IOL = 0.05, 0.3, 0.6, 2, 4mA selectable (at 2.0V)

• RAM 1-port asynchronous, 2-port asynchronous

• Dual power supply operation by built-in level shifter Internal logic: Low voltage I/O buffers: High and low voltages mixed

Chapter 1 Overview

2 EPSON GATE ARRAY S1L50000 SERIES DESIGN GUIDE

1.2 Master Lineup The following 14 masters are available for the S1L50000 Series:

Table 1-1 Master Lineup

BC Count Cell Utilization U: (%)*2 Masters Total BC

Count *1 PAD

Count Row Column 2-LM 3-LM 4-LM

S1L50062/50063/50064 5760 48 144 40 50 88 95

S1L50122/50123/50124 11948 56/64 206 58 50 88 95

S1L50282/50283/50284 28710 88/104 319 90 50 88 95

S1L50552/50553/50554 55500 124/144 444 125 47 85 95

S1L50752/50753/50754 75774 144/168 519 146 47 85 95

S1L50992/50993/50994 99198 168/192 594 167 47 85 95

S1L51252/51253/51254 125772 188/216 669 188 45 80 95

S1L51772/51773/51774 177062 224 794 223 45 75 95

S1L52502/52503/52504 250160 264 944 265 45 75 95

S1L53352/53353/53354 335858 308 1094 307 43 75 95

S1L54422/54423/54424 442112 352 1256 352 40 70 90

S1L55062/55063/55064 506688 376 1344 377 40 70 90

S1L56682/56683/56684 668552 432 1544 433 40 70 90

S1L58152/58153/58154 815468 480 1706 478 40 70 90

Notes: *1 : Add about 350 BCs to the estimation for the recommended test circuit. *2 : Values shown here are utilization when RAM and other macro cells are not embedded.

Since utilization is dependent not only on logic size, but also on the numbers of signal lines and nodes per signal, these values can be used only as reference.

Chapter 1 Overview


1.3 Electrical Characteristics and Specifications

Table 1-2 Absolute Maximum Ratings (Single power supply) (VSS = 0 V)

Parameter Symbol Limit Unit

Power Supply Voltage VDD -0.3 to +4.0 V

Input Voltage VI -0.3 to VDD+0.5*1 V

Output Voltage VO -0.3 to VDD+0.5*1 V

Output Current/Pin IOUT ±30 mA

Storage Temperature Tstg -65 to +150 °C

Note: *1: For N-channel open drain bi-directional buffers, input buffers prefixed with IDC and IDH, and fail-safe cells, the allowable voltage range is –0.3 to +7.0V.

Table 1-3 Absolute Maximum Ratings (Dual power supplies) (VSS = 0 V)

Parameter Symbol Limit Unit

HVDD*3 -0.3 to +7.0 V

Power Supply Voltage LVDD

*3 -0.3 to +4.0 V

HVI -0.3 to HVDD+0.5*1 V Input Voltage

LVI -0.3 to LVDD+0.5*1 V

HVO -0.3 to HVDD+0.5*1 V Output Voltage

LVO -0.3 to LVDD+0.5*1 V

Output Current/Pin IOUT ±30 (±50*2) mA

Storage Temperature Tstg -65 to +150 °C

Notes: *1 : For N-channel open drain bi-directional buffers, input buffers prefixed with LIDC, LIDH, HIDC and HIDH, and fail-safe cells, the allowable voltage range is –0.3 to +7.0V.

*2 : Applicable to buffers with 24mA output current *3: HVDD≥LVDD must be met.

Chapter 1 Overview


Table 1-4 Recommended Operating Conditions (for single power supply operation with VDD = 3.3V)

(VSS = 0 V)

Parameter Symbol Min. Typ. Max. Unit

Power Supply Voltage VDD 3.00 3.30 3.60 V

Input Voltage VI -0.3 - VDD+0.3*1 V

0 25 70*2 Ambient Temperature Ta

-40 25 85*3 °C

Normal Input Rising Time*4 tri - - 50 ns

Normal Input Falling Time*4 tfa - - 50 ns

Schmitt Input Rising Time*4 tri - - 5 ms

Schmitt Input Falling Time*4 tfa - - 5 ms

Notes: *1 : For N-channel open drain bi-directional buffers, input buffers prefixed with IDC and IDH, and fail-safe cells, the limit voltage is 5.55V or 5.80V.

*2: Temperature range recommended when Tj = 0 to +85°C *3: Temperature range recommended when Tj = -40 to +125°C *4: Period during which power supply voltage changes by 10 to 90%

Table 1-5 Recommended Operating Conditions (for single power supply operation with VDD = 2.0V)

(VSS = 0 V)


Power Supply Voltage VDD 1.80 2.00 2.20 V

Input Voltage VI -0.3 - VDD+0.3*1 V

0 25 70*2 Ambient Temperature Ta

-40 25 85*3 °C

Normal Input Rising Time *4 tri - - 100 ns

Normal Input Falling Time *4 tfa - - 100 ns

Schmitt Input Rising Time *4 tri - - 10 ms

Schmitt Input Falling Time *4 tfa - - 10 ms

Notes: *1 : For N-channel open drain bi-directional buffers, input buffers prefixed with IDC and IDH, and fail-safe cells, the allowable voltage range is 5.55V or 5.80V.

*2: Temperature range recommended when Tj = 0 to +85°C *3: Temperature range recommended when Tj = -40 to +125°C *4: Period during which the power supply voltage changes by 10 to 90%

Chapter 1 Overview


Table 1-6 Recommended Operating Conditions (for dual power supply operation) (VSS = 0 V)


Power Supply Voltage (High) HVDD 4.75 4.50

5.00 5.00

5.25 5.50 V

Power Supply Voltage (Low) LVDD 3.00 3.30 3.60 V

HVI -0.3 - HVDD+0.3*1 V Input Voltage

LVI -0.3 - LVDD+0.3*1 V

Ambient Temperature Ta 0 -40

25 25

70*2 85*3 °C

Normal Input Rising Time*4 tri - - 50 ns

Normal Input Falling Time*4 tfa - - 50 ns

Shumitt Input Rising Time*4 tri - - 5 ms

Shumitt Input Falling Time*4 tfa - - 5 ms

Notes: *1 : For N-channel open drain bi-directional buffers, input buffers prefixed with LIDC and LIDH, and fail-safe cells, the limit voltage is 5.55V or 5.80V.


Table 1-7 Recommended Operating Conditions (for dual-power supply operation) (VSS = 0 V)

Item Symbol Min. Typ. Max. Unit

Power Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V

Power Supply Voltage (Low Voltage) LVDD 1.80 2.00 2.20 V

HVI -0.3 HVDD+0.3*1 V Input Voltage

LVI -0.3 LVDD+0.3*1 V

Ambient Temperature Ta 0 -40

25 25

70*2 85*3 °C

Htri 50 Normal Input Rising Time *4

Ltfa 100 ns

Htri 50 Normal Input Falling Time *4

Ltfa 100 ns

Htri 5 Schmitt Input Rising Time *4

Ltfa 10 ms

Htri 5 Schmitt Input Falling Time *4

Ltfa 10 ms

Notes: *1 : For N-channel open drain bi-directional buffers, input buffers prefixed with LIDC, LIDH, HIDC, and HIDH, and fail-safe cells, the limit voltage is 5.55V or 5.80V.


Chapter 1 Overview


Table 1-8 Electrical Characteristics (HVDD = 5V, VSS = 0V, Ta = -40 to +85°C)

Parameter Symbol Conditions Min. Typ. Max. UnitInput Leakage Current ILI - -1 - 1 µA Off State Leakage Current IOZ - -1 - 1 µA

High Level Output Voltage VOH

IOH = -0.1mA(Type S), -1mA(Type M)-3mA (Type 1), -8mA (Type 2) -12mA (Type 3, Type 4)

HVDD = Min.

HVDD-0.4 - - V

Low Level Output Voltage VOL

IOL = 0.1mA (Type S),1mA (Type M) 3mA (Type 1), 8mA (Type 2) 12mA (Type 3), 24mA (Type 4)

HVDD = Min.

- - 0.4 V

High Level Input Voltage VIH1 CMOS level, HVDD = Max. 3.5 - HVDD +0.3 V

Low Level Input Voltage VIL1 CMOS level, HVDD = Min. -0.3 - 1.0 V High Level Input Voltage VT1+ CMOS Schmitt 2.0 - 4.0 V Low Level Input Voltage VT1- CMOS Schmitt 0.8 - 3.1 V Hysteresis Voltage ∆V CMOS Schmitt 0.3 - - V

High Level Input Voltage VIH2 TTL level, HVDD = Max. 2.0 - HVDD +0.3 V

Low Level Input Voltage VIL2 TTL level, HVDD = Min. -0.3 - 0.8 V High Level Input Voltage VT2+ TTL Schmitt 1.2 - 2.4 V Low Level Input Voltage VT2- TTL Schmitt 0.6 - 1.8 V Hysteresis Voltage VH2 TTL Schmitt 0.1 - - V

High Level Input Voltage*2 VIH3 PCI level, HVDD = Max. 2.0 - HVDD +0.3 V

Low Level Input Voltage*2 VIL3 PCI level, HVDD = Min. -0.3 - 0.8 V

Type 1 30 60 (120)*1 144 kΩ

Pull-Up Resistor PPU VI = 0V Type 2 60 120 (240)*1

288 kΩ

Type 1 30 60 (120)*1 144 kΩ

Pull-Down Resistor PPD VI = HVDD

Type 2 60 120 (240)*1 288 kΩ

High Level Output Current*2 IOH3

PCI VOH = 1.4V, HVDD = Min.

VOH = 3.1V, HVDD = Max.

-44 -

- -

- -142 mA

Low Level Output Current*2 IOL3

PCI VOL = 2.20V, HVDD = Min. VOL = 0.71V, HVDD = Max.

95 -

- -

- 206 mA

High Level Bus Hold Current IBHH

Bus hold VIN = 2.0V HVDD = Min.

- - -80 µA

Low Level Bus Hold Current IBHL

Bus hold VIN = 0.8V HVDD = Min.

- - 33 µA

High Level Overdrive Current IBHHO To flip bus hold VIN = 0.8V

HVDD = Max. -550 - - µA

Low Level Overdrive Current IBHLO To flip bus hold VIN = 2.0V

HVDD = Max. 330 - - µA

Input Pin Capacitance CI f = 1MHz, HVDD = 0V - - 10 pF Output Pin Capacitance CO f = 1MHz, HVDD = 0V - - 10 pF IO Pin Capacitance CIO f = 1MHz, HVDD = 0V - - 10 pF

Notes: *1 : Values in parentheses are applicable when Ta = 0 to +70°C *2: Compliant with the PCI standard Rev. 2.2

Chapter 1 Overview


Table 1-9 Electrical Characteristics (VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = -40 to 85°C)

Item Symbol Conditions Min. Typ. Max. UnitInput Leakage Current ILI ― -1 1 µA Off State Leakage Current IOZ ― -1 1 µA

High Level Output Voltage VOH IOH = -0.1mA (Type S), -1mA (Type M)

-2mA (Type 1), -6mA (Type 2) -12mA (Type 3)

VDD = Min.

VDD -0.4 V

Low Level Output Voltage VOL IOL = 0.1mA (Type S), 1mA (Type M)

2mA (Type 1), 6mA (Type 2) 12mA (Type 3)

VDD = Min.

0.4 V

High Level Input Voltage VIH1 LVTTL Level, VDD = Max. 2.0 VDD +0.3

V

Low Level Input Voltage VIL1 LVTTL Level, VDD = Min. -0.3 0.8 V High Level Input Voltage VT1+ LVTTL Schmitt 1.1 2.4 V Low Level Input Voltage VT1- LVTTL Schmitt 0.6 1.8 V

Hysteresis Voltage ∆V LVTTL Schmitt 0.1 V

High Level Input Voltage *2 VIH3 PCI Level, VDD = Max. 1.8 VDD +0.3 V

Low Level Input Voltage *2 VIL3 PCI Level, VDD = Min. -0.3 0.9 V

Type 1 20 50 (100)*1

120 kΩ Pull Up Resistor PPU VI = 0V

Type 2 40 100 (200)*1

240 kΩ

Type 1 20 50 (100)*1

120 kΩ Pull Down Resistor PPD VI = VDD

Type 2 40 100 (200)*1

240 kΩ

High Level Output Current *2 IOH3

PCI VOH = 0.90V, VDD = Min. VOH = 2.52V, VDD = Max.

-36

-115 mA

Low Level Output Current *2 IOL3

PCI VOL = 1.80V, VDD = Min. VOL = 0.65V, VDD = Max.

48

137 mA

High Level Maintenance Current IBHH Bus Hold

VIN = 2.0V, VDD = Min. -20 µA

Low Level Maintenance Current IBHL

Bus Hold VIN = 0.8V, VDD = Min. 17 µA

High Level Reversal Current IBHHO Bus Hold

VIN = 0.8V, VDD = Max. -350 µA

Low Level Reversal Current IBHLO Bus Hold

VIN = 2.0V, VDD = Max. 210 µA

Input Terminal Capacitance CI

f = 1MHz, VDD = 0V 10 pF

Output Terminal Capacitance CO f = 1MHz, VDD = 0V 10 pF

Input/Output Terminal Capacitance CIO f = 1MHz, VDD = 0V 10 pF

Notes: *1 : Values in parentheses are applicable when Ta = 0 to +70°C *2: Compliant with the PCI standard Rev. 2.2

Chapter 1 Overview


Table 1-10 Electrical Characteristics (VDD or LVDD = 2.0V±0.2V, VSS = 0V, Ta = -40 to +85°C)

Parameter Symbol Conditions Min. Typ. Max. UnitInput Leakage Current ILI - -1 - 1 µA Off State Leakage Current IOZ - -1 - 1 µA

High Level Output Voltage VOH

IOH = -0.05mA(Type S), -0.3mA (Type M)-0.6mA (Type 1), -2mA (Type 2) -4mA (Type 3)

VDD = Min.

VDD-0.2 - - V

Low Level Ouput Voltage VOL

IOL = 0.05mA(Type S), 0.3mA (Type M)0.6mA (Type 1), 2mA (Type 2) 4mA (Type 3)

VDD = Min.

- - 0.2 V

High Level Input Voltage VIH1 CMOS level, VDD = Max. 1.6 - VDD +0.3 V

Low Level Input Voltage VIL1 CMOS level, VDD = Min. -0.3 - 0.3 V High Level Input Voltage VT1+ CMOS Schmitt 0.4 - 1.6 V Low Level Input Voltage VT1- CMOS Schmitt 0.3 - 1.4 V Hysteresis Voltage ∆V CMOS Schmitt 0 - - V

Type 1 30 120 300 kΩ Pull-Up Resistor PPU VI = 0V Type 2 60 240 600 kΩ Type 1 30 120 300 kΩ Pull-Down Resistor PPD VI＝VDD Type 2 60 240 600 kΩ

High Level Bus Hold Current IBHH Bus hold VIN = 1.6V

VDD = Min. - - -2 µA

Low Level Bus Hold Current IBHL

Bus hold VIN = 0.3V VDD = Min. - - 2 µA

High Level Overdrive Current IBHHO To flip bus hold VIN = 0.3V

VDD = Max. -100 - - µA

Low Level Overdrive Current IBHLO To fip bus hold VIN = 1.6V

VDD = Max. 100 - - µA

Input Pin Capacitance CI F = 1MHz, VDD = 0V - - 10 pF Output Pin Capacitance CO F = 1MHz, VDD = 0V - - 10 pF IO Pin Capacitance CIO F = 1MHz, VDD = 0V - - 10 pF

Chapter 1 Overview


Table 1-11 Static Current (With single power supply) (Tj = 85°C)

Master 3.3V ± 0.3V IDDS Max.

2.0V ± 0.2V IDDS Max. Unit

S1L50062/50063/50064 S1L50122/50123/50124 5 4 µA

S1L50282/50283/50284 S1L50552/50553/50554 S1L50752/50753/50754 S1L50992/50993/50994

35 31 µA

S1L51252/51253/51254 S1L51772/51773/51774 S1L52502/52503/52504

90 80 µA

S1L53352/53353/53354 S1L54422/54423/54424 S1L55062/55063/55064

170 150 µA

S1L56682/56683/56684 S1L58152/58153/58154 260 230 µA

Table 1-12 Static Current (With dual power supplies) (Tj = 85°C)

Master 5V ± 0.5V HIDDS Max.

3.3V ± 0.3V LIDDS Max.

3.3V ± 0.3V HIDDS Max.

2.0V ± 0.2V LIDDS Max. Unit

S1L50062/50063/50064 S1L50122/50123/50124 11 5 9 4 µA

S1L50282/50283/50284 S1L50552/50553/50554 S1L50752/50753/50754 S1L50992/50993/50994

30 35 25 31 µA

S1L51252/51253/51254 S1L51772/51773/51774 S1L52502/52503/52504

45 90 35 80 µA

S1L53352/53353/53354 S1L54422/54423/54424 S1L55062/55063/55064

65 170 50 150 µA

S1L56682/56683/56684 S1L58152/58153/58154 80 260 60 230 µA

HIDDS: Static current between HVDD and VSS

LIDDS: Static current between LVDD and VSS

Chapter 1 Overview


Use the following equation to obtain approximate static current when the temperature condition is other than Tj = 85°C. (The equation is applicable only when Tj = -40 to 85°C. When Tj = 125°C, apply temperature coefficient = 12. When Tj = 85°C to 125°C, contact Epson sale representative.)

IDDS = IDDS (Tj = 85°C) × Temperature Coefficient

= IDDS (Tj = 85°C) × 6085

10−Tj

(Example) When VDD = 3.3V±0.3V and Tj = 50°C, the approximate static current of S1L55062 is obtained as follows:

IDDS (Tj = 50°C) = IDDS(Tj = 85°C) × 608550

10−

= 170 × 0.261

= 44.37 (µA)

When the device is operated with dual power supplies, the sum of static currents that flow at voltages used is the total static current (HIDDS + LIDDS).

1.4 Outline of Gate Array Development Flow The customer and Epson work together to develop gate arrays. Using the cell libraries and various design information provided by Epson, the customer designs the system and logic, and creates test patterns. Then the customer is requested to present Epson the data and documents checked against the data release checklist attached in this Design Guide.

Simulation and simulation result analysis are performed by the customer using the EDA software available at the customer’s design site and the EPITS7* offered by Epson. Then Epson takes over the subsequent tasks starting from placement and routing.

* The EPITS7 is Epson specific ASIC library kit that is developed to run on the SUN-Solaris platform.

The EPITS7 currently supports the following EDA software:

• Verilog-XL, NC-Verilog *1

• Design Compiler *2

NOTE: *1 : Verilog-XL and NC-Verilog are registered trademarks of Cadence Design Systems Corporation, USA.

*2 : Design Compiler is a registered trademark of Synopsys Inc., USA.

For more information, contact Epson’s sales representative.

Chapter 1 Overview


The gate array development flow is shown below:

Chapter 2 Gate Count Estimation and Master Selection


Chapter 2 Gate Count Estimation and Master Selection This chapter describes how to select the right master to implement a given circuit on gate arrays. It discusses how to estimate the gate count of the circuit partitioned from the system designed by the customer. Points that the designer needs to pay attention to when selecting a master are also discussed.

2.1 Circuit Partitioning Care must be taken for the following points when partitioning a circuit from the system designed by the customer and implementing the partitioned circuit on gate arrays.

i. Gate count

ii. IO pin count

iii. Target package

iv. Power consumption

As the circuit size (gate count) increases, the power consumption and IO pin count normally increase. Because of this, partitioning the circuit into multiple chips may sometimes turn out to be more cost effective and power saving than forcibly implementing the circuit on a single chip.

2.2 Gate Count Estimation The circuit size is obtained by counting up all the basic cells (BC) comprising the pre-designed function cells used in the circuit. The BC count of each cell is described in the Gate Array S1L50000 Series MSI Cell Library. To obtain the total BC count of the circuit, refer to the library.

2.3 IO Pin Count Estimation Following the gate count estimation, the IO pin count must be estimated. In doing this, count in test pins for RAM and other macro cells as well as power supply pins. To estimate power supply pin count, refer to Chapter 10, Pinout and Simultaneous Switching Outputs.

2.4 Master Selection Considering the estimated BC count, IO pin count (including power supply pins) and the target package, select the best possible master from Table 1-1, Master Lineup in Chapter 1.

Usable gate count (BCA) for each design is obtained by the following formula using the raw gate count (BCG) of each master and the cell utilization (U) shown in Table 1-1:

BCA = U × BCG

When the design includes RAM cells, refer to the next section and Chapter 5, RAM.

Chapter 2 Gate Count Estimation and Master Selection


2.5 Estimation of Usable BC Count for the Circuit with RAM RAM blocks are extremely large compared to MSI cells, and have fixed sizes in height and width. There are cases where RAM blocks are actually not embeddable, though they appear to fit into the chip with the estimated BC count. Refer to Chapter 5, RAM and check first whether the RAM block is embeddable or not. When target masters are narrowed down, use the following formula to estimate usable BC count for random logic blocks (BCAWR), excluding RAM cell(s):

BCAWR = 0.9 × U × (BCG-BCRAM)

NOTE: The formula stated above may not be applicable in some cases depending on the geometry of random logic area left after the layout of RAM cell(s) regardless of RAM cell count. If the design includes RAM cell(s), contact Epson sales representative for confirmation.

Chapter 3 Design Restrictions and Limitations



3.1 Basic Design Techniques

3.1.1 Insertion of IO buffers

All LSI signals need to be input and output through IO buffers. Be sure to insert either input or output buffer between an external pin and an internal cell. This is because CMOS LSI devices are extremely vulnerable to static electricity and thus they need to be protected by IO buffers integrating a circuit to prevent static electricity.

3.1.2 Avoid Excessive Fanout

In CMOS circuits, as the output load capacitance increases, the signal propagation delay time (tpd) becomes longer together with the rising and falling times of signal waveforms (Tslew).

If the output load capacitance of any one logic gate becomes excessive, signal delays may occur at a specific circuit node. This lowers the operation speed and accuracy in delay simulation, and causes erroneous operations. Because the signal takes longer time to switch, it becomes more susceptible to noise effect.

To avoid excessive load on logic gates in the design phase, limit on connectable load called “fan-out limit” is specified. For each logic gate input pin, the input capacitance relative to the input capacitance of an inverter cell (IN1), called “fan-in” is specified. The fan-out limit is the total number of fan-ins connectable to the output pin of each logic gate. When designing a circuit, make sure that the total fan-ins do not exceed the fan-out of the gate output pin. For logic gate output pins that operate at high speed, such as high-speed clock pins (that operate at 60 MHz or higher), limit the fan-out to about half the normal fan-out value.

The actual load capacitance of a logic gate output pin includes the signal wire capacitance in addition to the input capacitance of the gate connected to the output pin. As the result of running the placement and routing tool, specific nodes may have large load capacitance. The load capacitance of each circuit node can be checked by Tslew output result. If any node capacitance exceeds the specified value, we may ask the customer to modify the circuit to meet the specification. Not to increase the load capacitance after layout, minimize the number of circuit branches from a single node, or use buffers with larger fan-out values.



3.1.3 Wired logic is prohibited

Since CMOS transistors are used for the S1L50000 series, wired logic functions (see Figure 3-1) are prohibited unlike bi-polar transistors. The only permissible method for connecting the outputs of multiple gates is using a bus circuit.

Figure 3-1 Examples of prohibited wired logic

3.1.4 Synchronous Design Techniques

The most fundamental and essential ASIC design guideline is to make sure that all circuits are designed with synchronous logic. In synchronous designs, timings between registers are simple and thus suitable for high-speed circuit designs, a variety of EDA tools, such as those for clock tree synthesis, DFT and STA, are possible to use, and technology independent circuits are easily reusable.

Ideal synchronous circuits meet the following conditions:

1. The timing of all registers in the circuit remains synchronized with one clock.

2. No feedback paths by combinational logic (See Figure 3-2.)

3. No pulse generation using the circuit delay (See Figure 3-3)

4. Asynchronous set/reset is not used other than system reset

In reality, it is difficult to operate all registers synchronously with one clock. However, it is strongly recommended to reduce the number of clock signals. The more clock signals are used and the more complicated relationships between signals exist, the longer time EDA tools need to be run, and less chance the tools output accurate results.

Figure 3-2 Examples of feedback loop



Figure 3-3 Pulse generation using delay

3.2 Differentiating Circuits are Prohibited The propagation delay time (tpd) of each LSI element is dependent on the operating environment (voltage, temperature, etc.) and manufacturing conditions. Therefore, in differentiating circuits using relative tpd differences as the one shown in Figure 3-4, pulse widths may not be enough under certain operating environments or manufacturing conditions, and circuit malfunctions may result.

When using differentiating circuits, do no use the circuit design shown in Figure 3-4. Use the circuit with flip-flops as the one shown in Figure 3-5.

Figure 3-4 Bad example of differentiating circuit

CLK

CK

D Q

XQ

CK

D Q

XQ

Figure 3-5 Differentiating circuit using flip-flops

D

C

Q

XQR

DFR



3.3 Clock Tree Synthesis

3.3.1 Outline

Epson offers the service of clock tree synthesis that automatically inserts a tree of buffers in order to optimize the clock skew and delay. Clock trees inserted by customers by themselves for clock line fan-out adjustment sometimes result in larger clock skew and delay. This is because the layout tool run later changes the layout of inserted buffers. To prevent this, customers are requested not to insert clock line buffers by themselves, but ask Epson to perform clock tree synthesis.

It is possible to optimize the skew and delay of gated clock lines as well.

For the clock tree synthesis service, Epson asks the customer to insert dedicated buffers or dedicated gating cells in clock lines for the following three reasons:

1. To decide the place to implement clock tree synthesis

2. To run pre-layout simulation, estimating the delay of clock tree buffers to be inserted

3. To back-annotate delay values to the inserted clock tree for running accurate post-layout simulation



3.3.2 Design Flow

P&R Clock Tree Synthesis

Post-layout netlist* SDF

Post-layout simulation

Post-layout simulation result Verify post-layout

simulation result

OK

NG

Circuit change Circuit verification

Netlist after circuit change

Pinout or

ppd ECO

(Enginnering Change Order)

Post-layout netlist*

Sign off

Clock Tree Synthesis Check Sheet

Initial netlist

Pinoutor

ppd

Customer Seiko Epson

(ECO is a technique to perform P&R only for places that require modifications.)

Notes:

• Post-layout netlists include buffers inserted by clock tree synthesis.

• To run post-layout simulation, netslists including buffers inserted by clock tree synthesis and sdf file are used.

• If the post-layout simulation result does not meet the design requirements, modify the post-layout netlists. If the initial netlists are modified, P&R needs to be iterated.

• If the circuits of clock nets (dedicated buffers, gating cells, and DFF) are modified, P&R needs to be iterated. If changes occurred to the clock nets, contact Epson.



3.3.3 How to implement

Select dedicated buffers for clock tree synthesis from Table 3-2, and dedicated gating cells for gated clock tree synthesis from Table 3-3. Insert the selected buffers and gating cells considering the constraints described in Section 3.3.4 and Reference circuit 1 shown below.

In the case of the circuits created by logic synthesis, dedicated buffers and gating cells are not automatically inserted. They must be directly written to netlists. Also, not to synthesize other buffers in the clock lines where dedicated buffers or gating cells are inserted, execute the following command of Design Compiler:

set_dont_touch_network clock_name

Table 3-1 Skew values for reference

Fan-out count Without gating cells With gating cells 0 to 500 ± 200ps ± 300ps

500 to 3000 ± 250ps ± 400ps 3000 to 10000 ± 300ps ± 500ps Over 10000 ± 350ps ± 600ps

Notes:

• Skew values vary depending on the circuit size, wire congestion, and clock count.

• Do not use gating cells in series. Up to 20 gating cells are allowed to use.

• The skew values shown for reference are for the case where gating cells are not used in series and the number is 20 or less.

• If multiple gating cells are used in series or the total number exceeds the limit, post-layout simulation may output timing errors due to skew. To prevent delay in the development schedule, minimize the number of gating cells.

Table 3-2 Dedicated buffers

S1L50000 Series

Cell name T0 Max (ns) Guideline number of fan-outs

CRBF1 1.00 0 to 200 CRBF1H 1.50 0 to 300 CRBF2 2.00 0 to 500 CRBF3 3.00 500 to 3000 CRBF4 4.00 3000 to 10000 CRBF5 5.00 Over 10000 CRBF6 6.00 CRBF7 7.00 CRBF8 8.00



Notes:

• The K value (delay due to fan-out) of these cells is set to 0 for pre-layout simulation.

• The fan-out value of these cells is set to infinite.

• Delay values relative to fan-out count vary depending on the design size and the utilization. Use the values only for reference.

Table 3-3 Dedicated gating cells

Circuit configuration (Function) Cell name AND CAD2P OR COR2P

2-1 selector AND-OR CAO24A NAND CNA2P NOR CNO2P

2-1 selector AND-NOR CAN24A INVERTER CPV2

Latch-based AND CLAD2V Latch-based OR CLOR2V

Latch-based AND with test pin CLPSAD2V Latch-based OR with test pin CLPSOR2V

Latch-based gating cells are offered among the gating cells. The benefit of using the latch-based gating cells is that glitches that occur when signals switch in clock lines do not propagate, and thus clock signal is stable.

For the latch-based gating cell function structure, see the S1L50000 Cell Library.

Notes:

• The delay values of these cells (T0) are set to 0 for pre-layout simulation.

• The K value (delay due to fan-out) of these cells is set to 0 for pre-layout simulation.

• The fan-out values of these cells are set to infinite.

3.3.4 Constraints and notes

• Implementing clock tree synthesis increases the gate count by 10 to 30%.

• If too many gating cells are used, timing errors due to skew may occur in the post-layout simulation. Minimize the number of gating cells not to delay the development schedule.

• Dedicated buffers and gating cells are usable only for clock tree synthesis.

• Clock tree synthesis is possible to implement on data lines and other control signals. However, the increase of synthesized nets results in larger skew and delay values. Therefore, confine the implementation of clock tree synthesis up to 10 nets, which are critical and have large fan-out values.

• Implementing clock tree synthesis on nets with small fan-out may increase delay and skew. Limit clock tree synthesis only to nets with more than some dozen fan-out values.



• Do not insert cells other than dedicated gating cells in the clock line. If cells other than dedicated gating cells are included in the clock line, skew occurs in the pre-layout simulation.

• Dedicated gating cells must be combined with dedicated buffers to use. If dedicated gating cells are used alone by mistake, skew and delay values are not optimized.

• As the number of dedicated gating cells inserted in one clock net increases, skew and delay values become larger. Up to 20 dedicated gating cells allowed.

• If multiple gating cells are used in series, skew and delay values increase. Do not use dedicated gating cells in series.

• The default skew adjustment covers cells with clock pin, such as DFF and latch cells. If skew must be adjusted for cells without clock pin, contact Epson.

• If the net covered by clock tree synthesis is connected to the input pin of a megacell, the skew up to the megacell input pin is adjusted.

• Do not use multiple dedicated buffers in series. If dedicated buffers are in clock nets, skew and delay values are not optimized.



3.3.5 Clock Tree Synthesis Check Sheet

To implement clock tree synthesis, the following information is required:

Target skew and delay values

Instance name of CRBF* Target Skew (Max.) (SIM condition: MAX)

Target Delay (Min./Max.) （SIM condition: MAX）

Notes:

• The target values will be used only as reference for synthesis. Care must be taken because the shown values are not guaranteed to meet.

1. The number of clock line is 10 or less Yes / No

2. Clock net has dedicated gating cell Yes / No If the answer to question 2 is “Yes,” answer questions 3 through 9.

3. The number of dedicated gating cells used in each clock net is 20 or less Yes / No

4. Dedicated gating cells are not used in series Yes / No

5. Clock net has dedicated buffer Yes / No

6. Clock net has cell other than dedicated gating cell Yes / No If the answer to question 6 is “Yes,” describe the cell name(s) below.

Notes: • If “3-input AND” is treated as a special gating cell, the cell is treated as a special gating cell

in all clock lines. • DFF and latch cells are not treated as special gating cells.

7. Skew adjustment on cells other than DFF and latch cells is desired Yes / No If the answer to question 7 is “Yes,” describe the cell name(s)/pin name(s) below.

Cell name: Pin name: Cell name: Pin name: Note:

• If the skew of an inverter is adjusted, the skew of inverter cells in all clock lines are adjusted.

8. The circuit configuration as the one shown in Reference circuit 2 exists. Yes / No Note:

• It is not possible to optimize the skew of DFF clock nets in both sections A and B. To adjust the skew of both DFF clock nets, add “CAO24A” as shown in Reference circuit 2.

9. The circuit configuration as the one shown in Reference circuit 3 exists. Yes / No Note:

• DFF in section A is driven by both clock roots A and B. It is not possible to adjust the skew of both clock roots. In Reference circuit 3, “CRBF” of clock root B must be deleted.



3.3.6 Reference

3.3.6.1 Circuits before and after clock tree synthesis

D

C

Q

XQ R

DFR

P

CAD2P

CRBF2 Clock Root

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

Before executing Clock Tree Synthesis

Clock tree synthesis optimizes the skew of the thick clock lines.

D

C

Q

XQ R

DFR

P

CAD2P

CRBF2 Clock Root

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

After executing Clock Tree Synthesis

Reference circuit 1

As shown in the above circuit, executing clock tree synthesis inserts buffers in the dotted circles.



3.3.6.2 Solution for problematic circuit 1

D

C

Q

XQ R

DFR

CAO24A

CRBF2 Clock Root A

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

Clock Root B CRBF2

Original circuit

D

C

Q

XQ R

DFR

CAO24A

CRBF2 Clock Root A

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

Clock Root B CRBF2

After modification

PDW

CAO24A

Dummy Cell ↓

Reference circuit 2

The DFFs in the dotted circle in the original circuit are driven by clock roots A and B. Clock tree synthesis is not applicable to circuits like this. In this case, insert dummy “CAO24A” as shown in the modified circuit. Clock tree synthesis optimizes the skew of thick clock lines shown in the above diagram.




D

C

Q

XQ R

DFR

CAO24A

CRBF2Clock Root A

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR Clock Root B CRBF2

Reference circuit 3

The DFFs in the dotted circle in the original circuit are driven by clock roots A and B. Clock tree synthesis is not applicable to circuits like this. In this case, delete the “CRBF” cell in clock root B.


D

C

Q

XQ R

DFR

P

CAD2P

CRBF2

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

D

C

Q

XQ R

DFR

CRBF2

Reference circuit 4



In the above circuit, two dedicated buffer cells, CRBF2 and CAD2P, are connected in series. Delete CRBF2 connected to CAD2P, as it is not required.



3.4 Designing High-Speed Circuits In high-speed operation (operating frequency higher than 60MHz), one cycle time is short and thus allowable propagation delay becomes small. Care must be taken for the following points in the design phase to minimize propagation delay values.

<To minimize propagation delay values>

• Avoid using NOR gates, but use NAND gates to build logic*1.

• Avoid using too many logic elements with multiple inputs*1.

• Use a tree structure at points where one element drives many nodes*2. Limit the number of nodes to drive to 10.

• For the output pins of logic elements driven at high speed (the operating frequency of 60MHz or higher) and circuits where very limited delay is allowed, reduce the fan-out values to one-half or one-third of typical values*2

• Use high drivability type logic elements for those connected to modules, macros and I/Os*2.

• Exclude the paths with ample timing margin from the design constraints. (Synthesis tools tend to start optimization from the paths most difficult to meet the constraints. Therefore, eliminating unnecessary timing constraints reduces the synthesis tool run time. If it is unavoidable that the circuit has a very small timing margin or timing errors, contact Epson in advance.)

NOTE: *1: Since high- and low-level drivability is different, NAND gates can build circuits with less delay time than NOR gates. Avoiding the use of logic elements with multiple inputs also help reduce delay time.

*2: In the actual layout of LSI circuit, load capacitance includes not only the input capacitance of the cell connected but also wire capacitance. Accurate wire capacitance is known only after the circuit layout, and a specific node may have large capacitance as the result of layout. To limit the increase in post-layout load capacitance, reduce the number branches driven by a single node.



3.5 Metastable In the case of FF and latch cell input signals, if they violate timing rules, such as clock and data setup time, hold time, and release or removal time of clock set and reset, the FF and latch cell output signals may go neither high or low level. This unstable state of output signals is called “metastable.”

The metastable state ends after some time and output signals enter the defined state of either high or low level. However, the defined levels are not dependent on the data input level, and thus outputs are in unknown state.

When setup/hold and release/removal timing specifications are not met, take appropriate measures to prevent the metastable state from propagating to the whole circuit.

In the S1L50000 Series, the metastable time is estimated by the following formula, when setup/hold, and release/removal time specifications are not met:

Metastable time = Tpd x 6

Where Tpd is the delay time from the active edge of FF, latch cell clock, set, and reset signals to output change.

Logic simulation does not consider the delay of signals in the metastable state. Ensure that the design meets the timing specifications.

Fugure 3-6 DF metastable state

D

C

Q

XQ CLOCK

Seup Hold

DATA

CLOCK

Output expected value: Q

Tpd

Output: Q Metastable state

Meatastable state/unknown state

DF

DATA Q

XQ



3.6 Internal Bus Configuration The bus circuit is composed of tri-state logic buffers. By operating the bus control signal, one of the outputs connected to the bus circuit is set active (other outputs are in the high-impedance state), and the one signal line is shared by allocating accessible time.

The following are the points to pay attention when building an internal bus circuit using internal tri-state buffers.

• Use bus cells only for bus circuits. (See Table 3-4 for the S1L50000 series bus cells)

• When building a bus, attach the bus latch cell BLT* to the bus.

• Among the bus cells connected to a bus, only one output is set active (0 or 1); other bus cell outputs must be set to high-impedance state (Z)*1.

• The fun-out of the bus cell connected to a bus must be the specified value or less*2.

• Bus circuits tend to increase propagation delay due to fan-out values and thus not suitable for high-speed operation*2.

• Data held by the bus latch cell should be used only to prevent floating; do not use it as a logic signal*3.

• Generate test patterns that can easily initialize bus circuits*4.

• The bus control signal is allowed to switch only once per cycle.

Notes: *1: If multiple bus cells connected to a bus are simultaneously become active (either 0 or 1), the output voltage level goes unstable and a flow-through current continually flows from VDD to GND. To avoid this, this rule must be met.

*2: If the load on the internal bus is large, the rising and falling times of signals extend due to longer wiring and more connections. This lowers the accuracy of logic simulation.

*3: Even when all the bus cells connected to a bus are set in the high-impedance state (Z), data is held by the bus latch cell. However, the latch function is limited not to affect the circuit in operation. Therefore, do not use the data held in the latch cell as valid data.

*4: Enhance testability by adding a test pin for better control of bus circuits or other means.

Table 3-4 S1L50000 Series Bus Cells

Cell nmae Cell type

1-bit 4-bit 8-bit

Bus latch BLT1 BLT4 BLT8

Bus driver TSB, TSBP T244H T244

Inverting bus driver TSV, TSVP T240H T240

Transparent latch with reset and 3-state output - T373H T373

D flip-flop with reset and 3-state output - T374H T374

1-bit RAM RM1 - -



TSB

TSB

BLT1

IN 1

NA2

Figure 3-7 Bus cell circuit example



3.7 Avoid Contention with External Bus When a gate array and other LSI are connected on a system by bus, possible solutions for bus contention, such as adding pull-up and pull-down registers, must be considered in addition to the notes described in the previous section, Internal Bus Configuration. Also, to prevent the external bus floating, IO cells with pull-up or pull-down resistor and those with bus-hold function* are available.If no measures are taken for bus contention, the input levels may be unstable, and cause erroneous operations and increase input current leakage.

* : Bus-hold circuit:

In the S1L50000 series library, IO buffers with bus-hold function that holds the output pin data are available to prevent output or bi-directional pins from going to the high-impedance state. However, the function to hold data is limited not to affect the normal operation. The data held by the bus-hold function is easily affected by external data if supplied. See the section of Electrical Characteristics for the output current held by the bus-hold circuit.

Output signal

Enable signal

Test pins Output pin

(a) Output buffer

Input signal

Output signal

Enable signal

Test pins

Bi-directional pin

(b) Bi-directional buffer

Figure 3-8 Example of bus-hold circuit symbol



3.8 Solution for Hazards In the case of circuits combining NAND and NOR gates or decoder cells, a very short pulse may occur because of the difference in timing delay of gates. This short pulse is called “hazard” and it causes erroneous operations if it is input to the clock or reset pin of flip-flops.

Therefore, care must be taken to design circuits that do not propagate hazards. When using a decoder circuit, for example, use the circuit with “enable” pin.

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

Figure 3-9 Solution examples for hazard

3.9 Oscillator Circuits

3.9.1 Oscillator circuit configurations

There are two types of cells dedicated to oscillation circuits. One is for the crystal oscillation and the other, for the CR oscillation. Further, the crystal oscillation circuits are divided into two types – continuous and intermittent types. Each type has those for the internal cell area and those for the I/O cell area. The following illustrates that the oscillation circuit configurations differ depending on the oscillator cell used.

G X

D

LIN LOT

Rf

X ’tal Rd

Cg Cd

Inside IC

OSC c ell

C ontinuous osc illation

G

E

X

D

LIN LOT

Rf

X ’tal Rd

Cg Cd

Inside IC

O SC cell

Interm itten t oscillation

Figure 3-10 Crystal oscillator circuits (for internal cell area)



RfX’tal

Rd

Cg

Cd

Inside IC

LIN

Oscillator cell

G

X

PAD

Continuous oscillation

Figure 3-11 Crystal oscillation circuit (for I/O cell area)

G X

R

C

LIN LOT LOT

R

C

Inside IC

Oscillator cell

Figure 3-12 CR oscillation circuit

3.9.2 Notes when using oscillator circuits

(1) Pinout

• Place the input and output pins of the oscillator circuit next to each other and enclose them with the power supply pins (VDD, VSS) on both sides.

• Place the input and output pins of the oscillator circuit away from other output pins, especially from those in-phase or out-of-phase of the oscillation waveform. Place such output pins on the opposite side of the package.

• Place the input and output pins of the oscillator circuit away from the input pins that operate at high speed, such as clock.

• Place the input and output pins of the oscillator circuit at the center of one of the four package sides.

• When multiple oscillator circuits are embedded, place them away from one another to prevent interference.



• When using an area array package such as BGA, contact our sales representative regarding the pinout.

(2) Test pattern generation

For how to generate test patterns for the circuit with an oscillator, refer to Section 8.5 of Chapter 8, “Notes When Using Oscillation Circuit.”

(3) How to select oscillator cells

The oscillation frequency ranges from several tens of KHz to several tens of MHz. For details, contact our sales representative.

(4) How to determine the external resistance and capacitance

The oscillator circuit characteristics are dependent on the elements of the circuit (IC, crystal, Rf, Rd, Cg, Cd, and the board). Therefore, determine the values of external Rf, Rd, Cg, and Cd, by mounting the components on the actual board and testing them fully.

(5) Guarantee level

The oscillator circuit characteristics are dependent on the elements of the circuit (IC, crystal, Rf, Rd, Cg, Cd, and the board). Therefore, Seiko Epson cannot guarantee the oscillation operation or characteristics. It is recommended that the customer spend ample time on the evaluation and confirm the oscillation characteristics using ES samples.

(6) Oscillator circuits with dual power supplies

The oscillator circuit configuration with dual power supplies is basically the same as that with single power supply. Since the oscillator cell is connected to LVDD power supply, use LLIN and LLOT for the LIN and LOT cells respectively.

(7) About the clock signal input to the IC internal circuit

Because it is difficult to specify the waveform of the clock signal to be generated (signal of the oscillator cell X) in advance, what the logic simulator can accurately handle is only the clock frequency. For example, the actual clock duty of the IC differs from the simulation result.

Therefore, avoid using the circuit utilizing both rising and falling times of the generated clock signal. Circuits with errors not detected by the simulation may be produced. Use the circuit only utilizing either rising or falling time of the generated clock signal.



3.10 Constraints on Verilog-HDL/VHDL Netlists The Verilog-HDL/VHDL netlists to be transferred to Epson for further design processes must be pure gate-level netlist (without functional or behavioral descriptions). The restrictions and constraints on the development of Epson ASICs using Verilog HDL/VHDL will follow.

3.10.1 Constraints on Verilog-HDL/VHDL netlists

1. External pin names (I/O pins)

• Use only uppercase letters

• Number of characters allowed: 2 to 32

• Bus descriptions are prohibited

• Legal characters: Alpha-numeric characters and underscore, _; only a letter of the alphabet is allowed to use for the initial character

• Examples of illegal character strings:

2INPUT: Starts with a numeric character

¥2INPUT: Starts with a symbol

InputA: Includes lowercase characters

_INPUTA: Starts with an underscore

INA [3:0]: Bus description

INA [3]: Bus description

2. Internal pin names (including bus nets)

Mixing uppercase and lowercase characters are allowed, but names must be unique; thus using both “RESET” and “Reset” is not allowed.

• Number of characters allowed: 2 to 32

• Legal characters: Alpha-numeric characters, underscore, _, and square brackets, [ ] (Verilog bus brackets), and parentheses, ( ) (VHDL bus brackets). Only uppercase characters for initial characters.

3. Module names

Module names are case-sensitive on the system, but mixing uppercase and lowercase characters is prohibited by the design rule.

e.g. “TOPMODULE” and “TopModule”

Pay attention to cell names as they are case-sensitive.

4. Bus description is prohibited in the top module.

e.g. DATA [0:3], DATA [3], DATA[2] are prohibited. DATA0, DATA1, DATA2 are allowed.

5. Keep using the same series library for IO cells throughout the design; do not mix other series IO cells.

6. Behavioral, RTL, and C language descriptions are not allowed. Such descriptions in netlists are invalid.

7. The time scale accuracy of library is 1 ps in all series.



3.10.2 Constraints on Verilog netlists

1. The “assign” and “tran” statements are prohibited in the gate-level Verilog netlist.

2. Use cell pin names to describe connections in the Verilog netlists.

e.g.

Legal: IN2 inst_1 (.A(inst_2),.X(inst_3)); Illegal: IN2 inst_1 (net1,net2);

3. Verilog commands such as “force” are not allowed to describe the behavior of flip-flops. e.g. force logic.signal = 0;

4. The time scale is described at the head of the gate-level netlists compiled by the Synopsys Design Compiler. For this time scale, describe the value shown in the Seiko Epson’s Verilog library. The time scale is 1 ps in all series.

e.g. `timescale 1ps/1ps

5. Single port bus names and those with “escape” character (¥) are not allowed to use together in the same module by the Epson design rules.

e.g. input A[0]; wire ¥A[0];

6. The following character strings are Verilog reserved words and thus prohibited to use as user defined names.

always and assign begin buf bufif0 bufif1 case design default defparam disable else end endcase endfunction endmodule endtask event for force forever fork function highz0 highz1 if initial inout input integer join large medium module nand negedge nor not notif0 notif1 or output parameter posedge pull0 pull1 reg release repeat scalared small specify strong0 strong1 supply0 supply1 task time tri tri0 tri1 trinand trior trireg vectored wait wand weak0 weak1 while wire wor xor xnor



3.10.3 Constraints on VHDL netlists

1. In addition to the constraints listed in Section 3.10.1, the following character strings are prohibited to use. Since Epson uses TEXTIO package to run simulation, the function names used by the TEXTIO package are prohibited to use for user definitions.

INPUTA_: Ends with an underscore, _

INPUT_ _A: Uses two consecutive underscores, _ _

Read: Used by TEXTIO package

Write: Used by TEXTIO package

2. The following character strings are VHDL reserved words and thus prohibited to use as user defined names.

abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop map mod nand new next nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to transport type units until use variable wait when while with xor

3. To use Epson’s tools and utility programs, VHDL format files must be converted into Verilog format. Therefore, the Verilog reserved words listed in Section 3.10.2 are also prohibited.

3.10.4 About descriptions of oscillator cells and AC/DC test circuit cell (TCIR2)

Instantiate oscillator cells and add the “dont_touch” attribute using the “set_dont_touch” command to the input and output nets to prevent the synthesis tool from inserting buffers to the nets connecting the external pins of the oscillator cells.

Since the AC/DC test circuit cell, TCIR2, is a hard macro, gate descriptions as those shown below are required:

---VerilogHDL description example--- OSC1 inst1 (.G(gate_in), .D(drain_out), .X(clk_out) ); TCIR2 inst2 (.TM0(i_net0), .TM1(i_net1), .TM2(i_net2), .TM3(i_net3), .TST(i_net4), .MS(MS), .TD(TD), .TE(TE), .TS(TS), .TAC(TAC) ); ---VHDL description example--- inst1 : OSC1 port map (G＝> gate_in, D＝> drain_out, X＝> clk_out);



inst2 : TCIR2 port map (TM0＝> i_net0, TM1＝> i_net1, TM2＝> i_net2, TM3＝> i_net3, TST＝> i_net4, MS＝> MS, TD＝> TD, TE＝> TE, TS＝> TS, TAC＝> TAC );

3.10.5 About descriptions of clock root buffers

Insert the clock root buffer in the highest possible level in the design hierarchy and do not connect multiple gated cells in series.

In the RTL description, directly describe gated cells for clock root buffers and gated cells.

For the RTL simulation using Epson’s gate library, generate test patterns with sufficient delay, because the clock root buffers have some delay.

-----Verilog description---------- module TOP (CLK, RESET, ....., ); input CLK, RESET, ... ; output OUT1, OUT2, ... ; LIBC pad1 (.PAD(CLK), .X(iCLK) ); CRBF2 U0_L1CRBF2 (.A(iCLK), .X(wCLK) ); . . CLKGEN U_CLKGEN (.CLK(wCLK), .ACLK(ACLK), .BCLK(BCLK) ...); AIF U_AIF (.ACLK(ACLK), .....); BIF U_BIF (.BCLK(BCLK), .....); endmodule module CLKGEN (CLK, ACLK, BCLK); input CLK; output ACLK, BCLK ; CAD2P GATEDCLKAND0 (.A1(CLK), .A2(A_gate),.X(ACLK) ); CAD2P GATEDCLKAND1 (.A1(CLK), .A2(B_gate),.X(BCLK) ); ... endmodule --------VHDL description--------- library IEEE; library s1l50000_typ; use IEEE.std_logic_1164.all; use s1l50000_typ.primitives_tables.all; use s1l50000_typ.mos_switches.all;



entity TOP is port ( CLK ; in std_logic ; RESET ; in std_logic ; ... ); end TOP; architecture RTL of TOP is component LIBC port (PAD : in std_logic; X: out std_logic); end component; component CRBF2 port (A : in std_logic; X: out std_logic); component CLKGEN port ( CLK, ACLK, BCLK : in std_logic; ... ); end component; component AIF port (.... ); end component; signal wCLK, .....; begin PAD1 : LIBC port map ( PAD＝> CLK, X＝> iCLK ); PAD2 : U_CLKGEN : CLKGEN port map ( CLK＝> wCLK, ACLK＝> ACLK, ... ); U_AIF : AIF port map (ACLK＝> ACLK, ... ); end RTL;

Chapter 4 Types of I/O Buffers and Notes on Use


Chapter 4 Types of I/O Buffers and Notes on Use This chapter describes in detail how to configure input, output, and bi-directional I/O buffers of the S1L50000 Series gate arrays.

4.1 Types of I/O Buffers A variety of I/O buffers are available for the S1L50000 Series gate arrays. In addition to selectable input interface levels, output drive capability, and noise margin, buffers with Schmitt-trigger input, pull-up or pull-down resistor are available. Paying attention to the points described below, select optimum I/O buffers. It should be also noted that I/O buffers are usable in both single- (3.3 V or 2.0V) and dual- power supply applications (5.0V/3.3V or 3.3V/2.0V).

4.1.1 Selection of I/O buffers

(1) For input buffer selection, consider the following:

a) Desired interface level: CMOS or TTL

b) Schmitt-trigger input is required or not (Hysteresis is required or not)

c) Pull-up or pull-down resistor is required or not

(2) For output buffer selection, consider the following:

a) Required output drive current (IOL/IOH)

b) Provision for noise immunity

c) Bus-hold circuit

(3) For bi-directional buffer selection:

Consider both cases where the buffer is used for an input and an output

• Input interface level

i. Dual power supply (5.0V)

Input levels: TTL, CMOS, TTL Schmitt, CMOS Schmitt, PCI*

Output levels: CMOS and PCI*

ii. Single power supply and dual power supply (3.3V)

Input levels: LVTTL, LVTTL Schmitt, PCI*

Output levels: LVTTL, PCI*



iii. Single power supply and dual power supply (2.0V)

Input levels: CMOS, CMOS Schmitt

Output level: CMOS

NOTE : The TTL level input is not allowed in single power supply operation (3.3V or 2.0V). Contact Epson sales representative for the PCI interface.

• Output drive capability

Refer to the Electrical Characteristics (Tables 1-8 to 1-10)

• Pull-up/pull-down resistors

Refer to the Electrical Characteristics (Tables 1-8 to 1-10)

4.1.2 Bus Hold Circuit

The I/O buffers with bus hold function are available for the S1L50000 Series gate arrays. The bus hold function is to hold the data on output pins to keep the output pins or bi-directional pins from going to the high impedance state. However, the function of the bus hold circuit is restrained so that it may not affect other normal operations. Therefore, do not use the data output held by the bus hold circuit as valid data. The data is easily affected by external data if supplied. For the output bus hold current, refer to Tables 1-8 to 1-10.

4.2 I/O Buffers for Single Power Supply Operation When using the I/O buffers in the single power supply operation, the supply voltage allowed is 3.3V or 2.0V only. Do not use them at 5.0V.

4.2.1 Input Buffers

Table 4-1 Specifications of Pull-up and Pull-down Resistors

Resistance Pull-up/Pull-down Resistors

VDD = 3.3V VDD = 2.0V Unit

Type 1 50 120 kΩ

Type 2 100 240 kΩ



Table 4-2 Input Buffers (VDD = 3.3V)

Cell Name*1 Input Level Pull-up/Pull-down Resistors

IBC IBCP# IBCD#

LVTTL LVTTL LVTTL

N/A Pull-up resistor

Pull-down resistor

IDC *2 IDCD# *2

LVTTL LVTTL

N/A Pull-down resistor

IBH IBHP# IBHD#

LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt


Pull-down resistor

IDH *2 IDHD# *2

LVTTL Schmitt LVTTL Schmitt


IBPB IBPBP# IBPBD#

PCI-3V PCI-3V PCI-3V


Pull-down resistor

NOTE: *1: The # symbol represents a “Type” indicator, 1 or 2. For the cell names ended with “1,” Type 1 resistor is available, and for those ended with “2,” Type 2 resistor is available. (For the resistance specified for each Type, see Table 4-1.)

*2: 5V input is allowed.

Table 4-3 Input Buffers (VDD = 2.0V)

Cell Name*1 Input Level Pull-up/Pull-down Resistors

IBC IBCP# IBCD#

CMOS CMOS CMOS


Pull-down resistor

IDC *2 IDCD# *2

CMOS CMOS


IBH IBHP# IBHD#

CMOS Schmitt

CMOS Schmitt CMOS Schmitt


Pull-down resistor

IDH *2 IDHD# *2




*2: 5V input is allowed.



4.2.2 Output Buffers

Tables 4-5 and 4-6 are the listings of output buffers.

Table 4-4 Specifications of IOH and IOL

IOH*1/IOL

*2 Output Current

VDD = 3.3V VDD = 2.0V Unit

Type S -0.1/0.1 -0.05/0.05 mA

Type M -1/1 -0.3/0.3 mA

Type 1 -2/2 -0.6/0.6 mA

Type 2 -6/6 -2/2 mA

Type 3 -12/12 -4/4 mA

NOTE: *1: VOH = VDD-0.4V(VDD = 3.3V) or VDD-0.2V(VDD = 2.0V) *2: VOL = 0.4V(VDD = 3.3V) or 0.2V(VDD = 2.0V)

Table 4-5 Output Buffers (VDD = 3.3V)

NOTE: *1: The # symbol or $ mark represents a “Type” indicator (S, M, 1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL/IOH of Type S, M, 1, 2, or 3 specified in Table 4-4.

*2: In addition to the cells shown in Table 4-5, those without test pins are available. If cells without test pins are desired, contact your Epson sales representative.

Function IOH/IOL Cell Name*1, *2

Normal output

Type S Type M Type 1 Type 2 Type 3

OB#T

Output for PCI PCI-3V OBPBT

Normal output for high speed Type 1 Type 2 Type 3

OB1CT OB2CT OB3AT

Normal output for low noise Type 3 OB3BT

3-state output


TB#T

3-state output for PCI PCI-3V TBPBT

3-state output for high speed Type 1 Type 2 Type 3

TB1CT TB2CT TB3AT

3-state output for low noise Type 3 TB3BT

3-state output (Bus hold circuit)

Type M Type 1 Type 2 Type 3

TB$HT

3-state output for high speed (Bus hold circuit) Type 1 Type 2 Type 3

TB1CHT TB2CHT TB3AHT

3-state output for low noise (Bus hold circuit) Type 3 TB3BHT



Table 4-6 Output Buffers (VDD = 2.0V)


Normal output


OB#T

Normal output for high speed Type 1 Type 2 Type 3

OB1CT OB2CT OB3AT

Normal output for low noise Type 3 OB3BT

3-state output


TB#T


TB1CT TB2CT TB3AT

3-state output for low noise Type 3 TB3BT



TB$HT

3-state output for high speed (Bus hold circuit) Type 1 Type 2 Type 3

TB1CHT TB2CHT TB3AHT

3-state output for low noise (Bus hold circuit) Type 3 TB3BHT

NOTE: *1: The # symbol or $ mark represents a “Type” indicator (S, M, 1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOH/IOL of Type S, M, 1, 2, or 3 specified in Table 4-4.




Table 4-7 Specifications of N-Channel Open Drain Output Buffers, IOL

IOL*1

Output Current VDD = 3.3V VDD = 2.0V

Unit

Type 1 2 0.6 mA

Type 2 6 2 mA

Type 3 12 4 mA

NOTE: *1: VOL = 0.4V (VDD = 3.3V) or VDD - 0.2V (VDD = 2.0V)

Table 4-8 N-Channel Open Drain Output Buffers

Function IOL Cell Name*1, *2

Normal output Type 1 Type 2 Type 3

OD#T

High speed output Type 1 Type 2 OD$T

NOTE: *1: The # symbol or $ mark represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL of Type 1, 2, or 3 specified in Table 4-7.




4.2.3 Bi-Directional Buffers

Tables 4-9 and 4-10 are the listings of bi-directional buffers.

Table 4-9 Bi-Directional Buffers (VDD = 3.3.V)

Input Level Function IOH/IOL Cell Name*1, *2

Bi-directional output


BC#T

Bi-directional output for high speed Type 1 Type 2 Type 3

BC1CT BC2CT BC3AT

LVTTL

Bi-directional output for low noise Type 3 BC3BT PCI-3V Bi-directional output for PCI PCI-3V BPBT



BH#T


BH1CT BH2CT BH3AT

LVTTL Schmitt

Bi-directional output for low noise Type 3 BH3BT

Bi-directional output (Bus hold circuit)


BC$HT

Bi-directional output for high speed (Bus hold circuit)

Type 1 Type 2 Type 3

BC1CHT BC2CHT BC3AHT

LVTTL

Bi-directional output for low noise (Bus hold circuit) Type 3 BC3BHT



BH$HT



BH1CHT BH2CHT BH3AHT

LVTTL Schmitt

Bi-directional output for low noise (Bus hold circuit) Type 3 BH3BHT

NOTE: *1: The # symbol or $ mark represents a “Type” indicator (S, M, 1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to IOH/IOL of Type S, M, 1, 2, or 3 specified in Table 4-4.

*2: In addition to the cells shown in Table 4-9, cells with pull-up or pull-down resistor and those without test pins are available. If cells without test pins are desired, contact your Epson sales representative.



Table 4-10 Bi-Directional Buffers (VDD = 2.0V)




BC#T


BC1CT BC2CT BC3AT

LVTTL

Bi-directional output for low noise Type 3 BC3BT PCI-3V Bi-directional output for PCI PCI-3V BPBT



BH#T


BH1CT BH2CT BH3AT

LVTTL Schmitt

Bi-directional output for low noise Type 3 BH3BT



BC$HT



BC1CHT BC2CHT BC3AHT

LVTTL

Bi-directional output for low noise (Bus hold circuit) Type 3 BC3BHT



BH$HT



BH1CHT BH2CHT BH3AHT

LVTTL Schmitt

Bi-directional output for low noise (Bus hold circuit) Type 3 BH3BHT





Table 4-11 N-Channel Open Drain Bi-Directional Buffers (VDD = 3.3V)

Input Level Function IOL Cell Name*1, *2


Type 1 Type 2 Type 3 BDC#T

LVTTL

Bi-directional output for high speed Type 1 Type 2 BDC$CT


Type 1 Type 2 Type 3 BDH#T

LVTTL Schmitt

Bi-directional output for high speed Type 1 Type 2 BDH$CT



Table 4-12 N-Channel Open Drain Bi-Directional Buffers (VDD = 2.0V)



Type 1 Type 2 Type 3 BDC#T

CMOS

Bi-directional output for high speed Type 1 Type 2 BDC$CT


Type 1 Type 2 Type 3 BDH#T

CMOS Schmitt

Bi-directional output for high speed Type 1 Type 2 BDH$CT





4.2.4 Fail-Safe Cells

4.2.4.1 Outline

The S1L50000 Series fail-safe cells for single power supply designs provide the means for interfacing to voltage levels higher than specified value; no dedicated power supply interface is required. Fail-safe cells also prevent current leakage when external signals are input to the off-state IC and thereby provide the designer with even greater design flexibility.

4.2.4.2 Features

(1) No constraints on cell count and placement provide the designer with great flexibility to meet the customer’s layout requirement.

(2) No input leakage current flows when the input signal exceeding the power supply voltage is applied to the on-state IC.

(3) No input leakage current flows when an external input signal is applied to the off-state IC.

(4) Two types of input levels are available: LVTTL/LVTTL Schmitt levels (VDD = 3.3V) and CMOS/CMOS Schmitt levels (VDD = 2.0V)

(5) Low power consumption by the full CMOS architecture

4.2.4.3 Notes on Use

(1) A separate test circuit is needed. Create a test circuit, referring to the sample shown in Figure 4-1.

(2) When the output buffer is in the high-Z state, or the bi-directional buffer is in the input mode, no input leakage current occurs even if the signal exceeding the power supply voltage is input while the supply voltage is applied to the IC.

(3) In the output mode, if a signal exceeding the power supply voltage is input, input leakage current flows, as in universal IO buffers. Care must be taken because this also happens when an external pull-up resistor connected to the supply voltage greater than the IC operating voltage exists. (When the “High” level voltage higher than the supply voltage is required, use an open-drain type IO buffer and raise the voltage level to the “High” level by an external pull-up resistor.)

(4) It is possible to receive signals in the voltage level higher than the IC operating voltage, but care must be taken because the signal voltage possible to apply to the fail-safe cells cannot exceed the absolute maximum rating.



4.2.4.4 Cell Listing

Table 4-13 Fail-Safe Input Buffers

Cell Name*1 *2 Input Level Pull-up Resistor

IBBP# CMOS Available

NOTE: *1: The # symbol represents a “Type” indicator, 1 or 2. For the cell name ended with “1,” Type 1 resistor is available, and for that ended with “2,” Type 2 resistor is available. (For the resistance specified for each Type, see Table 4-1.)

Table 4-14 Fail-Safe Output Buffers

Function IOH/IOL Cell Name*1

3-state output Type 1 Type 2 TBF#


TBF1C TBF2C TBF3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to the IOH/IOL of Type 1or 2 specified in Table 4-4.

Table 4-15 Fail-Safe Bi-directional Buffers (VDD = 3.3V)


Bi-directional output Type 1 Type 2 BB#

LVTTL Bi-directional output for high speed


BB1C BB2C BB3A

Bi-directional output Type 1 Type 2 BG#

LVTTL Schumitt


BG1C BG2C BG3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to the IOH/IOL of Type 1 or 2 specified in Table 4-4.

*2: In addition to the cells shown in Table 4-15, those with pull-up or pull-down resistor are available.



Table 4-16 Fail-Safe Bi-directional Buffers (VDD = 2.0V)


Bi-directional output Type 1 Type 2 BB#

CMOS Bi-directional output for high speed


BB1C BB2C BB3A

Bi-directional output Type 1 Type 2 BG#

CMOS Schumitt


BG1C BG2C BG3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to IOH/IOL of Type 1 or 2 specified in Table 4-4.




4.2.5 Gated Cells

4.2.5.1 Outline

The S1L50000 Series gated I/O cell allows the designer to set the input pin to the floating state, i.e., to the high-Z state, without using the pull-up or pull-down resistor circuit, which was not possible in the past. The gated I/O cell can also cut off the high voltage power supply (HVDD) in dual power supply designs. Two types of control signals are available: one that cuts off the current flow at the high level voltage and the other, at the low level voltage. Either type is selectable according to the design need.

4.2.5.2 Features

(1) No constraints on cell count and placement provide the designer with great flexibility to meet the customer’s layout requirement.

(2) Possible to cut off the high voltage power supply (HVDD) in dual power supply designs. However, special care must be taken for cutting off the high-level voltage supply. When doing so, please contact your Epson sales representative.

(3) Possible to set the input to the high-Z state without using the pull-up or pull-down circuit.

(4) The input level of gated I/O cells for dual power supply design is not HVDD, but the CMOS level of LVDD because of its circuit configuration.

(5) Two types of control signals are available: one for cutting off the current flow at the high level voltage and the other, at the low level voltage

(6) Low power consumption by the full CMOS architecture

4.2.5.3. Notes on Use

(1) To check input levels, a separate test circuit is required. Develop a test circuit referring to the sample shown in Figure 4-1.

(2) To set the input to the high-Z state using the gated I/O cell, cut off the signal from the input pin using the control signal of the gated I/O cell before the input pin goes to the high-Z state. Without taking this process, if the input pin goes to the high-Z state, very high current flows as it does in the universal type cells, and destroys the gated I/O cell. The same is true if the control signal allows the signal from the input pin while the input is still in the high-Z state. Logic levels read into the device in these cases are not guaranteed.

(3) When cutting off the high voltage power supply (HVDD) using the gated I/O cell, the steps described in (2) need to be taken. If not, logic levels read into the device are not guaranteed. When cutting off the power supply using gated I/O cells, contact your Epson sales representative, since special care must be taken.




Table 4-17 Gated Input Buffers

Cell Name*1 *2 Input Level Pull-up Resistor

IBA IBAP# IBAD#

AND Type LVTTL (VDD = 3.3V)

CMOS (VDD = 2.0V)


Pull-down resistor

IBO IBOP# IBOD#

OR Type LVTTL (VDD = 3.3V) CMOS (VDD = 2.0V)


Pull-down resistor


Table 4-18 Gated Bi-directional Buffers


Bi-directional output Type 1 Type 2 Type 3

BA#T


BA1CT BA2CT BA3AT

AND Type

Bi-directional output for low noise Type 3 BA3BT


BO#T


BO1CT BO2CT BO3AT

LVTTL (VDD = 3.3V) CMOS (VDD = 2.0V)

OR Type

Bi-directional output for low noise Type 3 BO3BT

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to IOH/IOL of Type 1, 2, or 3 specified in Table 4-4.




Figure 4-1 Example of Test Circuit including Fail-safe and Gated I/O Cells



4.3 I/O Buffers for Dual Power Supply Operation For dual power supply designs, use I/O buffers dedicated to dual power supply designs. (I/O buffers for single power supply designs are not usable.)

Also, mixing of I/O buffers for single and dual power supply is not allowed, though the test I/O buffer (ITST1) is valid for both dual and single power supply designs.

(1) HVDD I/O buffers

There are following HVDD I/O buffers: 5.0V signal input buffer, 5.0V oscillation signal output buffer, and bi-directional buffer that inputs 5.0V signal and outputs 5.0V oscillation signal.

(2) LVDD I/O buffers

There are following LVDD I/O buffers: 3.3V (or 2.0V) input buffer, 3.3V (or 2.0V) oscillation signal output buffer, and bi-directional buffer that inputs 3.3V (or 2.0V) and outputs 3.3V (or 2.0V) oscillation signal. If high voltage (HVDD) signal is input to low voltage (LVDD) bi-directional buffer, excessive current flows through the protection diode within the LVDD buffers, and this lowers the quality. So do not apply voltage higher than LVDD to low voltage bi-directional buffers. (In this case, use fail-safe cells described in Chapter 4, Section 4.3.4, Fail-safe cells.)

4.3.1 Input Buffers

(1) HVDD input buffers

Input buffers are configured only with input cells. The HVDD input buffers have the high voltage (HVDD) input circuit connected to the input of low voltage (LVDD) circuit, and supply signals to the MSI cells (internal cell area), converting HVDD signals to LVDD signals. Table 4-20 is the listing of HVDD input buffers.



HVDD = 5.0V HVDD = 3.3V Unit

Type 1 60 100 KΩ

Type 2 120 200 KΩ



Table 4-20 HVDD Input Buffers (HVDD = 5 .0V)

Cell Name*1, Input Level Pull-up/Pull-down Resistors

HIBC HIBCP# HIBCD#

CMOS CMOS CMOS


Pull-down resistor

HIBT *2 HIBTP# *2 HIBTD# *2

TTL TTL TTL


Pull-down resistor

HIBH HIBHP# HIBHD#

CMOS Schmitt CMOS Schmitt CMOS Schmitt


Pull-down resistor

HIBS *2 HIBSP# *2 HIBSD# *2

TTL Schmitt TTL Schmitt TTL Schmitt


Pull-down resistor

HIBPA *2 HIBPAP# *2 HIBPAD# *2



Pull-down resistor


*2: Cells dedicated to HVDD = 5.0V power supply

Table 4-21 HVDD Input Buffers (HVDD = 3.3V)


HIBC HIBCP# HIBCD#

LVTTL LVTTL LVTTL


Pull-down resistor

HIBH HIBHP# HIBHD#

LVTTL LVTTL LVTTL


Pull-down resistor

HIBPB HIBPBP# HIBPBD#



Pull-down resistor




Table 4-22 HVDD Input Level Shifters (HVDD = 5.0V)


HIDC HIDCD#

CMOS CMOS


HIDH HIDHD#




Table 4-23 HVDD Input Level Shifters (HVDD = 3.3V)


HIDC HIDCD#

LVTTL LVTTL


HIDH HIDHD#

LVTTL Schmitt LVTTL Schmitt



(2) LVDD Input Buffers

The input buffers are configured with only input cells. The LVDD input buffers are shown in Table 4-25.



LVDD = 3.3V LVDD = 2.0V Unit

Type 1 50 120 KΩ

Type 2 100 240 KΩ



Table 4-25 LVDD Input Buffers (LVDD = 3.3V)


LIBC LIBCP# LIBCD#

LVTTL LVTTL LVTTL


Pull-down resistor

LIBH LIBHP# LIBHD#

LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt


Pull-down resistor


Table 4-26 LVDD Input Buffers (LVDD = 2.0V)


LIBC LIBCP# LIBCD#

CMOS CMOS CMOS


Pull-down resistor

LIBH LIBHP# LIBHD#

CMOS Schmitt CMOS Schmitt CMOS Schmitt


Pull-down resistor


4.3.2. Output Buffers

(1) HVDD Output Buffers

Tables 4-28 to 4-31 are listings of HVDD output buffers.


IOH*1/IOL

*2 Output Current

HVDD = 5.0V HVDD = 3.3V Unit

Type S -0.1/0.1 -0.1/0.1 mA

Type M -1/1 -1/1 mA

Type 1 -3/3 -2/2 mA

Type 2 -8/8 -6/6 mA

Type 3 -12/12 -12/12 mA

Type 4 -12/24 - mA

NOTE: *1: VOH = HVDD-0.4V

*2: VOL = 0.4V



Table 4-28 HVDD Output Buffers (HVDD = 5.0V)

Function IOL/IOH Cell Name*1, *2

Normal output

Type S Type M Type 1 Type 2 Type 3 Type 4

HOB#T

Normal output for high speed Type 3 Type 4

HOB3AT HOB4AT

Normal output for low noise Type 3 Type 4

HOB3BT HOB4BT

Normal output for PCI PCI-5V HOBPAT

3-state output


HTB#T

3-state output for high speed Type 3 Type 4

HTB3AT HTB4AT

3-state output for low noise Type 3 Type 4

HTB3BT HTB4BT

3-state output for PCI PCI-5V HTBPAT


Type M Type 1 Type 2 Type 3 Type 4

HTB$HT

3-state output for high speed (Bus hold circuit) Type 3 Type 4

HTB3AHT HTB4AHT

3-state output for low noise (Bus hold circuit) Type 3 Type 4

HTB3BHT HTB4BHT





Table 4-29 HVDD Output Buffers (HVDD = 3.3V)


Normal output


HOB#T

Normal output for high speed Type 3 HOB3AT Normal output for low noise Type 3 HOB3BT Normal output for PCI PCI-3V HOBPBT

3-state output


HTB#T

3-state output for high speed Type 3 HTB3AT 3-state output for low noise Type 3 HTB3BT 3-state output for PCI PCI-3V HTBPBT



HTB$HT

3-state output for high speed (Bus hold circuit) Type 3 HTB3AHT 3-state output for low noise (Bus hold circuit) Type 3 HTB3BHT



Table 4-30 HVDD N-Channel Open Drain Output Buffers (HVDD = 5.0V)


Normal output

Type 1 Type 2 Type 3 Type 4

HOD#T

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, 3, or 4), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL/IOH of Type 1, 2, 3, or 4 specified in Table 4-27.




Table 4-31 HVDD N-Channel Open Drain Output Buffers (HVDD = 3.3V)



HOD#T

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL/IOH of Type 1, 2, or 3 specified in Table 4-27.


(2) LVDD Output Buffers

Tables 4-33 to 4-36 are listings of LVDD output buffers.


IOH*1/IOL

*2 Output Current

LVDD=3.3V LVDD=2.0V Unit

Type S -0.1/0.1 -0.05/0.05 mA Type M -1/1 -0.3/0.3 mA Type 1 -2/2 -0.6/0.6 mA Type 2 -6/6 -2/2 mA Type 3 -12/12 -4/4 mA

NOTE: *1: VOH = LVDD-0.4V(LVDD = 3.3V)or LVDD-0.2V(LVDD = 2.0V)

*2: VOL = 0.4V(LVDD = 3.3V)or 0.2V(LVDD = 2.0V)



Table 4-33 LVDD Output Buffers (LVDD = 3.3V)


Normal output


LOB#T

Normal output for high speed Type 3 LOB3AT Normal output for low noise Type 3 LOB3BT Normal output for PCI PCI-3V LOBPBT

3-state output


LTB#T

3-state output for high speed Type 3 LTB3AT 3-state output for low noise Type 3 LTB3BT Normal output for PCI PCI-3V LTBPBT



LTB$HT

3-state output for high speed (Bus hold circuit) Type 3 LTB3AHT 3-state output for low noise (Bus hold circuit) Type 3 LTB3BHT





Table 4-34 LVDD Output Buffers (LVDD = 2.0V)


Normal output


LOB#T

Normal output for high speed Type 3 LOB3AT Normal output for low noise Type 3 LOB3BT

3-state output


LTB#T

3-state output for high speed Type 3 LTB3AT 3-state output for low noise Type 3 LTB3BT



LTB$HT

3-state output for high speed (Bus hold circuit) Type 3 LTB3AHT 3-state output for low noise (Bus hold circuit) Type 3 LTB3BHT



Table 4-35 LVDD N-Channel Open Drain Output Buffers (LVDD = 3.3V)

Function IOL Cell Name*1, *2


LOD#T

High speed output Type 1 Type 2 LOD#CT

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL of Type 1, 2, or 3 specified in Table 4-32.


Table 4-36 LVDD Fail-Safe Output Buffers (LVDD = 3.3V)

Function IOL Cell Name*1

Normal output Type 1 Type 2 LTBF#

High speed output Type 1 Type 2 Type 3

LTBF1C LTBF2C LTBF3A




4.3.3 Bi-Directional Buffers

(1) HVDD Bi-Directional Buffers

Tables 4-37 to 4-41 are the listings of HVDD bi-directional buffers.

Table 4-37 HVDD Bi-Directional Buffers (1/2) (HVDD = 5.0V)




HBT#T

Bi-directional output for high speed Type 3 Type 4

HBT3AT HBT4AT

TTL

Bi-directional output for low noise Type 3 Type 4

HBT3BT HBT4BT



HBC#T


HBC3AT HBC4AT

CMOS


HBC3BT HBC4BT

PCI Bi-directional output for PCI PCI-5V HBPAT



HBS#T


HBS3AT HBS4AT

TTL Schmitt


HBS3BT HBS4BT



HBH#T


HBH3AT HBH4AT

CMOS Schmitt


HBH3BT HBH4BT

NOTE: *1: The # symbol represents a “Type” indicator (S, M, 1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOH/IOL of Type S, M, 1, 2, or 3 specified in Table 4-27.




Table 4-38 HVDD Bi-Directional Buffers (2/2) (HVDD = 5.0V)




HBT#HT


Type 3 Type 4

HBT3AHT HBT4AHT

TTL

Bi-directional output for low noise (Bus hold circuit)

Type 3 Type 4

HBT3BHT HBT4BHT



HBC#HT


Type 3 Type 4

HBC3AHT HBC4AHT

CMOS


Type 3 Type 4

HBC3BHT HBC4BHT



HBS#HT


Type 3 Type 4

HBS3AHT HBS4AHT

TTL Schmitt


Type 3 Type 4

HBS3BHT HBS4BHT



HBH#HT


Type 3 Type 4

HBH3AHT HBH4AHT

CMOS Schmitt


Type 3 Type 4

HBH3BHT HBH4BHT





Table 4-39 HVDD Bi-Directional Buffers (HVDD = 3.3V)




HBC#T

Bi-directional output for high speed Type 3 HBC3AT

LVTTL

Bi-directional output for low noise Type 3 HBC3BT PCI Bi-directional output for PCI PCI-3V HBPBT



HBH#T

Bi-directional output for high speed Type 3 HBH3AT

LVTTL Schmitt

Bi-directional output for low noise Type 3 HBH3BT



HBC#T

Bi-directional output for high speed (Bus hold circuit) Type 3 HBC3AHT

LVTTL

Bi-directional output for low noise (Bus hold circuit) Type 3 HBC3BHT



HBH#HT

Bi-directional output for high speed (Bus hold circuit) Type 3 HBH3AHT

LVTTL Schmitt

Bi-directional output for low noise (Bus hold circuit) Type 3 HBH3BHT





Table 4-40 HVDD N-Channel Open Drain Bi-Directional Buffers (HVDD = 5.0V)


TTL Bi-directional output


HBDT#T

CMOS Bi-directional output


HBDC#T

TTL Schmitt Bi-directional output


HBDS#T

CMOS Schmitt Bi-directional output


HBDH#T


*2: In addition to those in Table 4-40, configurations without a test terminal are also possible. If configurations without a test terminal are desired, contact our sales representative.

Table 4-41 HVDD N-Channel Open Drain Bi-Directional Buffers (HVDD = 3.3V)


LVTTL Bi-directional output Type 1 Type 2 Type 3

HBDC#T

LVTTL Schmitt Bi-directional output


HBDH#T

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL of Type 1, 2, or 3 specified in Table 4-27.




(2) LVDD Bi-Directional Buffers

Tables 4-42 to 4-45 are the listings of LVDD bi-directional buffers

Table 4-42 LVDD Bi-Directional Buffers (LVDD = 3.3V)




LBC#T

Bi-directional output for high speed Type 3 LBC3AT

LVTTL

Bi-directional output for low noise Type 3 LBC3BT PCI Bi-directional output for PCI PCI-3V LBPBT

Bi-directional for low noise output


LBH#T

Bi-directional output for high speed Type 3 LBH3AT

LVTTL Schmitt

Bi-directional output for low noise Type 3 LBH3BT



LBC$HT

Bi-directional output for high speed (Bus hold circuit) Type 3 LBC3AHT

LVTTL

Bi-directional output for low noise (Bus hold circuit) Type 3 LBC3BHT



LBH$HT

Bi-directional output for high speed (Bus hold circuit) Type 3 LBH3AHT

LVTTL Schmitt

Bi-directional output for low noise (Bus hold circuit) Type 3 LBH3BHT

NOTE: *1: The # symbol represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL/IOH of Type 1, 2, or 3 specified in Table 4-32.

*2: In addition to the cells shown in Table 4-42, cells with pull-up or pull-down resistor and those without test pins are available. If those without test pins are desired, contact your Epson sales representative.



Table 4-43 LVDD Bi-Directional Buffers (LVDD = 2.0V)




LBC#T

Bi-directional output for high speed Type 3 LBC3AT

CMOS

Bi-directional output for low noise Type 3 LBC3BT



LBH#T

Bi-directional output for high speed Type 3 LBH3AT

CMOS Schmitt

Bi-directional output for low noise Type 3 LBH3BT



LBC$HT

Bi-directional output for high speed (Bus hold circuit) Type 3 LBC3AHT

CMOS

Bi-directional output for low noise (Bus hold circuit) Type 3 LBC3BHT



LBH$HT

Bi-directional output for high speed (Bus hold circuit) Type 3 LBH3AHT

CMOS Schmitt

Bi-directional output for low noise (Bus hold circuit) Type 3 LBH3BHT


*2: In addition to the cells shown in Table 4-43, cells with pull-up or pull-down resistor and those without test pins are available. If those without test pins are desired, contact your Epson sales representative.



Table 4-44 LVDD N-Channel Open Drain Bi-Directional Buffers (LVDD = 3.3V)



LBDC#T LVTTL

Bi-directional output for high speed Type 1 Type 2 LBDC$CT


LBDH#T LVTTL Schmitt

Bi-directional output for high speed Type 1 Type 2 LBDH$CT

NOTE: *1: The # symbol or $ mark in the cell name represents a “Type” indicator (1, 2, or 3), which indicates the cell’s output drive capability. Each indicator corresponds to the IOL of Type 1, 2, or 3 specified in Table 4-32.


Table 4-45 LVDD Fail-Safe Bi-Directional Buffers (LVDD = 3.3V)

Input Level Function IOL Cell Name*1

Bi-directional output Type 1 Type 2 LBB#

LVTTL *2


LBB1C LBB2C LBB3A

Bi-directional output Type 1 Type 2 LBG#

LVTTL Schmitt*3


LBG1C LBG2C LBG3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to IOL of Type 1 or 2 specified in Table 4-32.


*3: In addition to the cells shown in Table 4-45, those with pull-down resistor are available.



4.3.4 Fail-Safe Cell

4.3.4.1 Outline

For the outline of fail-safe cells for dual power supply designs, see Chapter 4, Section 4.2.4.1, “Outline.” (The specifications of LVDD fail-safe cells are applicable to the dual power supply fail-safe cells.)

4.3.4.2 Features

For the features of fail-safe cells for dual power supply designs, see Chapter 4, Section 4.2.4.2, “Features.”


For the notes on use for fail-safe cells for dual power supply designs, see Chapter 4, Section 4.2.4.3, “Notes on Use.”


Table 4-46 Fail-Safe Input Buffers

Cell Name*1 Input Level Pull-up Resistor

LIBBP# CMOS Available


Table 4-47 Fail-Safe Output Buffers

Function IOH/IOL Cell Name*1

3-state output Type 1 Type 2 LTBF#


LTBF1C LTBF2C LTBF3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to the IOH/IOL of Type 1 or 2 specified in Table 4-32.



Table 4-48 Fail-Safe Bi-directional Buffers


Bi-directional output Type 1 Type 2 LBB#

CMOS Bi-directional output for high speed


LBB1C LBB2C LBB3A

Bi-directional output Type 1 Type 2 LBG#

CMOS Schmitt


LBG1C LBG2C LBG3A

NOTE: *1: The # symbol represents a “Type” indicator (1 or 2), which indicates the cell’s output drive capability. Each indicator corresponds to IOH/IOL of Type 1 or 2 specified in Table 4-32.


4.3.5 Gated Cells

4.3.5.1 Outline

For the outline of gated cells for dual power supply designs, see Chapter 4, Section 4.2.5.1, “Outline.” (The specifications of HVDD voltage cells are applicable to the dual power supply gated cells.)

4.3.5.2 Features

For the features of gated cells for dual power supply designs, see Chapter 4, Section 4.2.5.2, “Features.”


For the notes on use for gated cells for dual power supply designs, see Chapter 4, Section 4.2.4.3, “Notes on Use.”


Table 4-49 Gated Input Buffers

Cell Name*1 Input Level Pull-up/Pull-down Resistor

HIBA HIBAP# HIBAD#

AND Type TTL (HVDD=5.0V/LVDD=3.3V)


Pull-down resistor

HIBO HIBOP# HIBOD#

OR Type TTL (HVDD=5.0V/LVDD=3.3V)


Pull-down resistor




Table 4-50 Gated Bi-Directional Buffers




HBA#T


HBA3AT HBA4AT

AND Type


HBA3BT HBA4BT



HBO#T


HBO3AT HBO4AT

TTL (HVDD=5.0V/ LVDD=3.3V)

OR Type


HBO3BT HBO4BT


*2: In addition to the cells shown in Table 4-50, cells with pull-up or pull-down resistors and those without test pins are available. If those without test pins are desired, contact your Epson sales representative.



4.4 Notes on the Use of Dual Power Supplies By providing the capability of dual power supply operation, the S1L50000 Series enables each I/O buffer to interface 5.0V, 3.3V, or 2.0V signals. The internal cell area operates by either 3.3V or 2.0V power supply.

4.4.1 To Implement Dual Power Supply Designs

The S1L50000 Series can interface different voltage signals from the core cell area operating voltage.

There are two ways of interfacing with different voltage signals.

When using single power supply:

In a single power supply design, use of N-channel open drain buffers or fail-safe cells allows the designer to input higher voltage signals than power supply voltage. However, to output higher voltage signals than the power supply voltage is not possible. To do this, use open-drain type buffers combining them with pull-up resistors.

When using dual power supplies:

The use of input buffers dedicated to dual power supplies allows the designer to input higher voltage signals than the core cell operating voltage. To output higher voltage signals than the core area is also possible by the use of output buffers for dual power supply operation.

4.4.2 Power Supply for Dual Power Supply Designs

To provide two different voltage power supplies, use two power supply cells: HVDD and LVDD.

Use the HVDD power supply for HVDD voltage I/O buffers, and LVDD power supply for LVDD voltage output buffers and core cells. The power supply voltages must always meet the following formula:

HVDD ≥ LVDD

The functions are not guaranteed when HVDD < LVDD. The following operating conditions are recommended:

HVDD = 5.0V, LVDD = 3.3V HVDD = 3.3V, LVDD = 2.0V

4.4.3 Power On-Off Sequence

In case of the dual power supply chip, take the following sequence to power on or off.

To power on: LVDD (Core area) -> HVDD (I/O area) -> Turn on input signals

To power off: Turn off input signals -> HVDD (IO area) ->LVDD (Core area)

NOTE: 1: Do not apply the HVDD voltage continuously (longer than 1 second) when the LVDD power supply is turned off. It may lower the chip quality and cause malfunctions to the chip.

2: The state of core circuit is not guaranteed when HVDD power supply is returned from the off to on state, due to the power supply noise effect. In this case, ensure that the circuit is initialized after powered on.

Chapter 5 RAM


Chapter 5 RAM The S1L50000 series supports 1-port and 2-port RAMs.

5.1 Features (1) 1-port RAM

• Asynchronous

• Fully static operation

• 1 read/write address port, 1 input data port, 1 output data port

• 8- to 256-word deep, configurable in 4-word increments 1- to 32-bit wide, configurable in 1-bit increments

• Maximum size: 8K bits/module

(2) 2-port RAM

• Asynchronous

• Fully static operation

• 1 read address port, 1 write address port, 1 input data port, 1 output data port

• 8- to 256-word deep, configurable in 4-word increments 1- to 32-bit wide, configurable in 1-bit increments

• Maximum size: 8K bits/module

5.2 Word-bit Configurations and Simulation Models Since the RAM delay parameters vary depending on the word-bit configuration, simulation models are prepared for all possible word-bit configurations. Tables 5-1 and 5-2 are the listings of available simulation models for 1-port and 2-port RAMs.

If the RAM out of the word-bit configuration range shown in the following tables is required, combine multiple RAMs.

Table 5-1 1-port RAM simulation models with different word-bit configurations

Word depth Bit count

8 to 32 36 to 64 68 to 96 100 to 128 132 to 160 164 to 192 196 to 224 228 to 256

1 to 16 RAM1P1 RAM1P3 RAM1P5 RAM1P7 RAM1P9 RAM1P11 RAM1P13 RAM1P15


Table 5-2 2-port RAM simulation models with different word-bit configurations

Word depth Bit count

8 to 32 36 to 64 68 to 96 100 to 128 132 to 160 164 to 192 196 to 224 228 to 256



Chapter 5 RAM


5.3 RAM Size Estimation Use the following formulas for estimating the BC count for X and Y directions:

(1) 1-port RAM

X direction size: RX = Word + Bit/2 + 13

Y direction size: RY = 2xBit + 10

BC count: RAMBCS = RX x RY

Table 5-3 Where Word is the word depth and Bit is the bit count.

Bit count Word depth

4 8 16 32

32 846 (47 x 18) 1,274 (49 x 26) 2,226 (53 x 42) 4,514 (61 x 74)

64 1,422 (79 x 18) 2,106 (81 x 26) 3,570 (85 x 42) 6,882 (93 x 74)

128 2,574 (143 x 18) 3,770 (145 x 26) 6,258 (149 x 42) 11,618 (157 x 74)

256 4,878 (271 x 18) 7,098 (273 x 26) 11,634 (277 x 42) 21,090 (285 x 74)

(2) 2-port RAM

X direction size: RX = Word + Bit/2 + 13

Y direction size: RY = 2xBit + 14

BC count: RAMBCS = RX x RY

Where Word is the word depth and Bit is the bit count.

Table 5-4 2-port RAM configuration examples and BC counts

Bit count Word depth

4 8 16 32

32 1,034 (47 x 22) 1,470 (49 x 30) 2,438 (53 x 46) 4,758 (61 x 78)

64 1,738 (79 x 22) 2,430 (81 x 30) 3,910 (85 x 46) 7,254 (93 x 78)

128 3,146 (143 x 22) 4,350 (145 x 30) 6,854 (149 x 46) 12,246 (157 x 78)

256 5,962 (271 x 22) 8,190 (273 x 30) 12,742 (277 x 46) 22,230 (285 x 78)

Chapter 5 RAM


5.4 Embeddable RAM Size The X -Y dimensions of the place where a RAM is going to be embedded must exceed the RAM size, in terms of the number of basic cells used.

When multiple RAMs are used, they should be placed next to each other. In the formula mentioned earlier, wiring area around the RAM is included, and thus to see whether the RAM block is embeddable not, simply add the RX and RY sizes. For each master’s basic cell count in the X and Y directions, see Table 1-1.

The following is an example to see if S1L50282 and S1L50752 can integrate 4 cells of 1-port RAM 256-word deep and 8-bit wide.

As shown in Figure 5-1, the RAM layout size is estimated as follows:

X direction: 273 BCs

Y direction: 104 BCs

Therefore:

S1L50282 with BC counts in (X, Y) directions = (319, 90), and thus the RAM block is not embeddable

S1L50752 with BC counts in (X, Y) directions = (519, 146), and thus the RAM block is embeddable

As for the usable random gate count extracting RAM block gates, see Section 2.5, “Estimation of Usable BC Count for the Circuit with RAM.”

256w x 8b RAM 26

273

RAM (1)

RAM (2)

RAM (3)

RAM (4)

273

26

26

26

26

104

×4 ⇒

Figure 5-1 RAM layout example

Chapter 5 RAM


5.5 Function Examples (1) 1-port RAM

Table 5-5 1-port RAM signal descriptions

Signal name I/O Function Remard

CS IN Chip select signal, H: RAM active FI = 1LU

RW IN Read/Write signal, H: Read, L: Write FI = 1LU

A0, A1, ..., A (m-1) IN Read/Write address port, A0 : LSB FI = 1LU

D0, D1, ..., D (n-1) IN Data input port, D0: LSB FI = 1LU

Y0, Y1, ..., Y (n-1) OUT Data output port, Y0: LSB FO = 55LU

K: equivalnet to IN2

Table 5-6 1-port RAM truth table

CS RW A0, A1, ..., A (m-1) Y0, Y,1 ..., Y (n-1) Mode

0 X X Unknown Standby

1 0 Stable Unknown Write

1 1 Stable Read data Read X: High or Low

• Data Read

Set address with CS and RW held High to read data.

• Data Write

There are two ways to write data:

(1) Set address with CS held High, and input Low-level pulse to RW.

(2) Set address with RW held Low, and input High-level pulse to CS.

In both cases, the RAM latches the data at the falling edge of the pulse.

• Standby state

When CS is Low, the 1-port RAM goes standby and only holds data. The current that flows through the RAM is only leakage current and the consumption current is almost 0.

Chapter 5 RAM


(2) 2-port RAM

Table 5-7 2-port RAM signal descriptions

Signal name I/O Function Remark

CS IN Chip select signal, H: RAM active FI = 1LU

RD IN Read signal, H: Read enable FI = 1LU

WR IN Write signal, H: Write enable FI = 1LU

RA0, ... RA（m-1） IN Read address port, RA0: LSB FI = 1LU

WA0, ... WA（m-1） IN Write address port, WA0: LSB FI = 1LU

D0, D1, ... D（n-1） IN Data input port, D0: LSB FI = 1LU

Y0, Y1, ... Y（n-1） OUT Data output port, Y0: LSB FO = 55LU

K: equivalnet to IN2

Table 5-8 2-port RAM truth table

CS RD WR RA0, ..., RA (n-1) WA0, ..., WA (m-1) Y0, ..., Y (n-1) Mode

0 x x x x Unknown Standby

1 0 0 x x Unknown Standby

1 0 1 x Stable Unknown Write

1 1 0 Stable x Read data Read

1 1 1 Stable Stable Read data Read&WriteX: High or Low

• Data read

Set address with CS and RD held High to read data.

• Data write

There are two ways to write data:

(1) Set address with CS held High, and input High-level pulse to WR

(2) Set address with WR held High, and input High-level pulse to CS

• Data read and write

Simultaneous read and write is possible using read and write addresses, though simultaneous read and write access to the same address is prohibited. As described in Section 5.6, Delay Parameters, the read cycle access time is applicable to the data for which write operation is finished.

Chapter 5 RAM


• Standby state

In the following conditions, 2-port RAM goes standby and only holds data. The current that flows through the RAM is only leakage current and the consumption current is almost 0.

(1) CS is Low

(2) CS is High, RD and WR are Low.

Chapter 5 RAM


5.6 Delay Parameters (1) 3.3V specification (VDD = 3.0 to 3.6V, Ta = -40 to +85°C)

Table 5-9 1-port/2-port RAM read cycle (1/4)

RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3

RAM1P4/ RAM2P4 Parameter Symbol

Min. Max. Min. Max. Min. Max. Min. Max.Unit

Read cycle tRC 4.35 — 4.77 — 5.19 — 5.61 —

Address access time tACC — 4.35 — 4.77 — 5.19 — 5.61

CS access time tACS — 4.35 — 4.77 — 5.19 — 5.61

RW access time tARW — 4.35 — 4.77 — 5.19 — 5.61

CS active time tRCS 4.35 — 4.77 — 5.19 — 5.61 —

Output hold time after address change tOH 0.08 — 0.14 — 0.08 — 0.14 —

Output hold time after CS is disabled tOHCS 0.08 — 0.14 — 0.08 — 0.14 —

Output hold time after RW is disabled tOHRW 0.08 — 0.14 — 0.08 — 0.14 —

ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Read cycle tRC 6.03 — 6.45 — 6.86 — 7.29 —








ns

Chapter 5 RAM


Table 5-9 1-Port/2-Port RAM Read Cycle (3/4)

RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11


Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read cycle tRC 7.70 — 8.12 — 8.54 — 8.96 —



RW access time tARW – 7.70 — 8.12 — 8.54 — 8.96





ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Read cycle tRC 9.38 — 9.80 — 10.22 — 10.64 —








ns

Chapter 5 RAM


Table 5-10 1-port/2-port RAM write cycle (1/4)

RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Write cycle tWC 3.82 — 5.07 — 3.93 — 5.17 —

Write pulse width tWP 1.87 — 3.11 — 1.91 — 3.16 —

CS active time tWCS 1.87 — 3.11 — 1.91 — 3.16 —

Address setup time tAS 0.63 — 0.63 — 0.68 — 0.68 —

Address hold time TAH 1.33 — 1.33 — 1.33 — 1.33 —

Data setup time tDS 0.00 — 0.00 — 0.00 — 0.00 —

Data hold time tDH 2.33 — 3.33 — 2.37 — 3.37 —

ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Write cycle tWC 4.04 — 5.28 — 4.15 — 5.40 —







ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Write cycle tWC 4.27 — 5.51 — 4.39 — 5.64 —







ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Write cycle tWC 4.52 — 5.76 — 4.65 — 5.89 —







ns

Chapter 5 RAM


(2) 3.3V specification (VDD = 3.0 to 3.6V, Ta = 0 to +70°C)


RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Read cycle tRC 4.22 — 4.63 — 5.04 — 5.45 —








ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Read cycle tRC 5.85 — 6.26 — 6.66 — 7.08 —








ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Read cycle tRC 7.47 — 7.88 — 8.29 — 8.70 —



RW access time tARW – 7.47 — 7.88 — 8.29 — 8.70





ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Read cycle tRC 9.10 — 9.51 — 9.92 — 10.32 —








ns

Chapter 5 RAM



RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Write cycle tWC 3.71 — 4.92 — 3.82 — 5.02 —



Addresss setup time tAS 0.62 — 0.62 — 0.66 — 0.66 —




ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Write cycle tWC 3.92 — 5.13 — 4.03 — 5.24 —







ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Write cycle tWC 4.15 — 5.35 — 4.26 — 5.47 —







ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Write cycle tWC 4.39 — 5.59 — 4.51 — 5.72 —







ns

Chapter 5 RAM


(3) 2.0V specification (VDD = 1.8 to 2.2V, Ta = -40 to +85°C)


RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Read cycle tRC 18.68 — 20.05 — 22.59 — 23.96 —








ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Read cycle tRC 26.50 — 27.88 — 30.42 — 31.79 —








ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Read cycle tRC 34.33 — 35.70 — 38.24 — 39.62 —








ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Read cycle tRC 42.16 — 43.53 — 46.07 — 47.44 —








ns

Chapter 5 RAM



RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Write cycle tWC 13.16 — 17.52 — 13.39 — 17.63 —







ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Write cycle tWC 13.50 — 17.86 — 13.74 — 18.10 —







ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Write cycle tWC 14.12 — 18.48 — 14.37 — 18.73 —







ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Write cycle tWC 14.62 — 18.98 — 14.88 — 19.24 —







ns

Chapter 5 RAM


(2) 2.0V specification (VDD = 1.8 to 2.2V, Ta = 0 to +70°C)


RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Read cycle tRC 18.12 — 19.45 — 21.92 — 23.25 —








ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Read cycle tRC 25.71 — 27.05 — 29.51 — 30.84 —








ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Read cycle tRC 33.30 — 34.63 — 37.10 — 38.44 —








ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Read cycle tRC 40.90 — 42.23 — 44.69 — 46.02 —








ns

Chapter 5 RAM



RAM1P1/ RAM2P1

RAM1P2/ RAM2P2

RAM1P3/ RAM2P3



Write cycle tWC 12.77 — 17.00 — 12.99 — 17.11 —







ns


RAM1P5/ RAM2P5

RAM1P6/ RAM2P6

RAM1P7/ RAM2P7



Write cycle tWC 13.10 — 17.33 — 13.33 — 17.56 —







ns

Chapter 5 RAM



RAM1P9/ RAM2P9

RAM1P10/ RAM2P10

RAM1P11/ RAM2P11



Write cycle tWC 13.70 — 17.93 — 13.94 — 18.17 —







ns


RAM1P13/ RAM2P13

RAM1P14/ RAM2P14

RAM1P15/ RAM2P15



Write cycle tWC 14.19 — 18.41 — 14.44 — 18.67 —







ns

Chapter 5 RAM


5.7 Timing Chart (1) 1-port RAM

Figure 5-2 Read cycle

Figure 5-3 Write cycle (RW control)

Figure 5-4 Write cycle (CS control)

ADDRESS

CS

RW

Data in valid

tAStWCS

tWC

tDH

tAH

tDS

ADDRESS

CS

RW

Data in valid

tAStWP

tWC

tDH

tAH

tDS

A1 A2 A3 ADDRESS

CS

RW

Data out A1 X A1 X A2 X A3

tRCS

tACS tOHCS

tACCtRC

tOH

tACC

tOHRW

X A3

tARW

Chapter 5 RAM


(2) 2-port RAM

Figure 5-5 Read cycle

Figure 5-6 Write cycle (WR control)

Figure 5-7 Write cycle (CS control)

ADDRESS

CS

WR

Data in valid

tAS tWCS

tWC

tDH

tAH

tDS

ADDRESS

CS

WR

Data in valid

tAS tWP

tWC

tDH

tAH

tDS

A1 A2 A3ADDRESS

CS

RD

Data out A1 X A1 X A2 X A3

tRCS

tACS tOHCS

tACCtRC

tOH

tACC

tOHRW

X A3

tARW

Chapter 5 RAM


5.8 Access to Invalid Addresses If the RAM has 48- or 88-word deep configuration, access to invalid addresses may occur. If an invalid address is accessed to read data in the actual IC, all word lines go to the off state and all bit lines go floating. This leads to the following conditions:

1. Read operation with all bit lines floating outputs unknown to all the RAM output bits

2. Read operation with all bit lines floating generates a current flow path in the circuit. The value of this current varies depending on the RAM size or configuration; but it deviates the IC’s dynamic and static current values from the specified values.

Considering these unfavorable conditions, the access to invalid addresses is prohibited. In the logic simulation, invalid addresses are checked at the rising time of the clock signal in the Read/Write operation, and if an invalid address is accessed, a timing error is output.

Chapter 6 Design for Testability


Chapter 6 Design for Testability Before shipment, ICs are tested using LSI testers. To facilitate this test, engineers need to design from the onset considering the testability provisions discussed in this chapter.

Boundary scan circuits implemented together with those testability provisions are not covered in this chapter. For boundary scan designs, which require test patterns that allow DC testing, refer to Section 6.7, “Boundary Scan Design.” If test circuit is not possible to add, contact your Epson sales representative.

6.1 Circuit Initialization The initial states of flip-flops (FFs) used in digital circuits are all unknown (X) at the time of testing with LSI testers and running simulation. Because of this, circuit initialization is sometimes not possible due to the circuit configuration, or requires a large number of test patterns. Therefore, design considerations to easily accomplish circuit initialization are required, such as using flip-flops with reset feature.

6.2 Shortening the Test Patterns As circuit complexity increases, the size of test patterns increases. Care must be taken because the LSI testers have the following constraints on the test pattern size:

The number of events per test pattern: Up to 256K events The number of test patterns: Up to 30 patterns The number of total events: Up to 1M events

The maximum numbers shown above are the limits on the test patterns for the DC testing, which include the test patterns for the Z-test, test circuits, and for ROMs and mega cells developed by Epson. For the number of test patterns and events required for ROMs and mega cells, contact your Epson sales representative. As for the test patterns for ROMs, those generated by the customer are subject to the number limit mentioned above, though the test patterns generated by Epson to verify all the patterns for RAM are not counted.

Having a test pin somewhere in the long counter-chain to input a clock signal, and adding a test pin that allows the designer to observe the internal signals are considerations that can be taken to improve the design testability and reduce the number of test patterns.

6.3 Special Test Circuit Provisions for AC and DC Tests For the S1L50000 Series, a pre-shipment test circuit that can efficiently validate AC and DC performance characteristics needs to be added to the customer’s circuit. If it is not possible to add the test circuit, contact your Epson sales representative.



6.3.1 Test Circuit Configuration

Figure 6-1 shows the circuit configuration of the test mode control circuit, “TCIR2.” Figure 6-2 shows the test circuit using the test mode control circuit, “TCIR2,” and a sample of test circuit for RAM of 2 words x 2 bits. (No such configuration actually exists.) Develop a test circuit referring to these circuits and the following descriptions of 1 to 4. If the design contains RAM and functional cells, refer to Section 6.4, “Test Circuit for Memory Blocks,” and Section 6.5, “Test Circuit for Function Cells.” 1 Test pin addition and selection

Add or select pins for the following 4 types of test pins to configure the test circuit:

• Test mode switch input pin: 1

• Test mode select input pin: 4

• Monitor output pin for AC test: 1

• Monitor output pin for DC test (input voltage level): 1

Table 6-1 Constraints on test pins

Test pin Pin count

Pin name (example) Constraints

Test mode switch input pin 1 TSTEN Dedicated input pin. ITST1 is used for the input buffer

H: Test mode, L: Normal mode

Test mode select input pin 1 INP0~INP3 Dual-purpose input pin that can be also used for a user function. Not possible to use as a bi-directional pin. Avoid using as an input pin connected to a critical path.

Monitor output pin for AC test

1 OUT3 Dual-purpose output pin that can be also used for a user function. Not possible to use as Nch open drain cell. Not possible to use the Type S and Type M output buffers.

Monitor output pin for DC test

1 OUT4 Dual-purpose output pin that can be also used for a user function. Not possible to use as a bi-directional pin, 3-state pin, and Nch open drain pin.

Output pin, bi-directional pin - - Output buffer with test mode function. (Bi-directional buffer is used.)

• About DC test:

The DC parameters of all the input and output pins are measured to check if they meet the specifications. If a test circuit is not included, test patterns for validating the DC parameters are required and this demands considerable manpower. Embedding a test circuit facilitates the test pattern generation and the DC parameter measurement.



• About AC test:

Pin-to-pin delay (from an input pin to an output pin) is measured. When the system-speed testing is not possible by the LSI tester, the IC’s operating speed is guaranteed by measuring a certain path delay. When using the test circuit “TCIR2” recommended by Epson, differences in the deviations from the AC specifications depending on production lots are evaluated by measuring the dedicated AC path using the monitor output pin. The recommended test circuit “TCIR2” can measure delays regardless of the test circuit location within the chip and the external conditions, because it checks the measured delay difference between the target element and the path bypassing the element.

2. The addition and connection of the test mode control circuit

a: Place the test mode control circuit, “TCIR2.”

b: Connect the output pins (X) and (LG) of the test mode switch input buffer “ITST1” with the input pins (TST) and (ILG) of “TCIR2” respectively.

c: Connect the output pin of the input buffer for the test mode select input pin with the input pin of the test mode control circuit, “TICR2.”

• Connect the X pin of the INP0 input buffer with the TM0 pin of the “TCIR2”




d: Connect the output pin of the test mode control circuit “TCIR2” with the input pins of the output and bi-directional buffers.

• Connect the TAC pin of the “TCIR2” with the TA pin of the AC test monitor output pin (OUT3)

• Connect the OLG pin of the “TCIR2” with the TA pin of the DC test monitor output pin (OUT4)

• Connect the TD pin of the “TCIR2” with the TA pins of all the I/O buffers except the AC and DC test monitor output pins (OUT3 and OUT4)

• Connect the TE pin of the “TCIR2” with the TE pins of the IO buffers for the 3-state pin (OUT2) and bi-directional pin (BID1).

• Connect the TS pin of the “TCIR2” with the TS pins of all the IO buffers.

• The MS pin of the “TCIR2” is usable to control each macro cell when RAM and function cells exist.

e: Ignore if the signals connected to the TA, TE, or TS pin of the I/O buffers exceed the fan-out limit.



3. Example of typical test mode setup

a: DC test

• Static current test mode *1 TSTEN --- “HIGH”

*1: If the embedded macro has its own static current test mode, it must be set up separately.

• Output voltage (VOH/VOL) test mode TSTEN --- “High” INP0 --- “Low” INP1 --- “High” and “Low” INP2 --- “Low” Pins to test *2 --- “High” and “Low”

*2: All the output and bi-directional pins other than the DC test monitor output pin.

• Input voltage (VIH/VIL) test mode TSTEN --- “High” Pins to test *3 --- “Low” Pins not to test --- “High” DC test monitor pin --- “High” and “Low”

*3: All the input and bi-directional pins other than TSTEN.

• Leakage current test mode TSTEN --- “High” INP0 --- “High” INP1 --- “Low” INP2 --- “High” Pins to test *4 --- “High” and “Low” 3-state and Nch open drain pins --- High impedance

*4: All the input, 3-state output and bi-directional pins other than INP0 to 2. b: Dedicated AC test

• Dedicated AC path test mode TSTEN --- “High” INP0 --- “Low” INP1 --- “Low” INP2*5 --- Transition to “HIGH” and “LOW” (Input signal to the target element) INP3*5 --- Selection between “HIGH” (target cell delay) and “LOW” (bypass delay) (Pin for selecting the target element)

*5： After selecting the element to test by INP3, change the INP2 in the subsequent event. In case of the patterns where INP2 and INP3 simultaneously change, correct delay may not be obtained. Refer to the example of test pattern generation for test options shown in Figure 6-3.



c: Macro test

• Macro test mode TSTEN --- “High” INP0 --- “High” INP1 --- “Low” INP2 --- “Low” Test mode macro control pin *6 --- Depending on the macro function Test mode macro monitor pin *6 --- Depending on the macro operation

*6: Dual-purpose pin assigned to the macro in test mode

Table 6-2 Truth table for the test circuit

INPUT OUTPUT

TST ILG TM3 TM2 TM1 TM0 TS TD TE TAC OLG MS

0 x x x x x 0 0 0 0 0 0

1 1 x x x x 1 x x x 1 x

1 0 x x x x 1 x x x 0 ×

1 x x 1 1 1 1 1 1 1 x 0

1 x x 1 1 0 1 1 1 1 x 0

1 x x 1 0 1 1 1 1 1 x 0

1 x x 0 1 1 1 1 1 1 x 0

1 x x 0 0 1 1 1 0 1 x 1

1 x x 0 1 0 1 1 0 1 x 0

1 x 0 1 0 0 1 0 0 1 x 0

1 x 0 0 0 0 1 0 0 0 x 0

1 x 1 1 0 0 1 0 0 1 x 0

1 x 1 0 0 0 1 0 0 0 x 0

4. Test pattern generation

Test circuits and test patterns need to be designed so that the DC and AC tests may be efficiently performed. Figure 6-3 shows an example of test patterns for the test circuit shown in Figure 6-2. Generate test patterns, paying attention to the following points:

a. Create test patterns like the one shown as an example in addition to the patterns to verify the circuit.

b. Describe all the pins used for the circuit in the test patterns

c. Test patterns to check cell delay and those to check bypass delay are required for the AC testing. Refer to Figure 6-3, and create test patterns to input two pulses in each mode.

d. Describe the test mode switch pin (TSTEN) in the test patterns for the function verification as well. In this case, the input level of the test mode switch pin (TSTEN) must be in the “0” state to get out of the test mode.

e. When the input level of the test mode switch pin (TSTEN) is “1,” all the pull-up and pull-down resistors are in the inactive state.



5. Circuit configuration with the test mode control circuit “TCIR2”

Figure 6-1 shows the test circuit configuration using the test mode control circuit, “TCIR2” recommended by Epson. The test mode control circuit “TCIR2” sets the entire circuit to the test mode and allows the designer to efficiently perform the DC and AC tests of LSIs.

I_33

ACP1B

I_22

BF8

I_23

BF8

I_24

BF8

I_25

BF8

I_26

BF8

I_27

BF8

I_15

OR2

I_16

AN222

I_21

NO2

I_17

NO2

I_1

NO2

I_2

IN2

I_18

NO3

I_6

NO2

I_19

NO2

I_20

NO2

I_28

NA2

I_29

NA2

I_30

NA2

I_7

NA2

I_31

IN1

I_32

IN1

I_9

IN1

I_8

IN1

I_10

BF1

I_11

BF1

I_12

BF1TM0

TM1

TM2 MS

TD

TE

TS

TAC

TM3

TST

OLGILG

Figure 6-1 TCIR2 Internal Circuit



Figure 6-2 Example of Test Circuit



# Test pattern example in the APF format $RATE 200000

$RESOLUTION 0.001ns

$STROBE 185000

$NODE

TSTEN ID 0

INP0 I 0

INP1 I 0

INP2 I 20000 # Measure delay difference

INP3 I 0

IA0 I 0

ID0 I 0

ID1 I 0

ICS1 I 0

ICS2 I 0

IRW1 I 0

IRW2 I 0

BID1 B 0

OUT0 O

OUT1 O

OUT2 O

OUT3 O

OUT4 O

$ENDNODE

$PATTERN

# TIIIIIIIIIIIBOOOOO

# SNNNNADDCCRRIUUUUU

# TPPPP001SSWWDTTTTT

# E0123 1212101234

# N

#

# IIIIIIIIIIIIBOOOOO

# D

#

0 00000.......XXXXXX

1 10000.......LLLLLX：Measurement 1 of the dedicated AC path (bypass delay)

2 10010.......LLLLHX ↑

3 10000.......LLLLLX ↑

4 10001.......LLLLLX：Measurement 2 of the dedicated AC path (cell delay)

5 10011.......LLLLHX ↑

6 10001.......LLLLLX ↑

7 11010.......0ZHHHX：Off-state leakage current measurement

8 11010.......1ZHHHX ↑

9 10000.......LLLLLX：Output characteristics measurement

10 10100.......HHHHHX ↑

$ENDPATTERN

#

# EOF

Note: The underscore ( _ ) represents “1” or “2.”

Figure 6-3 Example of Test Patterns with Test Options



6.4 Test Circuit for Memory Blocks When RAM is used, all the bits must be checked before shipment. For this pre-shipment test, a test circuit that allows the external pins to directly access the RAM I/O pins needs to be embedded.

The test I/O pins can be also used as I/O pins for normal operation, and thus, adding the test circuit should not affect the pin count.

During the RAM test, all the bi-directional pins are in the output state and cannot be used as input pins. If there are not enough input pins, add a control circuit to the TE pins of I/O buffers for the target bi-directional pins and use them as input pins.

When multiple RAMs are embedded, it is recommended to assign the I/O pins of each RAM to a separate set of external pins. If there are not enough external pins, however, they can be shared by I/O pins of different RAMs using a test circuit.

The sample test circuit shown in Figure 6-2, which allows the normal operation in the non-test mode, directly writes data to RAM from the primary pins ICS1~2, IRW1~2, ID0~1, and IA0 in the test mode. In the test mode, the RAM data are output to the primary pins AY0 and AY1.

The RAM I/O pins can be assigned to bi-directional pins and 3-state output pins, but the state of bi-directional pins during the RAM test must be fixed to either input or output. Also care must be taken not to assign an input buffer with pull-up resistor to Chip Select (CS). Otherwise the static current cannot be measured.

6.4.1 Test Patterns for RAM Blocks

When a RAM block and a test circuit are embedded, test patterns for the normal operation mode and those for the test mode need to be separately created. The test patterns for the normal operation mode check if the RAM is properly connected with the user circuit; and those for the test mode check if the test circuit is properly embedded. The customer is requested to provide Epson with a template file to create test patterns for the RAM blocks. Figures 6-4 and 6-5 show the examples of test pattern generation.



Figure 6-4 Test patterns for 1-port RAM



Figure 6-5 Test patterns for 2-port RAM



6.5 Test Circuit for Function Cells Designs including function cells, like those including RAM Cells, require a large number of test patterns and a lot of manpower to verify the functions of the entire circuit. Therefore, it is necessary to design a test circuit that allows the designer to selectively verify the behaviors of each function cell and the user circuit.

The following describes the points that the designer should pay attention to when developing a test circuit. For more information, refer to the design guides for function cells.

6.5.1 Test Circuit Configuration

1. Add a test circuit and connect the pins of function cells to the external pins so that the designer can selectively check each block, isolating it from the user’s circuit.

2. Even when the inputs of the function cells are fixed to VSS or VDD, add a test circuit so that test signals can be input.

3. Even when the output pins of the function cells are not used, add a test circuit so that all the outputs of the function cells may be observable by the external pins.

4. Do not share one test pin with multiple output or input pins of the function cell.

5. Do not use a sequential circuit for the test circuit to test function cells.

6. Do not invert the input signal from the test input to the function cell. Conversely, do not invert the output signal from the function cell to the test output pin.

7. When the chip pins are directly used as the input and output pins of the function cells, a test circuit is not required.

6.5.2 Test Patterns

Test patterns are roughly divided into the following three types:

1) Test patterns that test only the user’s circuit

2) Test patterns that test the entire circuit

3) Test patterns that test only function cells

The test patterns to be generated by the customer are 1) and 2) above. Test patterns 3) are not required; existing test patterns generated by Epson will be used. Please be noted that the test patterns for function cells (existing test patterns) are not released to customers.

6.5.3 Test Circuit Information

Please provide Epson with the following information on the test circuit. The information is required to run simulation and to test function cells before shipment.

1. The connections of the function cell pins to the chip pins in the test mode

2. Function cells to be tested and their test modes if the test circuit is designed to allow one test pin to test multiple function cells

3. Serially numbered function cell names in the schematic and their test pins, if multiple same function cells are used.

4. The procedures of switching to the test mode.

To use function cells, be sure to read the “Function cell design guide” as well.



6.6 Scan Design To reduce the number of defective products, pre-shipment tests using test patterns that stimulate logic circuits are required. However, this task demands considerable manpower for large-scale designs. Scan design is a solution to this problem, which generates test patterns with high-fault coverage by developing a design according to given rules and implementing Automatic Test Pattern Generation (ATPG).

This section describes the design rules for scan designs and the ATPG service. Since the design configuration will greatly affect the implementation of scan design, it is important to deign conforming to the scan design rules from the onset of the design. If any part of the design violates the design rules, what is aimed by ATPG may not be achieved and thus the service is not available in this case.

6.6.1 Scan Circuit

Build up scan paths replacing all the registers (D-FF, JK-FF) in the designs with scan type registers (full-scan design). Running ATPG on full-scan designs generates test patterns with high fault coverage.

Note: The test patterns ATPG generates are not for verifying the specifications. Transparent latches are not replaced with scan registers.

Scan-outScan-in

Com

binational circuit

Com

binational circuit

: Scan-type resistor

Figure 6-6 Example of Scan Circuit

6.6.2 Scan Design Flow

The following figure shows the task flow for scan designs and ATPG. If the customer desires to add scan registers and run ATPG, contact your Epson sales engineer.



Circuit Design(Synchronous design)

Design Rule Check(snrc)

Scan Rule Check(Check sheet)

ＮＧ

ＮＧ

Yes

Yes

Full-scan circuit generation

ＡＴＰＧ

Netlist with scan registers

Test pattern

Verification

Fault coverage

P&R

　・Gate-level netlists　・Scan-design check sheet (attached at the end of this chapter.)　・Clock Tree Synthesis check sheet (See Chapter 3, "Clock Tree Synthesis.")If the design to be provided to Epsonalready incorporates scan registers,make it known to Epson.

Design a synchronous logic circuit. If thecircuit is designed without regard to thescan design rules, the scan service willnot be made available.

Run the design rule checker, "snrc"included in the Epson Design Kit, EPITS,and check if the design meets the basicdesign rules for ASIC.

Check if the design meets the followingdesign rules for incorporating scanregisters:Please provide Epson with the followingdata:

Customer

SeikoEpson

Incorporate scan registers into thecircuit and run ATPG.

Verify the generated netlists and testpatterns. Verified test patterns are usedfor the pre-shipment test.

Figure 6-7 Design Flow of Circuit with Scan Registers



6.6.3 Design Rules

This section describes design rules that must be met by circuits with scan registers. To achieve 90% or higher fault coverage, the design must meet all the conditions described below. When transferring the design to Epson for further design tasks, also present the “Scan Design Check Sheet” attached at the end of this chapter.

a. Scan control external pins

To implement scan designs, all the external pins described below are required:

• ATPG enable input pin (ATPGEN) – dedicated pin

ATPGEN is an external input pin to activate the ATPG execution mode. Design blocks that need to be in a fixed state, blocks whose internal logics become unknown (including those becoming black boxes during a simulation run), function macros, and RAM cell outputs should be set to a fixed value by using this pin. Without this consideration, the fault coverage will significantly decrease. Use a dedicated pin for ATPGEN.

• Scan enable input pin (SCANEN) – dedicated pin

SCANEN is a dedicated external input pint to switch normal data paths (parallel operation) and scan paths (shift operation). This pin cannot be shared with normal and other mode functions. Prepare an input cell and an external pin for SCANEN. Epson takes care of the internal connection.

• Scan clock input pin – Same as the normal clock input pin or a dedicated pin

A clock input pin for test patterns generated by ATPG. Epson’s scan cells use scan registers with MUX and thus the system clock for normal operation drives them in most cases. However, if an internally generated clock exists, a clock pin dedicated to scan registers is required in some cases. For more information, see “b. Clock Design.”

• Scan data input pin (multi-purpose pin)

External input pins for setting data to scan registers that have replaced normal registers in the design. Multiple pins are required according to the number of scan registers. One input pin covers 300 to 500 scan registers. The number of scan data input pins must be the same as scan data output pins. The scan data input pins can be used as other external input pins used in normal mode. However, they cannot be shared with asynchronous set/reset, and analog signal input pins. Using this pin for multiple purposes increases the fan-out value of the connected net. Avoid connecting this pin to a critical path.

Scan data input pins are connected by Epson as a task in scan design. The customer is requested to specify external input pins for scan data input pins. If not specified, the responsible engineer at Epson will specify them.

• Scan data output pin (multi-purpose pin)

External output pins to output data observed at the scan registers that have replaced normal registers in the design. Multiple pins are required according to the number of scan registers. About 300 to 500 scan registers require one output pin. The number of scan data output pins must be the same as the scan data input pins.

The scan data output pins can be used as other external output pins in normal mode. (2-state type output pins are recommended.) However, they cannot be shared with analog signal



output pins. Using this pin for multiple purposes increases the cell count of the net. Avoid connecting this pin to a critical path.

Scan data output pins are connected by Epson as a task in scan design. The customer is requested to specify external output pins for scan data output pins. If not specified, the responsible engineer at Epson will assign them.

b. Clock Design

Clock design is very important for scan design. Complicated clock design not only lowers fault coverage but also generates unreliable test patterns. It inhibits the designer to achieve the original purpose of scan design and ATPG, and thus the most fundamental design guideline is to make sure that all circuits are designed with synchronous logic. The following design rules also need to be met.

Implementing CTS (Clock Tree Synthesis) is also essential for clock lines. For more information, see Chapter 3, “3.3. Clock Tree Synthesis.”

• Must be externally controllable

The scan clock signal must reach registers from the external input pin, keeping its initial clock waveform. Internally generated clocks are allowed to exist in normal operation, but not in the ATPG mode. Examples are shown in Figures 6-8 to 6-11.

• Ideal clock

Figure 6-8 shows an example of ideal clock design. As shown in this example, if a clock is designed to be supplied from an external pin to all the registers at an early stage of the design, clock line modification for scan design is not required, but only CTS process. Since clock line modification influences the timing of entire logic, it is important to consider the scan circuit from the onset of circuit design.

clock

Figure 6-8 Ideal Clock

• How to handle an internally-generated clock: Technique 1

When an internally-generated clock is used, add a circuit that bypasses the clock generation part and also the one that implements CTS in the ATPG execution mode as shown in Figure 6-9. However, by doing this, the MUX cell is added to the clock line and it sometimes work against timing adjustment with other clocks. Therefore, caution must be exercised when using this technique.



clock

?

?

?clock

ATPGEN

?

ATPG mode :ATPGEN=1

CTS Special Cell

CRBF

Figure 6-9 Technique 1 for an internally generated clock

• How to handle an internally-generated clock (clock gating): Technique 2

One possible solution to prevent the cell addition to the internally-generated clock line is to control the clock gating enable line. Figure 6-10 is one example. This is an effective way to build a design with relatively small clock skew without inserting MUX on clock lines.

clock clock

ATPGEN

CRBF

ATPG mode :ATPGEN=1

CTS Special Cell

Figure 6-10 Technique 2 (Clock gating) for an internally generated clock

• Designs with multiple clock groups

If the design has multiple clocks including those internally generated, applicable techniques to handle them may be limited depending on the relationship among the clock groups. There should be no problem if different clock blocks are not physically connected. However, adequate care must be taken if the specification forces those blocks to have false paths or multi-cycle paths. In false paths, though the different clock blocks are physically connected, no logic communications occur in normal operation, or timing is not considered at the time of logic synthesis. In multi cycle paths, the specification allows latch failures to occur several times as asynchronous communication.

clock

A

B

CClo

ckG

ener

ator

Figure 6-11 (a) Design with multiple internally-generated clocks



Figure 6-11 (b) shows an example of technique applicable when blocks, A, B and C are not physically connected. Since there are no physical connections, CTS can solve the skew problem of each clock for running ATPG.

clock

A

B

C

ATPGENATPG mode :ATPGEN=1

CTS Special Cell

CRBF

Clo

ckG

ener

ator

Figure 6-11 (b) Technique 1 for multiple internally-generated clocks (When blocks are not connected)

Note: This is an example based on the assumption that inserting one clock root buffer cell by CTS for the three clock blocks effectively build a scan chain.

However, when blocks are physically connected, some measures must be taken for ATPG. Figure 6-11 (c) is one example. ATPG generates test patterns at random, and this may cause operations through false paths that are impossible in terms of the specifications. In this case, the timing of data paths between A, B, and C is not possible to guarantee. To cope with this, bypass the internally-generated clocks separately and make each of their timing externally controllable. It is recommended to use dedicated pins for these bypass clock pins. If it is unavoidable to use multi-purpose pins, they need to be gated so that the clock signals input from them may propagate only to registers. (See Figure 6-11 (d).) When doing this, the net values are fixed and thus the fault coverage goes down.

clock

ATPGENATPG mode :ATPGEN=1

CTS Special Cell

CRBF

CRBF

CRBFScanClk1

ScanClk2

ScanClk3

Clo

ckG

ener

ator

A

B

C

Figure 6-11 (c) Technique 2 for multiple internally-generated clocks (When blocks are connected)



INPUT

ATPGEN

ScanClockTo Scan FFs

Figure 6-11 (d) Scan clock input from a common pin

• Minimize the clock count (recommended)

As shown in the above, a design with multiple clocks increases the work to be done by the customer, demanding design modification, addition, and timing re-verification. Also, it increases the test pattern size and lowers the fault coverage. For effective scan testing, the design should be built with the minimum number of clock groups.

• Avoid clocks using both rising and falling edges (recommended)

Using both rising and falling edges of any clock prevents efficient scan testing and ATPG. It even lowers fault coverage in certain cases. It is recommended to use only one edge of scan clock.

• Isolate the scan clock signal from data signals (recommended)

Isolate the scan clock signal from data signals. If the scan clock signal influences data lines, the scan clock and data signals are not separately controlled and thus faults cannot be detected.

c. Asynchronous set/reset signals for registers (essential)

Asynchronous set/reset signals for flip-flops and transparent latches are recommended to be externally controllable. If internally-generated signals are used for them, pay attention to the following points:

• Do not activate the signal while the scan enable is active

• Directly use the signal without passing through a combinational logic from the output of flip-flop to prevent minimum pulses. If internally-generated signals passing through combinational logic are used, use gray code or apply other possible solution to facilitate error correction.

Note: Ignoring these points may lower fault coverage and generate unreliable test patterns.

d. How to handle transparent latches (recommended)

Transparent latches are not replaced with scan cells. Avoid using transparent latches if possible because they lower the fault coverage. When using them, consider the following points:

• Take measures similar to those discussed in “b. Clock Design” for clock signals.

• Set to the same off-state level as other registers connected to the same clock line.

e.g. If FF is rising edge-triggered (ReturnToZero), the latch is transparent when “Low.” If FF is falling edge-triggered (ReturnToOne), the latch is transparent when “High.” However, if both edges of scan clock are used, or multiple scan clocks exist, the fault coverage may not improve depending on design configurations. In this case, take the following measures:

• If these two points cannot be met, set the latches to the transparent state in the ATPG execution mode. When doing this, care must be taken not to generate feedback loops.

Note: Ignoring these points lowers fault coverage and generates unreliable test patterns.



e. Cells and designs not allowed to use (essential)

In scan designs, the following cells are not allowed to use:

< Cells prohibited to use >

• RS latch cell

• FF with asynchronous set and reset functions

• Multi-bit FF cell

• Scan type FF

< Logic prohibited to use >

• Combinational feedback loop (including those passing through external bi-directional pins)

• Differentiation circuit (pulse generator)

• Self-reset logic

• ATPG mode by sequential control (Control ATPG by ATPG enable input pin.)

Note: Ignoring these points lowers fault coverage and generates unreliable test patterns.

f. Care that needs to be taken when using function macros and RAM cells (recommended)

A macro cell is processed as a black box in ATPG, and thus its inputs are not observable and the outputs are not controllable. This considerably lowers the fault coverage. Inserting flip-flops that can be replaced with scan registers immediately before and after a macro cell can greatly improve the fault coverage. (See Figure 6-12 (a).) If this is not allowed by the specifications, create a mode that bypasses the macro and also add a logic that fixes the macro output. (See Figure 6-12 (b).)

Macro

clock

Macro

ATPGEN

ATPG mode :ATPGEN=1 (a) (b)

Figure 6-12 Consideration for macro cells



g. Internal bus (recommended)

Avoid bus circuit using an internal tri-state cell. It is recommended to use selector logic instead. When using a tri-state cell in the ATPG execution mode, set the cell not to switch by activating only one line. (If a tri-state cell is used, the bus circuit is set to a fixed value, and thus the fault coverage decreases.)

h. External cells with various controls (essential)

The S1L50000 series has input and bi-directional buffer cells with various control pins. These control pins must be set to a fixed value by using the ATPG enable input pins.

• Gating signal (Pin C)

Set pin C to the fixed value using the ATPG enable input pin, ATPGEN, not to gate signals. (When ATPGEN is active, C=1)

i. Others

• The lead time for scan design (from the insertion of scan registers to verification) is approximately 7 days after Epson received the netlist meeting the design rules.

• Running CTS is essential for scan designs. Provide Epson with “Clock Tree Synthesis Check Sheet” attached to “3.3 Clock Tree Synthesis” in Chapter 3.



Scan Design Check Sheet (1/2)

Please fill in this check sheet and send it to Epson. The information you provide Epson by this sheet is required for the scan design and ATPG service. It should be noted the said service is not available unless Epson is provided this check sheet with answers filled in.

Information required for scan design and the result of design check are as mentioned below.

Date: (Month) (Date) , 200X (Year)

Company name:

Your name:

Design information

Top block name:

Target fault coverage: %

Pin information

ATPG enable pin names and trigger edges (Rise/Fall)

Pin name 1: Rise / Fall Pin name 2: Rise / Fall Pin name 3: Rise / Fall

Scan enable pin names and active levels (High/Low)

Pin name 1: “HIGH” / “LOW” Pin name 2: “HIGH” / “LOW” Pin name 3: “HIGH” / “LOW”

Scan clock input pin names and active levels (High/Low)


Scan data input pin name

Pin name:

Scan data output pin name

Pin name:

Asynchronous set/reset pin names and active levels (High/Low)




Scan Design Check Sheet (2/2) Please confirm each description below and tick all that apply.

Scan clock pins meet the rules described in Chapter 6, 6.6.3-b.

Asynchronous set/reset of registers meet the rules described in Chapter 6, 6.6.3-c.

Transparent latches

Not used

The rules described in Chapter 6, 6.6.3-d are met.

The rules described in Chapter 6, 6.6.3-d are not met, and thus lower fault coverage is accepted.

Remark:

Cells and circuits prohibited to use, which are described in Chapter 6, 6.6.3-e, do not exist in the design.

Function macros and RAM cells

Not used

The rules described in Chapter 6, 6.6.3-f are met.

The rules described in Chapter 6, 6.6.3-d are not met, and thus lower fault coverage is accepted.

Remark:

Internal 3-state bus circuits

Not used

The rules described in Chapter 6, 6.6.3-g are met.

The rules described in Chapter 6, 6.6.3-g are not met, and thus lower fault coverage is accepted.

Remark:

External cells with various control pins

Not used

The rules described in Chapter 6, 6.6.3-h are met.

The rules described in Chapter 6, 6.6.3-h are not met, and thus lower fault coverage is accepted.

Remark:

Other remark



6.7 Boundary Scan Design The boundary scan circuit and its controller circuit (TAP controller) compliant with IEEE 1149.1 are added in the periphery of the logic circuit by Epson’s boundary scan (JTAG) insertion service. The BSDL file that describes the information about the circuits is also provided. Epson generates the functional test patterns for the inserted boundary scan circuit and thus customers do not need to generate the patterns.

6.7.1 Boundary Scan Design Flow

Circuit design

Design rule check(snrc)

Design rule check(Check sheet)

ＮＧ

ＮＧ

Yes

Yes

Insert boundary scan registers

Generate test patterns for boundaryscan circuits and BSDL

Netlist of the circuit with boundary scan registers

BSDL

Verification

Please provide Epson with the followingdata:　・Gate-level netlists　・Design information sheet (attached at the end of this chapter.)

Run the design rule checker, "snrc"included in the Epson Design Kit, EPITSto check if the design meets the basicdesign rules for ASIC.

Check if the design meets the followingdesign rules for incorporating boundaryscan registers:

Customer

SeikoEpson

Verify the generated netlists and testpatterns. Verified test patterns are usedfor the pre-shipment test.Test pattern

To thecustomer

Figure 6-13 Design Flow of Circuit with Boundary Scan Registers



6.7.2 Instructions

The following boundary scan instructions are supported.

Table 6-3 Supported instructions and codes

Instruction Code

SAMPLE/PRELOAD 0...10

BYPASS 1...11

EXTEST 0...00

CLAMP Optional (*1)

HIGHZ Optional (*1)

IDCODE 0...01

NOTE: *1: Epson assigns codes if not specified by the customer. Codes must be unique. The instruction bit width should be 2 to 32 bits. Epson also specifies them if not specified by the customer.

6.7.3 Gate Count Estimation

The increase in gate count because of the insertion of boundary scan circuit varies depending on the ASIC series, supported instructions, and instruction bit width. To estimate gate count, use the following information:

Table 6-4 Gate count estimation (in sea-of-gates architecture)

Boundary scan block Gate count

TAP controller＋ miscellaneous gates About 1000 (BCs)

Input pin When using normal cells: about 30 (BCs/pin)

When using cells dedicated to monitor: about 15 (BCs/pin)

2-state output pin About 35 (BCs/pin)

3-state output pin About 65 (BCs/pin)

Bi-directional pin About 95 (BCs/pin)

6.7.4 Design Rules

The logic circuit must meet the following constraints for the boundary scan service. Before releasing the design data, make sure to provide Epson with the design information sheet, confirming the circuit information using the “Boundary Scan Check Sheet” attached at the end of this section. Also please be noted that the service is not available if there is any violation against the design rules.

a. AC /DC test circuits and boundary scan test circuit are mutually exclusive

Boundary scan circuit is not allowed to coexist with test circuits discussed in Section 6, “6.3 Special Test Circuit Provisions for AC and DC tests.”



b. Characters usable for external pin names

External pin names must meet the following constraints imposed by the BSDL format rules:

• Characters allowed to use are alphanumeric characters (a~z, A~Z, and 0~9) and underscore (“_”).

• External pin names are not case sensitive. (CLK and clk are considered identical character strings.)

• External pin names must start with a letter of the alphabet. (0CLK, _CLK are prohibited.)

• External pin names should not include consecutive underscores. (SYS__CLK is prohibited)

• External pin names should not end with an underscore. (CLK_ is prohibited.)

c. Dedicated external pins

Boundary scan circuit always requires five dedicated external pins. Use external pins according to the following rules:

• Clock (TCK)

Clock pin for the boundary scan circuit. Use an input cell with the output port not connected.

• Mode select (TMS)

Mode select pin for the boundary scan circuit. Use an input cell with the output port not connected. The input cell should have a pull-up resistor.

• Data input (TDI)

Scan data input pin for the boundary scan circuit. Use an input cell with the output port not connected. The input cell should have a pull-up resistor.

• Data output (TDO)

Scan data output pin for the boundary scan circuit. Use a 3-state output cell with the input port pulled down.

• Reset (TRST)

Asynchronous reset pin for the boundary scan circuit. Use an input cell with the output port not connected. The input cell should have a pull-up resistor.

IBC U1 ( .PAD(TCK) ); // IBC: Normal input cell IBCP1 U2 ( .PAD(TMS) ); // IBCP1: Input cell with pull-up resistor IBCP1 U3 ( .PAD(TDI) ); IBCP1 U4 ( .PAD(TRST) ); TB1 U5 ( .PAD(TDO), .A(1’b0),.E(1’b0) ); // TB1: 3-state output cell

Figure 6-14 Sample verilog descriptions of dedicated pins



d. Hierarchical design blocks

The netlist should have the following hierarchical structure. Hierarchical blocks such as TAP controller are added when the boundary scan chains are inserted.

• Place the I/O cells in the top block.

• Place other logic circuits in the sub block immediately lower than the top block.

Figure 6-15 Structure of hierarchical blocks

e. I/O cell types

Boundary scan is not supported if the following I/O cells are used:

• I/O cell with test mode

• Gated input cell

• Open-drain output cell

f. External pins for analog signals

Boundary scan cells are not inserted for the I/O pins for the oscillation circuit and those for analog signals.

g. Multi bonding and multi pad

Boundary scan is not supported if multi bonding or multi pad is used.

User logic

I/O cells

Block including BSR

TAP controller



Boundary scan check sheet

Check the following items on this page and then provide Epson with the information requested on the next page. If any violation against the rules is found or any essential information is missing, boundary scan is not available.

Before releasing the netlists, confirm the following:

(a) For instructions possible to support, see Table 6-3.

(b) Boundary scan circuits and “Special Test Circuit Provisions for AC and DC Tests” discussed in Section 6.3 of Chapter 6 cannot be used together.

(c) Make sure that external pin names are compliant with the rules described in “Characters usable for external pins” in Section 6.7.4-b of Chapter 6.

(d) About dedicated pins

• Make sure the 5 dedicated pins have already been in the netlists.

• Use input cells with a pull-up resistor for pins assigned to TMS, TDI, and TRST.

• Use 3-state output cell for the pin assigned to TDO.

• Make sure that dedicated pins are not shared with other functions.

(e) Place the I/O cells in the top hierarchical level.

(f) Do not use I/O cells described in Section 6.7.4-e of Chapter 6.

(g) Boundary scan cells cannot be inserted for the I/O pins for the oscillation circuit and those for analog signals.

(h) Make sure that multi bonding and multi pads are not used.



Design Information Sheet (Please fill in this check sheet and send it to Epson before releasing the design data.)

Information required for scan design is as mentioned below.

Date: (Month) (Date) 200X (Year)

Company name:

Your name:

Design information

Top block name:

1． Desired instuctions (Tick those desired)

Essential instruction CLAMP instruction HIGHZ instruction IDCODE instruction

→→→→

Codes are compliant with table 10-4 Desired code ___________________ (*1) Desired code ___________________ (*1) Code is compliant with table 10-4

2．Instruction bit width (Tick the one that apply)

not specified specified

→→

Specified by Epson Bit width _____________________ bits (*2)

3. Selection of boundary scan cells

Provide Epson with the following information only when the customer desires to select the boundary scan cells. Even when the information is not provided, Epson performs the following:

• Use boundary scan cells dedicated to observation for the system clock or asynchronous reset pin in some cases.

• Do not insert boundary scan cells for the input and output pins used for analog signals.

External pin names using boundary scan cells dedicated to observation:

External pin names that do not desire to have boundary scan cells inserted:

Remark:

Dedicated pin information (Describe the external pin names assigned to the following boundary scan circuit pins.)

TCK: TMS: TDI: TDO: TRST:

User circuit information

System clock name:

Asynchronous reset name:

Top block name:

Sub block name (*3):

NOTE: *1: Do not duplicate codes. If not specified, Epson will assign them. The bit width should match the instruction bit width mentioned in 2.

*2: Specify the bit width within the range from 2 to 32 bits.

*3: Describe all the sub blocks immediately below the top block. If buffers or delay elements inserted for delay adjustment or other purposes exist in the top block, also describe their instance names.

Chapter 7 Propagation Delay and Timing


Chapter 7 Propagation Delay and Timing Propagation delay time (Tpd) is dependent on a number of factors such as supply voltage, ambient temperature and manufacturing process conditions. It is also affected by output loading (wire capacitance and fan-out count), input signal slew time, input logic level, and the Miller effect due to circuit configurations.

With a delay calculator that considers these variable factors, the S1L50000 Series provides design environment where highly accurate delay estimation is possible. Therefore, it should be noted that delay values obtained by the delay calculator do not always match those you derived from the simple equation mentioned below, using the values given in the “S1L50000 Series Gate Array Cell Library.”

7.1 Relationship between Ta and Tj The CMOS IC delay is basically dependent on junction temperature (Tj). However, what is typically provided in the IC specification sheet is the ambient temperature (Ta), though the relationship between Tj and Ta varies depending on the IC package thermal resistance and IC power dissipation. (For more information, refer to Section 9.2, “Power Dissipation Limits.”

In the case of ASICs, circuits and applications determine packages and power dissipations, and defining specifications at Ta is technically difficult. Thus for the S1L50000 Series, the following delay libraries are offered for early stage design verification:

* Tj=0 to 85[°C] delay library as Ta=0 to 70[°C] delay library

* Tj=-40 to 125[°C] delay library as Ta=-40 to 85[°C] delay library

If the Ta and Tj ranges significantly differ due to the package and the estimated power dissipation, the Tj=-40 to 125[°C] delay library will be used instead of the Ta=0 to 70[°C] delay library. Also please be noted that additional constraints may be imposed depending on case.

7.2 Calculation of Propagation Delay The following is the equation for calculating the propagation delay with ease. In this equation, the greater the load capacitance, the greater the error in delay. Because the delay value derived from this equation is smaller than the result of delay calculator, it should be used only as a reference.

(1) Delay times of input cells and internal cells

The propagation delay times (Tpd) of input cells or internal cells are the sum of the cell’s intrinsic delay (T0), the delay due to capacitance load of wiring coming out from the cell’s output pin, plus input loads driven by the cell output pin. In other words, the propagation delay time Tpd is derived from the following equation:

Tpd = T0 + K × (Σ Load A + Load B) --- (Equation 7-1)

Where

T0 : Cell intrinsic delay [ps] K : Incremental delay due to fan-out loading [ps/LU] Load A : Input loads driven by the cell output pin [LU] Load B : Capacitance load due to wiring length [LU]

NOTE 1: The T0 and K values vary depending on the operating voltage, ambient temperature and manufacturing process variations. Use the values given in the “S1L50000 Series Cell Library.”



NOTE 2: The unit “LU” stands for Load Unit. In the S1L50000 Series, the input pin capacitance of the inverter cell (IN1) is defined as 1LU.

(2) Output cell delay times

The propagation delay times (Tpd) of output cells are derived from the following equation:

Tpd = T0 + K × CL / 10 --- (Equation 7-2)

Where

T0 : Output cell intrinsic delay [ps] K : Incremental delay due to output cell fan-out load [ps/10pF] CL : Load capacitance driven by external output pin [pF]

The T0 and K values in Equation 7-1 and 7-2 described above vary depending on the operating voltage, ambient temperature, and process conditions. Their values under the Min., Typ., and Max conditions, which are defined below, are given in the “Gate Array S1L50000 Series MSI Cell Library.” Use the values under the conditions that suit your purpose.

Min. state: VDD = Highest Ta = Lowest Process = Best case Typ. state: VDD = Nominal Ta = 25°C Process = Nominal case Max. state: VDD = Low Ta = Highest Process = Worst case

The delay values under the Min and Max conditions are important when verifying that circuit delay times are within the specified range even with variations in VDD, Ta and process conditions.

The overall de-rating factor (M) is possible to calculate by the following equation:

M = MV × MT × MP --- (Equation 7-3)

MV: De-rating factor due to variance in supply voltage MT: De-rating factor due to changes in temperature MP: De-rating factor due to manufacturing process variation

Table 7-1 shows derating factor values within the specified range. For values outside the specifieid ranges of supply voltages and ambient temperatures, contact your Epson sales representative.



Table 7-1 De-rating Factor (M)

M (Ta=0 to +70°C*1)

M （Ta=-40 to +85°C*2

）Conditions Min. Typ. Max. Min. Typ. Max.

HVDD＝5.0V 0.65 1.00 1.51 0.62 1.00 1.57

VDD or LVDD＝3.3V±0.3V 0.65 1.00 1.51 0.62 1.00 1.57I/O Buffers

VDD or LVDD＝2.0V±0.2V 0.39 1.00 2.94 0.39 1.00 3.38

VDD＝3.3V±0.3V 0.60 1.00 1.60 0.58 1.00 1.67MSI Cells

VDD＝2.0V±0.2V 0.42 1.00 2.49 0.42 1.00 2.68

*1: This temperature range is specified assuming Tj = 0 to +85°C.

*2: This temperature range is specified assuming Tj = -40 to +125°C.



7.3 Input Capacitance Load (Load A) The delay time of a logic gate depends on the sum of input capacitance (fan-in) driven by the gate output pin. Input capacitance (fan-in) of each gate and the limit on the load of output pin (fan-out) are given in the “Gate Array S1L50000 Series MSI Cell Library.” Care must be taken that the total fan-in values do not exceed the output fan-out value.

• Example of Calculating Load A The following shows an example of how to calculate Load A using the schematic in Figure 7-1 and the data shown in Table 7-2.

Figure 7-1 Sample Schematic for Calculating Load A

Table 7-2 Sample Data Used to Calculate Load A

Input Output Cell

Pin Fan-in Pin Fan-out IN1 A 1.0 X 23.6 IN2 A 2.1 X 47.2

NA2 A1 A2

1.0 1.0 X 23.3

NO2 A1 A2

1.0 1.0 X 11.8

The fan-in values of IN2, NA2, and NO2 are given in Table 7-2. The sum of those values is ΣLoad A.

Σ Load A (N1) = (fan-in of IN2) + (fan-in of NA2) + (fan-in of NO2)

= 2.1 + 1+ 1 = 4.1

IN1 IN2

NA2

NO2

2.1

1

1



7.4 Wire Capacitance Load (Load B) The load due to interconnects between cells (Load B) is not possible to correctly estimate unless actual layout is done. However, Load B has a correlation with the number of nodes driven by the cell’s output, and thus statistic estimation is possible. Pre-layout wire capacitance of each master is given in the “Gate Array S1L50000 Series MSI Cell Library.”

7.5 Estimation of Propagation Delay Time The following shows an example of propagation delay estimation using the schematic in Figure 7-2 (Operating voltage of 3.3V) and the data in Table 7-3.

Figure 7-2 Sample Schematic for Propagation Delay Estimation

Table 7-3 Characteristics of Each Cell (3.3V Supply Voltage)

Input Output Delay Characteristics (Typ.) Cell

Pin Fan-In [LU] Pin Fan-Out

[LU] From To Parameter T0 [ps]

K [ps/LU]

tpLH 53 23.2 IN1 A 1.0 X 23.6 A X tpHL 62 12.8 tpLH 45 11.7 IN2 A 2.1 X 47.2 A X tpHL 50 6.4 tpLH 70 23.2 NA2 A1 1.0 X 23.3 A X tpHL 66 21.9 tpLH 70 45.0 NO2 A1 1.0 X 11.8 A X tpHL 74 12.8

The propagation delay is calculated assuming the Load B of Node P is 2 (LU). In addition, the intrinsic delay time, rising and falling times of each output pin must be considered.

IN1 IN2

NA2

NO2

2.1

1

1

A

P

B

C

D



• Delay times of the paths from A to B, A to C, and A to D. (Under the Typ. condition)

In the following equations, the up arrow (↑) signifies rising time, and the down arrow (↓) signifies falling time. The rising and falling times are the transition time of output pin X.

Tpd (A↓→P↑) = T0 (↑) + K (↑) × (Σ Load A + Load B) = 53 + 23.2 × (4.1 + 2) = 194.5 [ps]

Tpd (A↑→P↓) = T0 (↓) + K (↓) × (Σ Load A + Load B) = 62 + 12.8 × (4.1 + 2) = 140.1 [ps]

Then, estimate the delay times of the paths from A to B, A to C, and A to D. In this case, B, C, and D have no loads and thus each cell’s intrinsic delay is added to the delay values above. Pay attention to whether each output is rising or falling.

1. A→B path delay = IN1(A→P delay) + IN2 (P→B delay)

Tpd (A↑→B↑) = Tpd (A↑→P↓) + Tpd (P↓→B↑) = 140.1 + 45 = 185.1 [ps]

Tpd (A↓→B↓) = Tpd (A↓→P↑) + Tpd (P↑→B↓) = 194.5 + 50 = 244.5 [ps]

2. A→C path delay = IN1(A→P delay) + NA2 (P→C delay)

Tpd (A↑→C↑) = Tpd (A↑→P↓) + Tpd (P↓→C↑) = 140.1 + 70 = 210.1 [ps]

Tpd (A↓→C↓) = Tpd (A↓→P↑) + Tpd (P↑→C↓) = 194.5 + 66 = 260.5 [ps]

3. A→D path delay = IN1 (A→P delay) + NO2 (P→D delay)

Tpd (A↑→D↑) = Tpd (A↑→P↓) + Tpd (P↓→D↑) = 140.1 + 70 = 210.1 [ps]

Tpd (A↓→D↓) = Tpd (A↓→P↑) + Tpd (P↑→D↓) = 194.5 + 74 = 268.5 [ps]



7.6 Output Buffer Delay Estimation If the load capacitance driven by the output buffer is CL, the delay time Tpd of the output buffer is derived from the following equation:

tpd = T0 (Output cell) + K (Output cell) × CL/10

T0 (Output cell) : Output cell intrinsic delay [ps]

K (Output cell) : Incremental delay due to output cell fan-out load [ps/10pF]

CL : Load capacitance driven by cell’s output pin [pF]

For the output cell intrinsic delay and incremental delay due to output cell fan-out load, refer to the “S1L Series Gate Array MSI Cell Library.”

7.7 Setup and Hold Time for Flip-Flops To get desired functions by logic circuits, it is important to apply signals at the correct timing to flip-flops and MSI sequential circuits using flip-flops. What is deeply concerned about this signal input is the setup time and hold time for flip-flops. Data input not in time for the setup time and data changed without waiting for the hold time are not correctly written to the FF circuit. The setup and hold times must be met by the design.

1) The minimum pulse width

If the pulse shorter than the minimum pulse width is input to flip-flops and MSI circuits using flip-flops, the signal becomes not only invalid, but also causes errors. There are three minimum pulse widths:

• The minimum pulse width of clock signal

• The minimum pulse width of set signal

• The minimum pulse width of reset signal

2) Setup time

Data state must be set before the active edge of clock pulse changes so that flip-flops and MSI circuits using flip-flops can properly read data. The time required to set the data state is called setup time.

3) Hold time

Data state must be retained after the active edge of the clock pulse occurs so that flip-flops and MSI circuits using flip-flops can properly read data. The time required to retain the data state is called hold time.



4) Release time (setup)

Flip-flops and MSI circuits using flip-flops require some time to change the clock pulse after the set/reset state is cancelled (setup). This time is called release time (setup).

5) Removal time (Hold)

Flip-flops and MSI circuits using flip-flops require some time to retain the set/reset input state after the clock pulse occurs. This time is called removal time (hold).

6) Set-reset setup time (Recovery)

Flip-flops and MSI circuits using flip-flops require some time for the reset signal to rise after the set input state is cancelled. This time is called set-rest setup time (recovery).

7) Set-reset hold time (Recovery)

Flip-flops and MSI circuits using flip-flops need to retain the signal states at the rising time of reset until the next set signal rising time. This time is called set-rest hold time.

For timing error messages that appear during the simulation, refer to the manual of each tool.

Figure 7-3 DFSR

D

C

S

R

Q

XQ

DATA

CLOCK

SET

RESET

Q

XQ



Figure 7-4 Timing Waveforms 1 (for statements (1) to (5) above)

Figure 7-5 Timing Waveforms 2 (for statements (6) and (7) above)

The setup and hold times of the S1L50000 Series flip-flops are given in the “Gate Array S1L50000 Series MSI Cell Library.” Pay attention to the characteristics of each cell, when using the timing data in the library.

CLOCK

PulseWidth

Pulse Width DATA

SETUP HOLD

SET (RESET)

PulseWidth

RELEASE (SETUP)

REMOVAL(HOLD)

SET (RESET)

SET RECOVERY

(SETUP)

RECOVERY(HOLD)

SET

RESET

Chapter 8 Test Pattern Generation


Chapter 8 Test Pattern Generation There are few constraints on test patterns you prepare for Epson to verify the IC design specifications. For example, if running simulation on the IC alone ends in a reasonable period of time, there are no constraints on the test pattern size.

However, test patterns for pre-shipment testing must meet the constraints due to the tester’s capability, and thus Epson generates them by modifying the test patterns used for the design verification. Therefore, when generating test patterns for design verification, the following constraints should be kept in mind.

8.1 Testability Considerations Test patterns are used for pre-shipment testing and thus they should be capable to verify all the internal circuits of the LSI. If any part of the LSI internal circuits is not tested with test patterns, defective devices could be undiscovered and shipped. However, it is difficult to test all the internal circuits of an LSI, so it is important to consider testability provisions in the design phase.

By inserting a test circuit recommended by Epson, the DC test and other conditions required by test patterns are allowed to set with ease. For details, see Section 6.5 of Chapter 6, “Test Circuit for Function Cells.”

8.2 Usable Waveforms Test patterns are normally collections of “0” and “1.” However, when running simulation or testing by the LSI tester, it is possible to delay input waveforms, or generate pulses. There are two patterns of waveforms usable when generating test patterns.

• NRZ (Non Return to Zero)

The waveform normally used for signals other than clock signal. The NRZ signal changes its level once per cycle time and it can be delayed.

• RZ (Return to Zero)

The waveform typically used for a clock signal. It generates one positive or negative pulse per cycle and thus effectively generates a clock signal. Like the NRZ signal, the RZ signal can be delayed.

Figure 8-1 Constraints on Timing Setup

NRZ waveform

RZ waveform

Output waveform

Strobe

Test rate Input delay Pulse width



8.3 Constraints on Test Patterns This section describes the constraints on test patterns for pre-shipment testing.

8.3.1 Test Rate and Event Count

The following are the constraints on test rate (tester speed) and event count:

Test rate: 100 nsec at minimum; possible to change in increments of 1nsec (Standard: 200 nsec)

Event count per test pattern: Up to 256K events

Test pattern count: Up to 30 patterns

Total event count of test patterns: Up to 1M events

8.3.2 Input Delay

The following are the constraints on the input delay time:

(a) Input delay range

Allowable delay is in the following range: 0 nsec ≤ Input delay value < Strobe point

For the limits of strobe point, refer to Section 8.3.5 of Chapter 8, “Strobe.”

(b) Phase difference of input delays

Phase difference of input delays must be greater than 3 nsec.

(c) Limits on different delay count

Up to 8 different delay values are allowed to set in one test pattern. 0 nsc is counted as one delay value. Delays of the same value but of different waveforms (RZ and NRZ) or pulses are also counted as different delays.

8.3.3 Pulse Width

The pulse width of RZ waveform must be greater than 15 nsec.

8.3.4 Input Waveform Format

The values 0, 1, P, and N can be used in the input waveforms. P and N here indicate the pulse inputs in the RZ waveforms. The combination of 0 and P, or 1 and N is allowed to use for one identical pin within one test pattern.

In the case of bi-directional signal pins, the RZ waveforms are allowed to use only when no output states exist in one test pattern.

8.3.5 Strobe

The following are constraints on strobe:

(a) Only one strobe is defined for each test pattern.

(b) The minimum strobe point must be at least 30 nsec later than all the output signal states changed by the input signals in all events.

(c) The maximum strobe value must be smaller than the test rate (tester speed), 15 nsec.

(d) Strobe is set in increments of 1 nsec.



8.4 Notes on DC Test Test patterns are used not only for functional tests but also for DC test, such as the measurement of output voltage. Generate test patterns that allow the following DC test. However, if the special test circuit for AC and DC tests explained in Section 6.3 of Chapter 6 is adopted, the test patterns discussed in this section are not required.

DC test is to verify the DC parameters of LSI. They are measured at the end of a test event. Therefore, the test pins should retain the same state in the test event after the strobe. The DC test parameters are as follows:

(a) Output characteristics (VOH, VOL)

The current drivability of output buffer is tested. With the test pins driven to the target output level, the voltage drop is measured when the specified current load is applied.

To test the output characteristics, the test patterns should include all possible states of target pins. Also, those states must remain during the test event even if the test rate is indefinitely extended.

(b) Quiescent current (IDDS) test

Quiescent current is leakage current that flows through the LSI power supplies when the input signals are stable. This current is normally very small, and thus it should be measured when no other currents are flowing. For this, all the following conditions must be met. Also, there should be two or more events where quiescent current is measurable.

(1) Input pins are all stable.

(2) Bi-directional pins are either input or output state.

(3) There are no active elements in the circuit, including the oscillator.

(4) Internal 3-state buffers (internal bus) are neither floating nor in contention.

(5) Current is prevented from flowing through RAM, ROM, and mega cells.

(6) Input pins with pull-up resistor are driven high.

(7) Bi-directional pins with pull-up resistor are driven high, or have high-level output

(8) Bi-directional pins with pull-down resistor are in the input state, or have low-level output

(c) Input current test

The parameters related to the inputs of input buffers, including input leakage current, pull-up and pull-down currents are tested. This test is implemented by measuring the current that flows when the VDD or VSS level voltage is applied to the target pin. That is, either high- or low-level voltage is applied to the pins under test.

For example, if the VDD level (high level) voltage is applied to the target signal pin of the low-level voltage, the signal level changes from low to high, and unintended behavior may occur to the LSI.

To test the input current, the VDD level voltage is applied to the target pin in the event where the pin is driven high, and the VSS level voltage is applied when the pin is driven low. Therefore, these states of the target signal pins must exist in test patterns for testing.



Input current tests are further divided into the following tests:

(1) Input leakage current test (IIH, IIL)

Tests the parameters related to the input current of input buffer without pull-up or pull-down resistor.

The current that flows when high-level voltage is applied to the input buffer is called IIH, and guaranteed up to the maximum value specified. To implement this test, the test patterns must have events where high-level signals are input to the pins under test. In the case of bi-directional pins, the high-level signals must be input while they are in the input state.

The current that flows when low-level voltage is applied to the input buffer is called IIL, and guaranteed up to the maximum value specified. To implement this test, the test patterns must have events where low-level signals are input to the pins under test. In the case of bi-directional pins, the low-level signals must be input while they are in the input state.

(2) Pull-up current test (IPU)

Measures the current when the low-level voltage is applied to the input buffer with pull-up resistor. To implement this test, the test patterns must have events where low-level signals are input. In the case of bi-directional pins, the low-level signals must be input while they are in the input state.

(3) Pull-down current test (IPD)

Measures the current when the high-level voltage is applied to the input buffer with pull-down resistor. To implement this test, the test patters must have events where high-level signals are input. In the case of bi-directional pins, the high-level signals must be input while they are in the input state.

(4) Off-state leakage current (IOZ)

Measures the leakage current that flows to the open-drain or 3-state output buffer when the output state is high impedance. Measures the current when the VDD-level or VSS-level voltage is applied to the test pins in the high impedance state. Therefore, the test patterns must have the events where test pins are in the high-impedance state.



8.5 Notes When Using Oscillator Circuit In the oscillator circuit like the one shown in Figure 8-2, the oscillator output waveform does not correctly propagate to the gate connected to the oscillator output because of the small drivability of the oscillation inverter, and the load due to the test environment.

G

E

X

D

LIN

LOT

PAD

PAD

Gate signal

Enable signal Drain signal

Clock signal

G X

D

LIN

LOT

PAD

PADGate signal

Drain signal

Clock signal

Oscillator Cell

Oscillator Cell

Figure 8-2 Example of Oscillator Circuit

To reproduce the signal states during the simulation on the LSI tester, invertedly driven signals are input to the drain pin. (i.e., signals having the same waveforms as the signals output to the drain are input to the drain pins.)

If the oscillation inverter is composed of inverters, it generates an invertedly driven signal simply by inputting the signal having the inverted waveform to the drain. However, if the oscillator inverter is composed of NAND gates (called gated-OSC), the waveform to be inverted is determined by the expected value of the drain pin, because it is not possible to determine only by the gate signal.

By this method, if the input waveform is NRZ type, and the strobe point is at the end of the test cycle, inverted waveform is generated using the expected values of the drain pin. However, in the case of the RZ waveform, the expected value of the drain pin is fixed to “H” or “L” whether the oscillator is enabled or disabled and thus it is not possible to determine the waveform to invert by the expected value of the drain pin.

When using the gated oscillator, care must be taken for the following:

1. RZ waveform is not allowed to use for input signals

2. Clock signal should not be changed by the change of an enable signal



8.6 AC Test AC test is a test to measure the time taken for a signal change occurred to the input pin to propagate to the output pin. The AC test path is selected by the customer. However, the test circuits discussed in Section 6.3 of Chapter 6, “Special Test Circuit Provisions for AC and DC tests” are adopted, the AC test path explained in this section is not required.

8.6.1 Constraints on Test Events

The test method is usually called “binary search” and the target test pin should have only one change point in a test event. (Pins that output RZ waveforms cannot be tested. Also pins that output hazard in the test event are not possible to test, either.) Signal changes allowed to test are “High” to “Low” or “Low” to “High.” (Changes concerned about High impedance are not possible to test.)

Also, care must be taken when selecting test events. Events where many output signals simultaneously change, and those where bi-directional and LSI tester signals are in contention should be avoided. Too many simultaneous signal changes and signal contention cause unstable power supply and this affects the output waveforms of test pins and makes the correct AC testing impossible.

8.6.2 Constraints on AC Test Points

The number of AC test points is limited to 4.

8.6.3 Constraints on Test Path Delay

The accuracy of AC test increases as the delay of test path increases. Set the test path delay greater than 30nsec and smaller than the strobe point for the Max. condition of test simulation.

8.6.4 Other Constraints

(1) Do not use the path from the oscillation circuit.

(2) Use the path not passing through the internal 3-state circuit (internal bus)

(3) Do not use the path passing through a bi-directional cell between the test path input buffer and output buffer

(4) When the IC is used in multiple operating voltage ranges, test the IC within one voltage range.

8.7 Constraints on Test Patterns of Bi-directional Pin It is not possible to switch the input and output modes of bi-directional pins multiple times within one event due to the limits of the LSI tester. Therefore, generate test patterns so that RZ waveform is not used for switching input and output modes of the bi-directional cell.



8.8 Notes on High-Impedance State Epson prohibits high-impedance state of CMOS device input pins during simulation, as the functions are not possible to guarantee.

As a solution to high-impedance, I/O cells with pull-up or pull-down resistors are released. However, because of the following reasons, propagation delay times of pull-up and pull-down resistors are not considered. This does not allow correct function simulation, and thus open state of bi-directional pin with pull-up or pull-down resistor in input mode is also prohibited.

The reasons why the propagation delay of pull-up and pull-down resistors is not considered:

• Delay varies significantly depending on the external load capacitance.

• Pull-up and pull-down resistors are only intended to avoid floating gates due to the high-impedance state.

Before running simulation, Epson checks if test patterns are violating the said constraints or not using a tool. If “Z” that indicates high-impedance state is detected, the test pattern needs to be modified. A warning is also given for the “Z” of bi-directional pins with pull-up or pull-down resistor because of the reasons explained earlier. Bi-directional pins with open-drain are also treated the same.

<Measures>

The test pattern check program outputs errors for all “Z” of bi-directional pins. (The “Z” of 3-state and open-drain output pins is excluded.)

To avoid this error output, a utility program is offered which replaces “Z” of bi-directional pins with pull-up resistor to “1” and “Z” of those with pull-down resistor to “0.”

If a bi-directional pin goes into the input mode while “X” is output, “X” is propagated as an input signal during the simulation regardless of whether the pin is pulled-up or pulled-down. The “X” is replaced with “?” in the simulation result. Correct the “?” and run simulation again.

Table 8-1 Handling the Signal at the Bi-Directional Pins in Simulation

Input pattern I/O mode Simulation Simulation result (Output pattern)

“X” Input mode “X” “?”

“1”, “H” Input mode “1” “1”

“0”, “L” Input mode “0” “0”

Chapter 9 Calculating Total Power Consumption


Chapter 9 Calculating Total Power Consumption CMOS LSI chips consume power in proportion to the operating frequency when they are active, though almost no current flows when not active. As the power consumption increases, the heat generated on the chip grows. Increases in this heat affect overall chip performance. Therefore, the designer needs to estimate the chip power consumption and ensure the value is within the allowable range. In this chapter, the way to calculate the total power consumption of S1L50000 series LSI chips is discussed.

9.1 Calculating Power Consumption The power consumption of the CMOS circuit is generally dependent on the operating frequency, load capacitance, and power supply (except special circuits where stationary current flows, such as RAMs and ROMs). To estimate the total power consumption, obtain the power consumption of each block in the internal circuit first, and add them up. Then obtain the power consumption of input and output buffers, and add up these values, too. Use the following formula to calculate the total power consumption, Ptotal.

Ptotal = Pint + Pi + Po

where

Pint is the power consumption of internal circuits

Pi is the power consumption of input buffers Po is the power consumption of output buffers

9.1.1 Internal Cell (Pint)

The power consumption by internal cells is dependent on the used gate count, cell utilization, operating frequency and the ratio of cells that operate at the operating frequency. To calculate, use the following formula:

Pint = ∑=

K

1i (Nb×U) × fi × Spi × Kpint [W]

Nb : Number of basic cells

U : Cell utilization ratio fi : Operating frequency in MHz Spi : Ratio of basic cells that operate at the operating frequency [MHz] to the total basic cell count (target 20 to 30%, depending on the system, though.) Kpint : Power consumption /BC, see Table 9-1

Table 9-1 Kpint/BC of S1L50000 Series

VDD (TYP) Kpi

3.3V 0.70µW/MHz

2.0V 0.25µW/MHz



9.1.2 Input Buffers (Pi)

The power consumption by input buffers is the total sum of the products of the operating frequency in MHz and the power coefficient Kpi [µW/MHz].

Pi = ∑=

K

1i (Kpi × fi) [µW]

where

fi : Input buffer operating frequency in MHz Kpi : Input buffer voltage coefficient (See Table 9-2)

Table 9-2 S1L50000 Series Input Cell Kpi

VDD (TYP) Kpi

3.3V 6.2µW/MHz

2.0V 2.0µW/MHz

9.1.3 Output Buffers (Po)

The power consumption by output buffers is different whether the load is DC load (resistive load by the connection with TTL device) or AC load (capacitive load by the connection with CMOS device). The output buffer consumption (Po) is obtained by the following formula:

Po = PAC + PDC

where PDC is the DC power consumption, and PAC is the AC power consumption.

9.1.3.1 AC Power Consumption (PAC)

Approximate AC power consumption is obtained by the following formula:

PAC = ∑=

K

1ifi × CL × (VDD)

2

where

fi : Output buffer operating frequency [Hz] CL : Output load capacitance [F] VDD : Power supply voltage [V]

9.1.3.2 DC Power Consumption (PDC)

Approximate DC power consumption is obtained by the following formula:

PDC = PDCH + PDCL

PDCH = |IOH| × (VDD* - VOH)

PDCL = IOL × VOL



The ratio of PDCH to PDCL is determined by the duty ratio of output signal.

T

T1 T2

Figure 9-1 Example of Duty Cycle

In Figure 9-1,

Duty H = (T1 + T2) / T Duty L = (T - T1 - T2) / T

PDC = PDCH + PDCL

= ∑=

K

1i (VDD* - VOHi) × IOHi × Duty H + ∑

=

K

1i [VOLi × IOLi × Duty L]

* HVDD or LVDD for dual power supply

9.1.4 Low Power Cells

Low-power cells are available to achieve lower power consumption. Using low-power cells increases the propagation delay time compared to the normal cells, but the power consumption decreases by about 80%. When using the low power cells, calculate the power consumption multiplying the Kpint/BC in Table 9-1 by 0.8. Table 9-3 shows the examples of low-power cells.

9.1.5 Low Noise Cells

Low noise cells are effective to reduce EMI noise to the customer’s product. The peak operating current due to the flip-flop cell operation is lowered as much as possible to reduce the effect on the delay propagation.

When using the low-noise cells, calculate the power consumption multiplying the Kpin/BC in Table 9-1 by 0.7. Table 9-3 shows the examples of low-noise cells.

Table 9-3 S1L50000 Series Low-power/Low-Noise Cells

Normal cell Low-power cell *1 Low-noise cell *2

DF D-Flip Flop DFL D-Flip Flop DFLQ D-Flip Flop

JKR JK-Flip Flop JKRL JK-Flip Flop -

LF Latch LFR Latch -

Notes: *1: In addition to the cells shown, scan cells are also available. (A total of 31 cells)

*2: In addition to the cells shown, scan cells are also available. (A total of 12 cells) For details, refer to the “Gate Array S1L50000 Series MSI Cell Library.”

Figure 9-2 illustrates how effectively low-noise cells reduce the EMI noise. The data shown is an example obtained from the evaluation using Epson’s test samples, and thus they are not guaranteed in the customer’s designs.



Figure 9-2 VDD Current Spectrum according to the IEC 61967-1, 6 (MP method)

9.2 Limit on Power Consumption The LSI chip temperature increases as the power consumption increases. When assembled in a package, the LSI chip temperature is possible to calculate from the ambient temperature Ta, package thermal resistance θj-a and power dissipation PD.

Chip temperature (Tj) = Ta + (PD × θj-a) (°C)

For normal operations, keep the chip temperature (Tj) lower than 125°C. For the thermal resistance of each package, refer to Table 9-4. The values shown in Table 9-4 considerably change depending on the mount board conditions and forced air cooling.



Table 9-4 Thermal Resistance of Each Package

θj-a（°C/W） Package type Pin

count 0 m/s 1 m/s 2 m/s

θj-c

(°C /W)Remark

QFP5 - 36 32 30 8

QFP8 - 27 24 23 8

QFP10 - 23 21 20 8

QFP12 - 51 46 44 6

QFP13 - 48 45 43 6

QFP14 - 44 41 39 6

QFP15 - 41 39 37 6

QFP20 - 36 33 31 6

QFP21 - 34 31 29 6

QFP22 - 27 24 23 6

QFP23 - 26 24 23 8

TQFP12 - 53 47 45 4

TQFP13 - 47 44 42 4

TQFP14 - 43 40 38 4

TQFP15 - 42 36 34 4

TQFP24 - 39 37 35 4

Mount board: JEDEC STD board

(114.3 x 76.2 x 1.6mm, 4-layer)

Lead frame: Cu

Depending on conditions,

- θj-a changes at a maximum of ±15°C/W

- θj-c changes at a maximum of ±3°C/W

PBGA1U 2-layer 256 24 21 20 4

PBGA1U 4-layer 256 19 17 16 4

PBGA3U 2-layer 324 23 20 18 5

PBGA3U 4-layer 484 18 15 14 5

PBGA4U 2-layer 256 22 19 18 6

PBGA6U 2-layer 388 19 17 16 6

PBGA6U 4-layer 388 14 12 11 6


(114.3 x 76.2 x1 .6mm, 4-layer)




PFBGA7UX - 34 31 30 3

PFBGA8UX - 31 28 27 3

PFBGA10UX - 30 22 21 3

PFBGA12UX - 24 21 20 3

PFBGA14UX - 22 20 19 3

PFBGA16UX -

20 18 17 3


(114.5 x 101.5 x 1.6mm, 4-layer)




* Values are shown only for reference.

Chapter 10 Pinout and Simultaneous Output Switching


Chapter 10 Pinout and Simultaneous Output Switching This chapter discusses the points the designer needs to pay special attention when deciding package pinout and adding power supply pins to avoid malfunctions due to simultaneous switching of output pins.

10.1 Estimating Power Supply Pin Count The designer needs to estimate the power supply pin count according to the LSI power consumption and output buffer count. Care must be taken especially for output buffers, as significant amount of transient current flows when they switch. The greater the output buffer drivability is, the larger transient current flows.

The following describes how to estimate the power supply pin count required for an LSI in relation to the consumption current:

(1) Single power supply

If the consumption current is IDD [mA], the power supply pin count NIDD is estimated as follows in relation to the consumption current:

NIDD ≥ IDD / 50 (pair)

That is, up to 50mA can be supplied to one pair of VDD and VSS pins.

Notes:

a. At least one pair of power supply pins must be inserted in each side of the package. That is, at least 4 pairs of VDD and VSS pins are inserted for each package. To obtain IDD, calculate the power consumption using the formula discussed in Section 9.1 of Chapter 9, “Calculating Power Consumption,” and then divide the power consumption by the operating voltage.

b. If the output buffer is connected to DC load and current steadily flows, power supply pins need to be added. For details, contact our sales representative.

(2) Dual-power supply

The maximum allowable current for one pair of power supplies (both HVDD and LVDD power supplies) is the same as single power supply. Required number of power supply pairs must be separately calculated for HVDD and LVDD.

i. HVDD power supply pin count

If the HVDD consumption current is IDD (HVDD) [mA], the power supply pin count NIDD (HVDD) for this consumption current is estimated as follows: NIDD (HVDD) ≥IDD (HVDD)/50

That is, up to 50mA can be supplied to each pin.

ii. LVDD power supply pin count

If the LVDD consumption current is IDD (LVDD) [mA], the power supply pin count NIDD (LVDD) for this current consumption is estimated as follows:

NIDD (LVDD) ≥ IDD (LVDD) / 50




iii. VSS power supply pin count

NIDD (VSS) ≥ IDD (HVDD) + IDD (LVDD) / 50


Notes:

a. At least one pin of HVDD, LVDD, and VSS power supplies must be inserted in each side of the package. That is, at least 4 pins of each power supply are inserted for each package. IDD is the value obtained by dividing the power consumption calculated using the formula in Section 9.1 of Chapter 9, “Calculating Power Consumption” by the operating voltage.

b. When the output buffer is connected to DC load and current steadily flows, power supply pins need to be inserted. For details, contact your Epson sales engineer.

c. When adding power supply pins to cope with simultaneous output switching, add HVDD, LVDD, and VSS power pins separately for HVDD and LVDD output buffers.



10.2 Simultaneous Switching and Power Supply Addition In the S1L50000 series, the maximum output drivability is as high as 24mA, and thus noise caused by the simultaneous switching of output buffers is also significantly large.

When a number of output buffers simultaneously switch, add power supplies referring to Tables 10-1 through 10-4 to prevent noise-induced errors.

Table 10-1 VSS Power Supply Addition for Output Buffer Simultaneous Switching (VDD = 3.3 V)

Number of power supply to add Output drivability (IOL)

Simultaneous switching

count CL ≤ 50pF CL ≤ 100pF CL ≤ 200pF

≤ 8 0 1 2

≤ 16 1 2 3

≤ 24 1 2 4 6mA

≤ 32 2 3 5

≤ 8 1 2 2

≤ 16 2 2 3

≤ 24 2 3 5 12mA

≤ 32 2 4 8

≤ 8 1 2 3

≤ 16 2 3 4

≤ 24 3 4 5 PCI

≤ 32 4 5 10

Table 10-2 VSS Power Supply Addition for Output Buffer Simultaneous Switching (VDD = 2.0 V)




≤ 8 0 1 2

≤ 16 1 2 3

≤ 24 1 2 4 4mA

≤ 32 2 3 5



Table 10-3 VDD Power Supply Addition for Output Buffer Simultaneous Switching (VDD = 3.3 V)




≤ 8 0 1 1

≤ 16 1 1 2

≤ 24 1 2 3 6mA

≤ 32 1 2 3

≤ 8 1 2 2

≤ 16 2 2 3

≤ 24 2 3 3 12mA & PCI

≤ 32 3 3 6

Table 10-4 VDD Power Supply Addition for Output Buffer Simultaneous Switching (VDD = 2.0 V)




≤ 8 0 1 1

≤ 16 1 1 2

≤ 24 1 2 3 4mA

≤ 32 1 2 3



10.3 Notes on Pinout After selecting the right device to suit a particular design, determine the package pinout. Refer to the “Pinout Table” form for the power supply pin information and usable I/O pin count of each package for the S1L50000 series.

Once the pinout is decided, send the “pinout table” in the given form to Epson. Then Epson proceeds with the placement and routing process according to the customer’s pinout table. Please check the table carefully before sending it to us. For the “Pinout Table” form, contact our sales representative.

The pinout table of LSI is one of the important specifications that determines the device quality. It is especially important to avoid noise-induced errors, which are difficult to detect by simulation.

The following describes the points for which the designer should take adequate care to avoid erroneous operations caused by unknown reasons. Fully consider these points when creating a pinout table.

10.3.1 Power Supply Pins in Fixed Locations

Depending on package combinations, some pins are only usable as power supply pins. Also, some packages have the VDD pins in the fixed locations, while others have the VSS pins fixed. Check the fixed power supply pins with the “Pinout Table” form when selecting a package.

10.3.2 Notes on Pinout

The pinout sometimes affects the LSI logic functions and electrical characteristics. Also there may be constraints on pinout because of the LSI packaging and the cell or master configurations. The following discusses the points for which adequate caution should be practiced when determining the pinout, such as power supply current, input and output pin layout, critical signals, pull-up and pull-down resistor inputs, simultaneous output switching, and high-current drivers.

(1) Power supply current (IDD, ISS)

Power supply current (IDD, ISS) defines the supply current allowable to the power supply pins when the device is active If the current exceeding this allowable value flows, the current density in the power lines within the LSI becomes too high, and this may lower the LSI reliability and even destroys the device. Also, the LSI internal voltage either increases or decreases depending on the voltage generated by the current and wire resistance. This voltage change induces functional errors and inversely affects the DC or AC characteristics.

To prevent these problems, the current density and power line impedance need to be lowered. To achieve this, estimate the power consumption in the design phase, and ensure enough power supply pins to prevent excessive current from flowing through each power supply pin. For power supply pins, refer to Section 10.1, “Calculating Power Supply Pin Count.” These power supply pins should not be placed close to each other, but should be scattered.

The total power supply pin count should include the power supply pins discussed above and additional power supply pins to reduce noise. For additional power supply pin count, see Section 10.2, “Simultaneous Switching and Power Supply Addition.”

(2) Noise caused by output cell operation

There are two types of noise that occur due to the output cell operation. To reduce this noise, one possible solution is to have as many power supplies as possible.

a. Noise generated in power supply lines

Noise generated in power supply lines becomes an issue when a large number of output pins simultaneously switch; and it changes the LSI input threshold level, which will end up



with malfunctions. The noise in power supply lines occurs when large current flows through the power supply lines by the simultaneous switching of output cells.

Inductance element affects power supply noise. The LSI equivalent circuit is illustrated in Figure 10-1. In this circuit, when the output changes from high to low, the current flows into the LSI from the output pin through the equivalent inductance L2, which is due to the LSI package, etc. When this happens, the equivalent inductance L2 changes the voltage of internal VSS power line. The voltage change in this VSS power line is the noise that occurs to the power line. This noise is generated mainly by the equivalent inductance L2, and thus the quicker the power supply current changes, the larger noise occurs.

VDD

Input pin

VDD (internal)

Output pin

VSS (internal) V1

L1

L2

L3

Figure 10-1 LSI Equivalent Circuit

b. Overshoot, undershoot, and ringing

Noise such as overshoot, undershoot and ringing, occurs due to the equivalent inductance of output pins. The L3 shown in Figure 10-1 is this equivalent inductance. Since inductance has the property to save energy, whether the output goes low or high, the saved energy makes the overshoot or undershoot proportional to the amount of flowing electric current and the rate of current change.

The most effective way to reduce overshoot or undershoot is use of output cells with small drivability. As the load capacitance increases, overshoot or undershoot noise tends to become smaller. Therefore, care must be taken when using cells with high drivability.

(3) Separating input and output pins

Separating the group of input pins from that of output pins is an important pinout technique to reduce noise effect.

Input pins and bi-directional pins in the input state are vulnerable to noise, and thus they should not be placed close to output pin. Separate the groups of input pins, output pins and bi-directional pins each other by power supply pins (VDD, VSS). (Figure 10-2)



VSS

VDD

VDD

VSS VDD

VDD

VSS

VSS

VDD

VDD

VS

S

VSS

Output pins

Inpu

t pin

s

Bid pins

Out

put p

ins

Figure 10-2 Example of separating input and output pins

(4) Critical signals

Pay attention to the following points for critical signals such as clock input and high-speed output pins.

a) Do not place clock and reset pins, that are vulnerable to noise, close to the output pins, but place them close to the power supply pins. (Figure 10-3)

b) Place the oscillation circuit input and output pins (OSCIN, OSCOUNT) close to each other and enclose them by the power supply pins (VDD and VSS). Also, do not place the output pins synchronous to the oscillation circuit close to the output pins. (Figure 10-4)

c) Place the high-speed input and output pins in the middle of the chip (package) side. (Figure 10-3)

d) When the delay from an input pin to an output pin is hard to meet the customer’s specification, place these input and output pins close to each other. (Figure 10-3)

VSS

CLK

Through output

High speed output

VSS

R

ST

Through input High speed input

Figure 10-3 Critical Signal Pinout Example 1



VDD

VSS

OSCIN

VSS

OSCOUT

Figure 10-4 Critical Signal Pinout Example 2

(5) Pull-up/Pull-down resistance input

Pull-up/pull-down resistance is relatively large, from some tens of K to some hundreds of KΩ, and dependent on the power supply voltage due to the resistor structure. When using these pins open for testing purpose, they easily get affected by noise and induce errors, so pay attention to the following points:

a) Place pull-up/pull-down resistor pins as far away form high-speed input pins (clock input pins, etc.) as possible. (Figure 10-5)

b) Place pull-up/pull-down resistor pins away form the output pins (especially from the high-current output pins). (Figure 10-6) Consider the following points as well:

• Perform pull up or pull down process on the printed circuit board wherever possible.

• Select pins with the smallest possible resistance.

CLK Pull Up

Figure 10-5 Pull-up and pull-down pinout example 1

Pull Down High drive output

Figure 10-6 Pull-up and pull-down pinout example 2



(6) Simultaneous output switching

Noise caused by simultaneous switching of output pins induces LSI malfunctions. When switching many output pins simultaneously, add power supply pins to the group of output pins to avoid errors by noise. As for the number of required power supply pins and how to place additional power pins, refer to Section 10.2, “Simultaneous Switching and Power Supply Addition.” (Figure 10-7)

Simultaneous signal switching can be reduced by inserting a delay cell at the input of the output cells in one group. This reduces noise as well. (Figure 10-8)

Output pins that simultaneously switch

VSS

V

DD

VSS

VSS

V

DD

VSS

VSS

VDD

Figure 10-7 Example of Adding Power Supply Pins

OUT1

A

TA

TS

OUT2

DL1 A

TA

TS

Figure 10-8 Example of Adding a Delay Cell

(7) High-current Drivers

For the pinout including the output of high-current driver (IOL = 12mA, 24mA, PCI), meet the following constraints:

a) Constraint on power supply enhancement

Since high-current drivers have high drivability, the noise that would occur when output buffers are active is also large, sometimes causing malfunctions to LSI.

When using high-current drivers, place the power supply pins close to the driver pins to secure power supply. (Figure 10-9)

VSS

High drive output

VSS

VDD

VDD

Figure 10-9 Example of Power Supply Enhancement



b) Low-noise pre-drivers

To reduce the noise generated by the active output buffers of high-current drivers, low noise output buffers and bi-directional buffers are available. For more information, see Chapter 4, “Types of I/O Buffers and Notes on Use.”

(8) Other notes:

a) NC pins (non-connection)

Do not connect anything to the NC pin.

b) TAB pins

TAB pins are no longer used.

10.3.3 Recommended Pinout

The pinout is important to have LSI devices function correctly. The following is a pinout example that meets the constraints discussed above (Figure 10-10). Determine the pinout referring to the following example.

Input pins

PLU

P

VDD

IN

P 9

VSS

VDD

IN

P10

IN

P11

IN

P12

INP

13

INP

14

CLK

INP

15

INP

16

INP

17

INP

18

INP

19

VDD

BID

0 V

SS

VDD

BID

1 B

ID2

BID

3 B

ID4

HO

UT

OU

T0

OU

T1

MO

SC

VDD

V

SS

VSS

VSS

Bid pins Output pins

VSS INP 8

VSS

VSS

INP 7

INP 6 INP 5

OSCIN

INP 4 INP 3 INP 2 INP 1 INP 0

VSS

VDD OSCOUT

Inpu

t pin

s

SOUT0

VSS

SOUT1

VSS

VSS

SOUT2

SOUT3 SOUT4

SOUT5 SOUT6

SOUT7 SOUT8 SOUT9

VSS

VDD

VSS

Out

put p

ins

Figure 10-10 Recommended Pinout Example

The input pins are placed at the upper and left sides of the package, the output pins that simultaneously switch are placed at the right side, and bi-directional and other output pins are placed at the lower side of the package.



Table 10-5 Description of Pinout Example

Place Pin Name Pin Description Pinout Description

PLUP Pull-up input pin Place in the location where noise effect is small Upper Side CLK Clock iput pin Place in the middle of the package side, and close to

the power supply pin

OSCIN Oscillator pin Place in the middle of the package side, and close to the power supply pin

OSCOUT Place in the middle of the package side, and close to the power supply pin

Left Side

INP0 to 19 Input pins Separate from other pins by the power supply pin

Right Side SOUT to 9 Simultaneous switching

output pins Separate from other pins by the power supply pin, and add power supply pins

BID0 to 4 Bi-directional pins Seprate from other pins by the power supply pin

MOSC Oscillation monitor output pin

Place away from the oscillator pin, and close to the power supply pin

HOUT High-drivability output pin Place close to the power supply pin

Lower Side

OUT01 Output pin Separate from other pins by the power supply pin

VDD VDD power supply pin All Sides VSS VSS (GND) power supply pin

Appendix A1 Input/Output Buffer Characteristic Graphs



A1.1 5.0-V operation Output current characteristics (5.0 V ±0.5 V)

Table A1-1

Output current

Type No. IOH (mA) IOL (mA)

TYPE S -0.1 0.1

TYPE M -1 1

TYPE 1 -3 3

TYPE 2 -8 8

TYPE 3 -12 12

TYPE 4 -12 24

PCI Conformed to the PCI Standard

“S,” “M,” and “1” through “4” following “TYPE” are the numbers indicated in the “XX*X” section of the names of output cells. Example: HOB3T indicates TYPE 3.

Input buffer characteristics (5.0 V ±0.5 V)

• Standard cell input buffer

Figure A1-1 Input characteristic (TTL level) Figure A1-2 Input characteristic (CMOS level)

Figure A1-3 Input characteristic (5-V PCI level)



• Schmitt trigger cell input buffer

Figure A1-4 Input characteristic (TTL level) Figure A1-5 Input characteristic (CMOS level)



Output driver characteristics

• Low-level output current

Figure A1-6 Figure A1-7





1 to 4


• High-level output current

Output voltage VOH - power supply voltage VDD (V)

-0.5



Output voltage VOH - power supply voltage VDD (V) Output voltage VOH - power supply voltage VDD (V)





Figure A1-18


1 to 4


Figure A1-21 Ambient temperature (Ta) vs. output current (IOL)

Figure A1-22 Ambient temperature (Ta) vs. output current (IOH)



Output delay time vs. output load capacitance (CL)

Figure A1-23 Output delay time (tPLH) vs. output load capacitance (CL)

Figure A1-24 Output delay time (tPHL) vs. output load capacitance (CL)







Output buffer rising/falling time vs. output load capacitance (CL)

Figure A1-29 Rising time (tr) vs. output load capacitance (CL)

Figure A1-30 Falling time (tf) vs. output load capacitance (CL)







Pull-up, pull-down resistance

• Pull-up characteristics

Figure A1-35 Pull-up resistance vs. VDD characteristics

Figure A1-36 Pull-up resistance vs. Ta characteristics

• Pull-down characteristics

Figure A1-37 Pull-down resistance vs. VDD characteristics

Figure A1-38 Pull-down resistance vs. Ta characteristics



Output waveforms

• High-speed type output buffer waveform (HOB3AT)

Output buffer condition: VDD = 5.0 V, Ta = 25°C, CL = 15 pF, and IOL = 12 mA

Out

put v

olta

ge V

o (V

)

Figure A1-39

• Normal type output buffer waveform (HOB3T)


Out

put v

olta

ge V

o (V

)

Figure A1-40

• Low-noise type output buffer waveform (HOB3BT)


Out

put v

olta

ge V

o (V

)

Figure A1-41




Table A1-2

Output current


TYPE S -0.1 0.1

TYPE M -1 1

TYPE 1 -2 2

TYPE 2 -6 6

TYPE 3 -12 12


“S,” “M,” and “1” through “4” following “TYPE” are the numbers indicated in the “XX*X” section of the names of output cells. Example: OB3T indicates TYPE 3.




• Standard cell buffer

Figure A1-42 Input characteristic (LVTTL level)

Figure A1-43 Input characteristic (3-V PCI level)


Figure A1-44 Input characteristic (LVTTL level)

Delay characteristics

Ta (°C)

Figure A1-45 Propagation time - power supply voltage characteristic

Figure A1-46 Propagation time - ambient temperature characteristic







Figure A1-51



1 to 3









Output voltage VOH - power supply voltage VDD (V) -0.5




1 to 3

-0.5


Output voltage VOL - power supply voltage VDD (V) Ta (°C)


Ta (°C)











Power consumption characteristics

Figure A1-80 Power consumption (IOP) vs. power supply voltage (VDD)

Figure A1-81 Power consumption (IOP) vs. operating frequency (kHz)



Output waveforms

• High-speed type output buffer waveform (OB3AT)


Out

put v

olta

ge V

o (V

)

Figure A1-82

• Normal type output buffer waveform (OB3T)


Out

put v

olta

ge V

o (V

)

Figure A1-83

• Low-noise type output buffer waveform (OB3BT)


Out

put v

olta

ge V

o (V

)

Figure A1-84




Table A1-3

Output current


TYPE S -0.05 0.05

TYPE M -0.3 0.3

TYPE 1 -0.6 0.6

TYPE 2 -2 2

TYPE 3 -4 4


“S,” “M,” and “1” through “4” following “TYPE” are the numbers indicated in the “XX*X” section of the names of output cells. Example: OB3T indicates TYPE 3.




• Standard cell input buffer

Figure A1-85 Input characteristic (CMOS level)


Figure A1-86 Input characteristic (CMOS level)

Delay characteristics

Figure A1-87 Propagation time - power supply voltage characteristic

Figure A1-88 Propagation time - ambient temperature characteristic







Figure A1-93



1 to 3

Figure A1-94









Figure A1-99


1 to 3

Figure A1-100

Figure A1-101 Ambient temperature (Ta) vs. output current (IOL)

Figure A1-102 Ambient temperature (Ta) vs. output current (IOH)










Power consumption characteristics

Figure A1-115 Power consumption (IOP) vs. power supply voltage (VDD)

Figure A1-116 Power consumption (IOP) vs. power supply voltage (kHz)



Output waveforms

• High-speed type output buffer waveform (OB3AT)


Out

put v

olta

ge V

o (V

)

Figure A1-117

• Normal type output buffer waveform (OB3T)


Out

put v

olta

ge V

o (V

)

Figure A1-118

• Low-noise type output buffer waveform (OB3BT)


Out

put v

olta

ge V

o (V

)

Figure A1-119

International Sales Operations

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Document Code: 410729300 First Issue February, 2004

Printed June 2006 in JAPAN C

Printed December, 2007 in JapanThis manual is printed on recycled paper using soy-based inks.

http://www.epson.jp/device/semicon_e/

GATE ARRAY S1L50000 SERIES DESIGN GUIDE - Epson · 6.7.3 Gate Count Estimation ... CMOS process...

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