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GaN HEMT Characterization and Mode ling using ASM-HEMT
Ahtisham Pampori and Yogesh S. ChauhanNanolab, Department of Electrical Engineering
IIT Kanpur, IndiaEmail: [email protected]
Homepage – http://home.iitk.ac.in/~chauhan/
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 2
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 3
Nanolab:Characte rization and Mode ling
Capabilitie s− About Nanolab
− Hardware Capabilities− EDA Capabilities
About Nanolab: Some Stats
− Postdoc – 5− Ph.D. – 27 − Te n PhDs graduate d
Curre nt Me m b e rs2020 2019 2018 2017 2016 2015
Books 1 1
Journal 16 14 20 19 18 9
Conference 9 15 19 11 30 30
Publications
− Gove rnm e nt Age ncie s− Industry Partne rs− Com pact Mode l Coalition (CMC)
Fund ing
Nanolab , Ind ian Ins titute of Te chnology Kanpur 5
About Nanolab: Collaborations
Nanolab , Ind ian Ins titute of Te chnology Kanpur 6
About Nanolab: Areas of Research
Nanolab , Ind ian Ins titute of Te chnology Kanpur 7
Hardware Capabilities I
Ke ysig h t Se m ic ond u c t or De vic e Ana lyze r (B1500A) Me a su re m e nt c a p a b ilit ie s :
− IV, CV, pulse / d ynam ic IV range of 0 .1 fA - 1 A / 0 .5 µV - 200 V− Evaluation of de vice s, m ate ria ls , se m iconductors ,
ac tive / passive com pone nts− AC capacitance m e asure m e nt in m ulti fre que ncy from 1 kHz to
5 MHz− Pulse d IV m e asure m e nt m in 10 ns gate pulse wid th with 2 ns
rise and fall tim e s with 1 µs curre nt m e asure m e nt re solution
Ma u ry Mic row a ve s / AMCAD AM3221
− Bipolar ±25V/ 1A (gate ) and high-voltage 250V/ 30A (d rain) m ode ls
− Pulse wid ths down to 200ns− Synchronize d pulse d S-param e te r m e asure m e nts− Conne ct syste m s in se rie s for synchronizing 3+ pulse d
channe ls− Long pulse s into the te ns and hundre ds of se conds for
trapp ing and the rm al characte rization
Nanolab , Ind ian Ins titute of Te chnology Kanpur 8
Hardware Capabilities II
Ke ysig h t PNA-X (N5244A) 10 MHz t o 43.5 GHz
− High Fre que ncy De vice Characte rization (Microwave Ne twork Analyze r)
− 100Khz to 8.5 GHz and 10 MHz to 43.5 GHz− 2-port and 4-ports with two built-in source s− High output powe r (+16 dBm )− Be st dynam ic accuracy: 0 .1 dB com pre ssion with +15 dBm
input powe r a t the re ce ive r− Low noise floor of -111 dBm at 10 Hz IF bandwid th
Ke ys ig h t ENA (E5071C) 100KHz t o 8 .5 GHz
− 9 kHz to 4.5/ 6 .5/ 8.5/ 14/ 20 GHz− 2- or 4-port, 50-ohm , S-param e te r te st se t− Im prove accuracy, yie ld and m arg ins with wide dynam ic range
130 dB, fast m e asure m e nt spe e d 8m s and e xce lle nt te m pe rature s tab ility 0 .005 dB/ °C
Nanolab , Ind ian Ins titute of Te chnology Kanpur 9
Hardware Capabilities III
Ke ysig h t Pow e r De vic e Cha ra c t e riza t ion Sys t e m : B1505
− Powe r de vice characte rization up to 1500 A & 10 kV− Me dium curre nt m e asure m e nt with high voltage b ias (e .g . 500 m A at 1200 V)− μΩ on-re sistance m e asure m e nt capab ility− Accurate , sub-p icoam p le ve l, curre nt m e asure m e nt a t high voltage b ias− Fully autom ate d Capacitance m e asure m e nt a t up to 3000 V of DC b ias− High powe r pulse d m e asure m e nts down to 10 μs− High voltage / high curre nt fast switch op tion to characte rize GaN curre nt collapse e ffe c t− Fully autom ate d the rm al te sting from -50 ℃ to +250 ℃
Ke ysig h t N8975B Noise Fig u re Ana lyze r
− Fre que ncy range 10 MHz to 26.5 GHz in a one -box solution− Include s Spe ctrum Analyze r and IQ Analyze r (Basic) m ode s− SNS se rie s noise source N4002A− U7227C 100 MHz to 26.5 GHz Exte rnal USB Pre am plifie r inc lude d
Nanolab , Ind ian Ins titute of Te chnology Kanpur 10
Load Pull Characterization
Ma u ry Loa d Pu ll Cha ra c t e riza t ion sys t e m
− A fundam e ntal passive load pull syste m capab le of pe rform ing load pull characte rization up to 15W.
− XT982GL01 – 0 .6 to 18 GHz Load tune r
− Plan to e xpand to a 3 harm onic hybrid load pull syste m soon.
Nanolab , Ind ian Ins titute of Te chnology Kanpur 11
Atomistic Simulations
EDA CapabilitiesSP
ICE
SIM
ULA
TOR
SR
F
TCAD
Nanolab , Ind ian Ins titute of Te chnology Kanpur 12
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 13
An introduction to ASM -HEMT− About ASM-HEMT and its core
− Extraction flow− Other models incorporated into the core
− Geometric Scaling
A brief history of HEMT models
Nanolab , Ind ian Ins titute of Te chnology Kanpur 15
Various classes of compact models
Advanced SPICE Model for GaN HEMTs (ASM-HEMT)
Compact Models (GaN HEMT)
Table Based
Empirical
Physics Based
Threshold Voltage Based
Surface Potential Based(ASM-HEMT)
Charge Based(MVSG)
Nanolab , Ind ian Ins titute of Te chnology Kanpur 16
www.iitk.ac .in/ asm
ASM-HEMT Te am
Nanolab , Ind ian Ins titute of Te chnology Kanpur 17
Dire
ctor
s
Prof. Yogesh Singh Chauhan
Dev
elop
ers
Dr. Sudip Ghosh Dr. Aamir Ahsan Dr. Avirup Dasgupta
Raghvendra DangiAhtisham Pampori
Prof. Sourabh Khandelwal
ASM-HEMT: Sum m ary
Analytical Solution of Schrod ige r’s & Poisson’s
SP-Base d Curre nt & Charge Mode l
Noise , Trapping , Se lf-He ating , Fie ld Plate
2-DEG Charge , Ef,Surface Pote ntial
I-V, C-V, DIBL, Rd , Rs, Ve l. Sat., ...
DC, AC, Transie ntHarm onic Sim .,
Noise , ...
Electrostatics
Transport
Higher-order Effects
Nanolab , Ind ian Ins titute of Te chnology Kanpur 18
ASM-HEMT: Core Mode l
Real Device Effects Incorporated into the Model
Core Model Parameters
Parameter Description Extracted Value𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 Cutoff Voltage −2.86 𝑉𝑉
𝑁𝑁𝑂𝑂𝐹𝐹𝐹𝐹𝐹𝐹𝑂𝑂𝐹𝐹 Subthreshold Slope Factor 0.202
𝐶𝐶𝐷𝐷𝐷𝐷𝐹𝐹𝐷𝐷 SS Degradation Factor 0.325 𝑉𝑉−1
𝜂𝜂0 DIBL Parameter 0.117
𝑈𝑈0 Low Field Mobility 33.29 𝑚𝑚𝑚𝑚2/𝑉𝑉𝑉𝑉
𝑁𝑁𝐷𝐷0𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷 AR 2DEG Density 1.9𝑒𝑒 + 17 /𝑚𝑚2
𝑉𝑉𝐷𝐷𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷 AR saturation velocity 157.6𝑒𝑒 + 3 𝑐𝑐𝑚𝑚/𝑉𝑉
𝑅𝑅𝐹𝐹𝑇𝑇0 Thermal Resistance 22 Ω
Core d rain curre nt e xpre ssion
Nanolab , Ind ian Ins titute of Te chnology Kanpur 19
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017]
Extraction Flow I
Set L, W, NF, TbarDevice Dimensions
Extract VOFF, NF, CDSCD,ETA from log -IDVG, LINEAR
And Saturation
Extract U0, UA, UB and RDS from IDVG-LIN
Extract VSAT, Improve ETA
From LINEAR IDVG
Extract LAMBDA, ImproveVSAT, ETA from IDVD
Temperature Parameters
Capacitance Modeling
Nanolab , Ind ian Ins titute of Te chnology Kanpur 20
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017]
Extraction Flow II
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 (Extract 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 , 𝑁𝑁𝑂𝑂𝐹𝐹𝐹𝐹𝐹𝐹𝑂𝑂𝐹𝐹,𝐶𝐶𝐷𝐷𝐷𝐷𝐹𝐹𝐷𝐷) 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 (Extract 𝑈𝑈0) 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑁𝑁𝐷𝐷0𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷)
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑉𝑉𝐷𝐷𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷)
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑅𝑅𝐹𝐹𝑇𝑇0)
[1] S. A. Ahsan et al., MOS-AK Workshop, Shanghai, [2016]Nanolab , Ind ian Ins titute of Te chnology Kanpur 21
Extraction from Id -Vg curve s
Nanolab , Ind ian Ins titute of Te chnology Kanpur 22
Start with 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 characte ris tics in the log scale
𝑬𝑬𝑬𝑬𝑬𝑬𝑬𝑬 – DIBL Param e te r
𝑵𝑵𝑵𝑵𝑬𝑬𝑵𝑵𝑬𝑬𝑵𝑵𝑵𝑵 – Sub-thre shold slope param e te r
𝑵𝑵𝑪𝑪𝑪𝑪𝑵𝑵𝑪𝑪 – Cap ture s the d rain voltage de pe nde nce on the sub-thre shold slope .
𝑽𝑽𝑵𝑵𝑵𝑵𝑵𝑵 – Cut-Off Voltage
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 characte ris tics in the line ar scale
𝑼𝑼𝑬𝑬 – Low fie ld m obility
𝑼𝑼𝑬𝑬,𝑼𝑼𝑼𝑼 – Mobility de gradation param e te rs
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017]
Extraction from Id -Vd curve s
Nanolab , Ind ian Ins titute of Te chnology Kanpur 23
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 characteristics
𝑽𝑽𝑪𝑪𝑬𝑬𝑬𝑬 – Velocity saturation parameter
𝑼𝑼𝑬𝑬, 𝑼𝑼𝑼𝑼 – Mobility degradation parameters
Access Region Parameters extracted from 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 characteristics:
𝑵𝑵𝑪𝑪𝑬𝑬𝑬𝑬𝑵𝑵𝑵𝑵𝑪𝑪(𝑪𝑪) – 2DEG density in the access region.
𝑽𝑽𝑪𝑪𝑬𝑬𝑬𝑬𝑬𝑬𝑵𝑵𝑵𝑵𝑪𝑪 – Saturation velocity in the access region.
𝑼𝑼𝑬𝑬𝑬𝑬𝑵𝑵𝑵𝑵𝑪𝑪(𝑪𝑪) – Low field mobility in the access region.
𝑼𝑼𝑬𝑬𝑬𝑬𝑵𝑵𝑵𝑵𝑪𝑪(𝑪𝑪) independently tunes the access region resistance around Vds = 0 and helps extract 𝑔𝑔𝑑𝑑𝑑𝑑 at that point.
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]
Bias-de pe nde nt acce ss re g ion re sistance m ode l: Ove rvie w
Nonlinear variation of source/ drain access resistances with Ids extracted from TCAD simulation and comparison with model.
Nanolab , Ind ian Ins titute of Te chnology Kanpur 24
[1] S. Ghosh e t al., IEEE Inte rnational Confe re nce on Ele ctron De vice s and Solid -State Circuits (EDSSC), [2016]
Bias-de pe nde nt acce ss re g ion re sistance m ode l: Re sults
Id - Vg and trans -conductance for the Toshiba power HEMT. Different slopes above Voff in
gm -Vg: self-heating governs the first slope while velocity
saturation in access region affects second slope.
Ids-Vds and reverse Ids -Vds fitting with experimental data. The non -linear Rs/d model shows correct behavior for the higher Vg curves in the Id -
Vd plot; the S -P based model can accurately capture the reverse output characteristics.
Effect of high access region resistance at high V g
Nanolab , Ind ian Ins titute of Te chnology Kanpur 25
[1] S. Ghosh e t al., IEEE Inte rnational Confe re nce on Ele ctron De vice s and Solid -State Circuits (EDSSC), [2016]
Bias-de pe nde nt acce ss re g ion re sistance m ode l: Te m pe rature scaling
The temperature dependence of R d/s model is extremely important as it increases significantly with increasing temperature
Temperature dependence of 2 -DEG charge density in the drain or source side access region:
Temperature dependence of Saturation Velocity:
Temperature dependence of electron Mobility:
Nanolab , Ind ian Ins titute of Te chnology Kanpur 26
[1] S. Ghosh e t al., IEEE Inte rnational Confe re nce on Ele ctron De vice s and Solid -State Circuits (EDSSC), [2016]
ASM-HEMT: Te m pe rature scaling re sults
Nanolab , Ind ian Ins titute of Te chnology Kanpur 27
Id - Vg at 100℃
Id - Vg at -20℃
Id - Vd at 100℃
Id - Vd at -20℃
ASM-HEMT fe ature s a robust te m pe rature scaling m ode l which has be e n validate d
across a b road range of de vice te m pe rature s .
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑇𝑇
= 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 −𝑇𝑇𝑑𝑑𝑑𝑑𝑑𝑑𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁
− 1 � 𝑲𝑲𝑬𝑬𝑲𝑲 + 𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑉𝑉𝑇𝑇𝑇𝑇𝑇𝑇
⋅ 𝑣𝑣𝑐𝑐𝑣𝑣𝑣𝑣 + 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
𝑈𝑈𝑈 𝑇𝑇 = 𝑈𝑈𝑈 ⋅𝑇𝑇𝑑𝑑𝑑𝑑𝑑𝑑𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁
𝑼𝑼𝑬𝑬𝑬𝑬
𝑉𝑉𝑉𝑉𝑇𝑇𝑇𝑇 𝑇𝑇 = 𝑉𝑉𝑉𝑉𝑇𝑇𝑇𝑇 ⋅𝑇𝑇𝑑𝑑𝑑𝑑𝑑𝑑𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁
𝑬𝑬𝑬𝑬
[1] S. Ghosh e t al., IEEE Inte rnational Confe re nce on Ele ctron De vice s and Solid -State Circuits (EDSSC), [2016]
Geometric Scaling I
Nanolab , Ind ian Ins titute of Te chnology Kanpur 28
Charge Scaling Current Scaling
Access Region Resistance Scaling
Geometric Scaling II
Nanolab , Ind ian Ins titute of Te chnology Kanpur 29
Thermal Noise and Flicker Noise Scaling
Gate Current Scaling
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 30
Modeling Power Devices using ASM -HEMT
− Modeling DC− Modeling field plates
− Model comparison with a mixed mode device
Modeling DC: Room Temperature Output Characteristics
Nanolab , Ind ian Ins titute of Te chnology Kanpur 32
Output Characteristics at T=25 ℃
Output conductance ve rsus Vd
De rivative of output conductance ve rsus Vd
ASM-HEMT accurately captures the IV
characteristics of a power GaN HEMT
device.
Modeling DC: Room Temperature Reverse Output Characteristics
Nanolab , Ind ian Ins titute of Te chnology Kanpur 33
Reverse Output Characteristics at T=25℃
Re ve rse Output conductance ve rsus Vd
De rivative of re ve rse output conductance ve rsus Vd
Modeling DC: Room Temperature Transfer Characteristics
Nanolab , Ind ian Ins titute of Te chnology Kanpur 34
Vd @ 0.1, 0.5, 1 and 10V
Vg (V) [E+0]
-6 -4 -2 0 2 40.0
0.2
0.4
0.6
0.8
1.0
Id (A
)
Vd @ 0.1, 0.5, 1 and 10V
Vg (V) [E+0]
-6 -4 -2 0 2 40
50
100
150
200
g m(m
A/V)
vg [E+0]
gm
' (m
/s) [
E-3]
/
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.00
50
100
150
200
Transfer Characteristics at T=25℃
Transconductance ve rsus Vg
De rivative of transconductance ve rsus Vg
Modeling DC: Room Temperature IV – Log Scale
Nanolab , Ind ian Ins titute of Te chnology Kanpur 35
Log (Id) - Vds (Vd>0) T=25℃
Log (Id ) - Vds (Vd<0) T=25℃
Id (A
)
Log (Id ) - Vgs T=25℃
Modeling DC: Output Characteristics @ T=-20℃
Nanolab , Ind ian Ins titute of Te chnology Kanpur 36
Id (A
)
The model scales accurately to sub-zero temperatures.
Output conductance ve rsus Vd @ -20℃
De rivative of output conductance ve rsus Vd @ -20℃
Output Characte ris tics
@ -20℃
Log Output Characte ris tics
@ -20℃
Modeling DC: Reverse Output Characteristics @ T=-20℃
Nanolab , Ind ian Ins titute of Te chnology Kanpur 37
Vg from -12 to 3 V @ 0.5V step
Reverse Output conductance versus Vd @ -20℃
Derivative of reverse output conductance versus Vd @ -20℃
Reverse Output Characteristics
@ -20℃
Log Output Characteristics
@ -20℃
The model scales accurately to sub-zero temperatures.
Modeling DC: Transfer Characteristics @ T=-20℃
Nanolab , Ind ian Ins titute of Te chnology Kanpur 38
Id (m
A)
Id (A
)
Transfer Characteristics @ T=-20℃
Transconductance @ T=-20℃
Derivative of Transconductance @ T= -20℃
Transfer Characteristics (Log) @ T=-20℃
The model scales accurately to sub-zero temperatures.
Modeling DC: IV Characteristics @ T=100℃
Nanolab , Ind ian Ins titute of Te chnology Kanpur 39
Id (m
A)
Id (m
A)
Id (m
A)
Output Characteristics @ T=100℃
Transfer Characteristics @ T=100℃
Transfer Characteristics (Log) @ T=100℃
The model can accurately capture high temperature operation of the device.
This is particularly important for power devices which generate a lot of heat.
Modeling DC: Reverse Output Characteristics @ T=150℃
Nanolab , Ind ian Ins titute of Te chnology Kanpur 40
Vg from -12 to 3 V @ 0.5V step
The model can accurately capture high temperature operation of the device.
This is particularly important for power devices which generate a lot of heat.
Re ve rse Output conductance ve rsus Vd @ 150℃
De rivative of re ve rse output conductance ve rsus Vd @ 150℃
Re ve rse Output Characte ris tics @
150℃
Log Output Characte ris tics @
150℃
Modeling field plates: Structure
A Gate Field Plate (GFP) and a Source Field Plate (SFP) structure modeled as transistors in series.
Field plates flatten out the peak in the electric field caused by the sudden drop in potential at the gate edge. TCAD showing field fluctuations leading to
a distributed field inside the device.
Nanolab , Ind ian Ins titute of Te chnology Kanpur 41
[1] S. A. Ahsan e t al., IEEE Transactions on Ele ctron De vice s (Spe cial Issue ), [2017]
Modeling field plates: Trends w.r.t Drain Voltage
Nanolab , Ind ian Ins titute of Te chnology Kanpur 42
Terminal Capacitance: Reverse (Crss)
Activation of different series transistors with increasing drain voltage at a fixed gate bias
Terminal Capacitance: Input side ( Ciss)
Terminal Capacitance: Output side ( Coss)
The plateaus in each capacitance curve denote the switching -off of one of the transistors in series as depicted in the
previous slide.
[1] S. A. Ahsan e t al., IEEE Transactions on Ele ctron De vice s (Spe cial Issue ), [2017]
Field Plate Models: Trends w.r.t temperature
Nanolab , Ind ian Ins titute of Te chnology Kanpur 43
Terminal Capacitance: Input side ( Ciss) with drain voltage
Terminal Capacitance: Output side ( Coss)
Terminal Capacitance: Input side (Ciss) with gate voltage
Terminal Capacitance: Reverse (Crss)
Increasing temperature shifts the threshold voltage in the negative direction – leading to a corresponding shift in the capacitance curves.
[1] S. A. Ahsan e t al., IEEE Transactions on Ele ctron De vice s (Spe cial Issue ), [2017]
Mixed mode TCAD circuit using ATLAS
Nanolab , Ind ian Ins titute of Te chnology Kanpur 44
− Schematic for Mixed-mode simulation using the numerical GaN FP device generated in Atlas.
− The FP-HEMT is put as the DUT with 7 V and 0 V pulses of 1 MHz at gate.
− The pulse has a pulse-width of 480 ns 20 ns rise and fall times.
− Supply voltage of 50 V is chosen to capture the maximum effect of cross coupling capacitances on switching transients while an inductive load is put at the drain.
[1] S. A. Ahsan e t al., IEEE Transactions on Ele ctron De vice s (Spe cial Issue ), [2017]
Voltage waveforms
The model accurately predicts drain overshoots due to LC ringing, Miller
plateaus due to accurate prediction in sharing of the
gate drive current to charge Cgs and Cgd and the associated gate -drain
charge, and the damping of the oscillations.
Nanolab , Ind ian Ins titute of Te chnology Kanpur 45
Turn-on by switching applied gate signal from 7 V to 0 V (FP vs no FP)
Turn-on by switching applied gate signal from 7 V to 0 V (Mixed -mode vs Model)
Turn-off by switching applied gate signal from 0 V to 7 V, keeping applied drain voltage fixed at 50 V (FP vs No FP)
Turn-off by switching applied gate signal from 0 V to 7 V, keeping applied drain voltage fixed at 50 V (Mixed -mode
vs Model)[1] S. A. Ahsan et al., IEEE Transactions on Electron Devices (Special Issue), [2017]
Current Waveforms
Comparison of modeled time -domain waveforms during turn -off with and without cross -coupling and substrate capacitances.
Solid lines = Cross-Coupling(CC) and substrate model includedDotted lines = CC and substrate model excluded.
Nanolab , Ind ian Ins titute of Te chnology Kanpur 46
Turn-on by switching app lie d gate s ignal from 7 V to 0 V (Mixe d-m ode vs Mode l)
Turn-off by switching app lie d gate s ignal from 0 V to 7 V, ke e p ing app lie d d rain voltage fixe d at 50 V (Mixe d-m ode
vs Mode l)
[1] S. A. Ahsan e t al., IEEE Transactions on Ele ctron De vice s (Spe cial Issue ), [2017]
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 47
Modeling RF Devices using ASM -HEMT− Extracting DC Parameters
− RF Model Extraction− Large signal simulations
− Load Pull Simulations
Extracting DC Parameters
Nanolab , Ind ian Ins titute of Te chnology Kanpur 49
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 (Extract 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 , 𝑁𝑁𝑂𝑂𝐹𝐹𝐹𝐹𝐹𝐹𝑂𝑂𝐹𝐹,𝐶𝐶𝐷𝐷𝐷𝐷𝐹𝐹𝐷𝐷) 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑔𝑔 (Extract 𝑈𝑈0) 𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑁𝑁𝐷𝐷0𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷)
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑉𝑉𝐷𝐷𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐷𝐷)
𝐼𝐼𝑑𝑑 − 𝑉𝑉𝑑𝑑 (Extract 𝑅𝑅𝐹𝐹𝑇𝑇0)
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]
RF Model & Extraction I
𝐿𝐿𝑥𝑥𝑔𝑔𝑔𝑔
𝐿𝐿𝑥𝑥𝑥𝑥 𝑥𝑥
𝐿𝐿𝑥𝑥𝑉𝑉
𝑉𝑉
GMF
SMF
DMF
Extrinsic
Manifolds
Overlap
𝐶𝐶𝑔𝑔𝑑𝑑,𝑖𝑖𝐶𝐶𝐺𝐺𝐷𝐷𝑂𝑂
𝐶𝐶𝐺𝐺𝐷𝐷𝑂𝑂
𝐶𝐶𝑔𝑔𝑑𝑑,𝑖𝑖
𝑔𝑔𝑚𝑚
𝑅𝑅𝑔𝑔 𝑅𝑅𝑥𝑥
𝑅𝑅𝑉𝑉
𝑔𝑔𝑥𝑥𝑉𝑉
ASM-GaN-HEMT
𝑔𝑔𝑖𝑖𝑉𝑉𝑖𝑖
𝑥𝑥𝑖𝑖
𝐶𝐶𝐷𝐷𝐷𝐷𝑂𝑂𝐶𝐶𝑑𝑑𝑑𝑑,𝑖𝑖
𝑔𝑔𝑖𝑖
𝑉𝑉𝑖𝑖
𝑥𝑥𝑖𝑖
𝑥𝑥𝑑𝑑PDK
Mod e l− Core surface pote ntia l base d PDK− Acce ss re g ion re sis tance s inc lude d in core− Bus-inductance s in e xtrinsics
Pad -le ve l Sm all Signal Equivale nt Circuit Mode l
De vice Layout
Thre e s te p m e thod olog y− De -e m be d m anifolds − Extract the intrinsic core m ode l - Using low fre que ncy Y-param e te rs− Extract Inductance s - Using high fre que ncy Y-param e te rs
Nanolab , Ind ian Ins titute of Te chnology Kanpur 50
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017]
RF Model & Extraction II: Pad ParasiticsManifold s / Pad s
− Use d to p robe the de vice− Fe e d the s ignal to gate , d ra in & source bus-inductance s− Me asure m e nts ob ta ine d using TRL Calib ration− Transm ission line type m ode l− Re cip rocal (m ay/ m ay not be sym m e tric)− De -e m be dde d using “de e m be d” s2p com pone nts in ADS
Sym m e tric ne twork use d for GMF/ DMF Sing le port SMF ne twork
Y-param e te rs for DMF
Y-param e te rs for GMF
Y-param e te rs for SMF
Nanolab , Ind ian Ins titute of Te chnology Kanpur 51
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017]
RF Model & Extraction III: Bus Inductances Ke y Pointe rs
− The e ffe c t of bus-inductance s is ignore d at low fre que ncie s (assum ption)
− Drain & Source acce ss re g ion re sis tance s ignore d from hand analysis (not an assum ption, it is an advantage )
− Ignore som e te rm s at low fre que ncy (~ 10 GHz) (assum ption)
− Ve ry sim ple – only ne e d to ad just ove rlap capacitance s & gate finge r re sis tance s (advantage )
[1] I. Kwon e t al., IEEE Trans. Microw. The ory Te chn., 50 (6), [2002]
[1]
[1]
Nanolab , Ind ian Ins titute of Te chnology Kanpur 52
Fitting core model parameters using ADS
Extract 𝐶𝐶𝐺𝐺𝐷𝐷𝑂𝑂
Extract 𝐶𝐶𝐺𝐺𝐷𝐷𝑂𝑂
𝑔𝑔𝑚𝑚 d ispe rsion hand le d by trap m ode l
𝑔𝑔𝑑𝑑𝑑𝑑 d ispe rsion hand le d by trap m ode l
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017] Nanolab , Ind ian Ins titute of Te chnology Kanpur 53
Bus Inductance fitting
Resonant peaks due to interaction of inductances with intrinsic capacitances
𝑉𝑉11 & 𝑉𝑉22 (5V) 𝑉𝑉12 & 𝑉𝑉21 (5V)
𝑉𝑉11 & 𝑉𝑉22 (20V) 𝑉𝑉12 & 𝑉𝑉21 (20V)
[1] S. A. Ahsan e t al., IEEE J. Ele ctron De vice s Socie ty, Se p ., [2017] Nanolab , Ind ian Ins titute of Te chnology Kanpur 54
Large Signal HB Simulations
Harmonic balance drive -up characteristics showing Pout, PAE & Gain
Time domain waveforms of drain voltage & current. Load line contours spanning the IV plane
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017] Nanolab , Ind ian Ins titute of Te chnology Kanpur 55
Validation – Re al and Im aginary Loads
Nanolab , Ind ian Ins titute of Te chnology Kanpur 56
Pout & PAE against load resistance (real load)
Pout & PAE against load reactance (imaginary load)
Fairly accurate in predicting the maxima for Pout & PAE
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]
Load Pull simulations using ASM -HEMT
ADS Schematic for simulation of load -pull contours 22 dBm signal @ 10 GHz
Pout & PAE load pull contours for 10 mA/mm Pout & PAE load pull contours for 100 mA/mm
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017] Nanolab , Ind ian Ins titute of Te chnology Kanpur 57
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 58
Characterizing Self Heating and its Mode ling
− Self heating Model− Characterization
Self- He ating Mode l
Self-Heating Effect
Nanolab , Ind ian Ins titute of Te chnology Kanpur 60
− The se lf-he ating c ircuit is de fine d in a the rm al d isc ip line .
− For the the rm al d isc ip line , powe r is the e quivale nt of “curre nt” and te m pe rature is the e quivale nt of “voltage ”
𝑇𝑇 𝑅𝑅𝑡𝑡𝑡 =𝑇𝑇𝑒𝑒𝑚𝑚𝑣𝑣(𝑅𝑅𝑡𝑡𝑡)𝑅𝑅𝑇𝑇𝑅𝑅𝑈
𝑇𝑇 𝑅𝑅𝑡𝑡𝑡 =𝑥𝑥𝑥𝑥𝑑𝑑
𝑇𝑇𝑒𝑒𝑚𝑚𝑣𝑣(𝑅𝑅𝑡𝑡𝑡) � 𝐶𝐶𝑇𝑇𝑅𝑅𝑈
𝑈𝑈𝑈𝑈𝑥𝑥𝑒𝑒𝑈𝑈 𝑑𝑑𝑡𝑒𝑒𝑉𝑉𝑒𝑒 𝑐𝑐𝑣𝑣𝑈𝑈𝑥𝑥𝑐𝑐𝑑𝑑𝑐𝑐𝑣𝑣𝑈𝑈𝑉𝑉, 𝑣𝑣𝑣𝑣𝑣𝑣𝑎𝑎𝑎𝑎𝑐𝑐𝑈𝑈𝑔𝑔 𝐾𝐾𝐶𝐶𝐿𝐿𝑣𝑣𝑈𝑈 𝑑𝑑𝑡𝑒𝑒 𝑑𝑑𝑡𝑒𝑒𝑈𝑈𝑚𝑚𝑣𝑣𝑎𝑎 𝑉𝑉𝑠𝑠𝑠𝑠𝑐𝑐𝑐𝑐𝑈𝑈𝑐𝑐𝑠𝑠𝑐𝑐𝑑𝑑,𝑤𝑤𝑒𝑒 𝑡𝑣𝑣𝑣𝑣𝑒𝑒:
Characterization𝑇𝑇𝐽𝐽1 = 𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,1 + 𝑅𝑅𝑡𝑡𝑡 × 𝑇𝑇𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑1
𝑇𝑇𝐽𝐽2 = 𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,2 + 𝑅𝑅𝑡𝑡𝑡 × 𝑇𝑇𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑2
Ids
Vds
DC @ 𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,1
Pulsed (0,0) @ 𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,2
Extracting Rth. Both curves are measured at the same Vgs. The intersection point denotes a
common junction temperature.
⇒ 𝑅𝑅𝑡𝑡𝑡= ∆𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁/∆𝑇𝑇𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑
At the intersection point:𝑇𝑇𝐽𝐽1 = 𝑇𝑇𝐽𝐽2
And 𝑇𝑇𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑2 = 0 (Pulsed at (0,0))
Nanolab , Ind ian Ins titute of Te chnology Kanpur 61
With the ASM-HEMT m ode l, the param e te r RTH0 is tune d till the s im ulate d inte rse ction
point ove rlaps with the m e asure d inte rse ction point afte r the rm al param e te rs like UTE, AT and
KT1 have be e n e xtrac te d .
[1] T. Pe yre taillade e t al.,1997 IEEE MTT-S Inte rnational Microwave Sym posium Dige st, De nve r, CO, USA, 1997. doi: 10 .1109/ MWSYM.1997.596619.
𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,2 > 𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁,1
Contents
Nanolab – Characte rization and Mode ling Capabilitie s
An introduction to ASM-HEMT
Mode ling Powe r De vice s using ASM-HEMT
Mode ling RF De vice s using ASM-HEMT
Characte rizing Se lf He ating and its Mode ling
Trapping m ode ls in ASM-HEMT
Nanolab , Ind ian Ins titute of Te chnology Kanpur 62
Trapping models in ASM -HEMT− Trapping Models in ASM-HEMT
− Extraction using pulsed measurements
Trapping Models in ASM -HEMT: TRAPMOD I
Nanolab , Ind ian Ins titute of Te chnology Kanpur 64
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑇𝑇𝑈𝑈𝑣𝑣𝑣𝑣 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 + (𝑇𝑇𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑉𝑉𝑇𝑇𝑇𝑇𝑇𝑇 + 𝐵𝐵𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑉𝑉𝑇𝑇𝑇𝑇𝑇𝑇 � 𝑒𝑒− 1𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐)
𝑅𝑅𝐷𝐷 𝑇𝑇𝑈𝑈𝑣𝑣𝑣𝑣 = 𝑅𝑅𝐷𝐷 + (𝑇𝑇𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑅𝑅𝑉𝑉 + 𝐵𝐵𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑅𝑅𝑉𝑉 � 𝑒𝑒− 1𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐)
𝑅𝑅𝐷𝐷 𝑇𝑇𝑈𝑈𝑣𝑣𝑣𝑣 = 𝑅𝑅𝐷𝐷 + (𝑇𝑇𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑅𝑅𝐴𝐴 + 𝐵𝐵𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝑅𝑅𝐴𝐴 � 𝑒𝑒− 1𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐)
𝜂𝜂0 𝑇𝑇𝑈𝑈𝑣𝑣𝑣𝑣 = 𝜂𝜂0 + (𝑇𝑇𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝐴𝐴𝑇𝑇𝑇𝑇𝑈 + 𝐵𝐵𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇𝐴𝐴𝑇𝑇𝑇𝑇𝑈 � 𝑒𝑒− 1𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐)
𝐼𝐼𝐹𝐹𝐹𝐹𝐹𝐹𝑇𝑇 = 𝑣𝑣(𝑉𝑉𝑑𝑑)𝑉𝑉𝑐𝑐𝑡𝑡𝑡𝑡
Ke y h ig h lig h t s
− De pe nde nt on d rain voltage only− Bias-de pe nde nt and b ias-inde pe nde nt op tions− Scale s with s ignal powe r le ve ls− Suitab le for RF− Affe cts thre shold voltage , DIBL, AR Re sis tance .
Trapping Models in ASM -HEMT: TRAPMOD II
Nanolab , Ind ian Ins titute of Te chnology Kanpur 65
Ke y h ig h lig h t s
− De pe nde nt on both gate and d rain voltage s− Modulate s just the d rain s ide acce ss re g ion re sis tance− Suitab le for PIV sim ulation− Affe cts thre shold voltage , DIBL, Sub thre shold Slope ,
AR Re sis tance .
Trapping Models in ASM -HEMT: TRAPMOD III
Nanolab , Ind ian Ins titute of Te chnology Kanpur 66
𝑅𝑅𝐷𝐷 𝑇𝑇𝑈𝑈𝑣𝑣𝑣𝑣 = 𝑅𝑅𝐷𝐷 +𝑉𝑉(𝑑𝑑𝑈𝑈𝑣𝑣𝑣𝑣𝑡)𝑉𝑉𝑇𝑇𝑇𝑇𝑅𝑅𝑇𝑇𝑇𝑇
�𝑇𝑇𝑑𝑑𝑑𝑑𝑑𝑑𝑇𝑇𝑁𝑁𝑂𝑂𝑁𝑁
𝐹𝐹𝐹𝐹𝐷𝐷𝑇𝑇𝑇𝑇𝐹𝐹
Ke y h ig h lig h t s
− De pe nde nt on both gate and d rain voltage s− Modulate s just the d rain s ide acce ss re g ion re sis tance for
dynam ic Ron− Suitab le for s im ulating Powe r De vice s− Incorporate s te m pe rature de pe nde nce .
Extraction using pulsed measurements
Nanolab , Ind ian Ins titute of Te chnology Kanpur 67
− Pulse d IV charac te rization in dual-pulse m ode a t a pulse fre que ncy of 1000 Hz with a duty-cycle of 0 .02 % is pe rform e d unde r m ultip le quie sce nt d ra in and gate b ias cond itions such that both the gate and the d rain voltage s are pulse d s im ultane ously from the quie sce nt b ias point.
− The pulse wid th of 200 ns and the m e asure m e nt window of 40 ns within the se 200 ns is short e nough to e nsure iso-the rm al and iso-dynam ic m e asure m e nt of the pulse d -IV charac te ristics.
Pulse d -IV Sche m e use d to s im ulate the P-IV Characte ris tics
Pulse d – IV chacte ris tics for
m ultip le quie sce nt cond itions – using
TRAPMOD II
Related Publications
Publications
Nanolab , Ind ian Ins titute of Te chnology Kanpur 69
1 S. Khandelwal, Y. S. Chauhan, T. A. Fjeldly, S. Ghosh, A. Pampori, D. Mahajan, R. Dangi, and S. A. Ahsan, "ASM GaN: Industry Standard Model for GaN RF and Power Devices - Part-I: DC, CV, and RF Model", IEEE Transactions on Electron Devices, 2019.
2 S. A. Albahrani, D. Mahajan, J. Hodges, Y. S. Chauhan, and S. Khandelwal, "ASM GaN: Industry Model for GaN RF and Power Devices - Part-II: Modeling of Charge Trapping", IEEE Transactions on Electron Devices, 2019.
3 A. Pampori, S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Compact Modeling of MSM-2DEG GaN-based Varactors for THz Applications", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, Mar. 2018.
4 S. A. Ahsan, A. Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "A New Small-signal Parameter Extraction Technique for large gate-periphery GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 10, Oct. 2017.
5 S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Multi-bias RF Large-Signal GaN HEMT Modeling and Parameter Extraction Flow", IEEE Journal of the Electron Devices Society, Vol. 5, Issue 5, Sept. 2017.
6 S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Pole-Zero Approach to Analyze and Model the Kink in Gain-Frequency Plot of GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 3, Mar. 2017.
7 S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Cross-Coupling and Substrate Capacitance in GaN HEMTs for Power-Electronic Applications", IEEE Transactions on Electron Devices (Special Issue), Vol. 64, Issue 3, Mar. 2017.
8 S. Ghosh, S. A. Ahsan, S. Khandelwal, A. Pampori, R. Dangi, and Y. S. Chauhan, "Physics Based Analysis and Modeling of Capacitances in a Dual Field Plated Power GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, Dec. 2017.
9 S. A. Ahsan, S. Ghosh, S. Khandelwal, A. Pampori, R. Dangi, and Y. S. Chauhan, "A Scalable Physics-based RF Large Signal Model for Multi-Finger GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, Dec. 2017.
10 S. Khandelwal, S. Ghosh, S. A. Ahsan and Y. S. Chauhan, "Dependence of GaN HEMT AM/AM and AM/PM Non-Linearity on AlGaN Barrier Layer Thickness", IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, Malaysia, Nov. 2017.
Publications
Nanolab , Ind ian Ins titute of Te chnology Kanpur 70
11 S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Surface-potential-based Gate-periphery-scalable Small-signal Model for GaN HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), Miami, USA, Oct. 2017.
12 S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron Devices, Vol. 63, Issue 2, Feb. 2016.
13 S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
14 S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
15 S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Statistical Simulation for GaN HEMT Large Signal RF performance using a Physics-based Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
16 A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference (IMaRC), Delhi, India, Dec. 2016.
17 S. Ghosh, S. A. Ahsan, S. Khandelwal and Y. S. Chauhan, "Modeling of Source/Drain Access Resistances and their Temperature Dependence in GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
18 S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Modeling of Kink-Effect in RF Behaviour of GaN HEMTs using ASM-HEMT Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
19 R. Nune, A. Anurag, S. Anand and Y. S. Chauhan, "Comparative Analysis of Power Density in Si MOSFET and GaN HEMT based FlybackConverters", IEEE International Conference on Compatibility and Power Electronics, Bydgoszcz, Poland, June 2016.
20 S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb. 2015.
Publications
Nanolab , Ind ian Ins titute of Te chnology Kanpur 71
21 S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec. 2015.
22 S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
23 K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
24 S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
25 S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015..
26 A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
27 K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
28 C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, "Modeling of GaN based Normally-off FinFET", IEEE Electron Device Letters, Vol. 35, Issue 6, June 2014.
29 C. Yadav, P. Kushwaha, H. Agarwal, and Y. S. Chauhan, "Threshold Voltage Modeling of GaN Based Normally-Off Tri-gate Transistor", IEEE India Conference (INDICON), Pune, India, Dec. 2014.
30 S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct. 2013.
Publications
Nanolab , Ind ian Ins titute of Te chnology Kanpur 72
31 S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, and Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013.
32 S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct. 2012.
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