Future of NanoCMOS after Scaling Limit
Transcript of Future of NanoCMOS after Scaling Limit
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Future of NanoCMOS after Scaling Limit
October 28, 2008
Hiroshi Iwai, Tokyo Institute of Technology
@Shenyang University of Technology
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Founded in 1881, Promoted to Univ. 1929
Tokyo Institute of Technology東京工業大学
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Tokyo Institute of Technology東京工業大学
Promoted to Univ. 1929
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International StudentsInternational Students
Asia 847Europe 78 North America 12
South America 24Oceania 5
Africa 16
Total 982
Country Students
China 403
S. Korea 130
Indonesia 64
Thailand 55
Vietnam 60
Malaysia 28
(As of May. 1, 2005)
Total 10,000 students: 5,000 under graduate
5,000 graduate
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• There were many inventions in the 20th
century:Airplane, Nuclear Power generation,
Computer,Space aircraft, etc
• However, everything has to be controlled by electronics
• ElectronicsMost important invention in the 20th
century• What is Electronics: To use electrons,
Electronic Circuits
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Lee De Forest
Electronic Circuits started by the invention of vacuum tube (Triode) in 1906
Cathode(heated) Grid
Anode(Positive bias)
Thermal electrons from cathodecontrolled by grid bias
Same mechanism as that of transistor
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4 wives of Lee De Forest
1906 Lucille Sheardown1907 Nora Blatch1912 Mary Mayo, singer1930 Marie Mosquini, silent film actress
Mary Marie
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First Computer Eniac: made of huge number of vacuum tubes 19Big size, huge power, short life time filament
Today's pocket PCmade of semiconductor has much higher performance with extremely low power consumption
dreamed of replacing vacuum tube with solid-state device
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History of Semiconductor devices
1947, 1st Point Contact Bipolar Transistor: Ge Semiconductor, Bardeen, Brattin
Nobel Prize1948, 1st Junction Bipolar Transistor,
Ge Semiconductor, SchokleyNobel Prize
1958, 1st Integrated Circuits, Ge Semiconductor, J.Kilby Nobel Prize
1959, 1st Planar Integrated Circuits, Noice
1960, 1st MOS Transistor, Kahng, Si Semiconductor
1963, 1st CMOS Circuits, C.T. Sah and F. Wanlass9
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History of Electronic Devices
Transistor Concept
IC
Vacuum tube 1st Electronic circuits
Solid-State Circuits
Silicon TechnologyLSI
2000
706050
30
2010
1900TriodeDiode
MOSFETMISFET
bipolarICSi-MOSFET
1st Transistor
VLSI
LSI
CMOS
30 years
ULSI
20 years
10 years
Low Power
High Integration
Low PowerHigh speedHigh integration
Low PowerHigh speedHigh integration
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J.E.LILIENFELD
J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENTFiled March 28, 1928
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ElectronSemiconductor
Gate Electrode
Gate InsulatorNegative bias
Positive bias
Capacitor structure with notch
No current
Current flows
Electricfield
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Gate ElectrodePoly-crystal Si
Gate InsulatorSiO2
Drain
SiSubstrate
Source
Channel N-MOS (N-type MOSFET)
Gate ElectrodePoly Si
Gate InsulatorSiO2
SubstrateSi
Use Gate Field Effect for switching
ee
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Source Channel Drain
0V
N+-Si P-Si
N-Si
0V
1V
Negative
Source Channel DrainN-Si1V
N+-Si P-Si
Surface Potential (Negative direction)
Gate Oxd
ChannelSource Drain
Gate electrode
S D
G
0 bias for gate Positive bias for gate
Surface
Electron flow
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N-MOS
Source Drain
Source Drain
(N-type MOSFET)
Gate
P-MOS (P-type MOSFET)
Gate
Hole flow
Electron flow
Current flow
Current flow
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However, no one could realize MOSFET operation for more than 30 years.Because of very bad interface property between the semiconductor and gate insulatorEven Shockley!
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Very bad interface property between the semiconductor and gate insulator
Even Shockley!
eGe
GeO Electric Shielding
CarrierScattering
Interfacial Charges
Drain Current was several orders of magnitude smthan expected
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1947: 1st transistor W. Bratten,
W. ShockleyBipolar using Ge
However, they found amplification phenomenon when investigatingGe surface when putting needles.This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism)
J. Bardeen
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1958: 1st Integrated Circuit Jack S. Kilby
Connect 2 bipolar transistors in theSame substrate by bonding wire.
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1960: First MOSFET by D. Kahng and M. Atalla
Top View
Al Gate
Source
Drain
Si
Si
断面
Al
SiO2
Si
Si/SiO2 Interface is extraordinarily good
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1970,71: 1st generation of LSIs
DRAM Intel 1103 MPU Intel 4004
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MOS LSI experienced continuous progress for many years
1960s IC (Integrated Circuits) ~
1970s LSI (Large Scale Integrated Circuit) ~1,0
1980s VLSI (Very Large Scale IC) ~10,0
1990s ULSI (Ultra Large Scale IC) ~1,000,0
2000s ?LSI (? Large Scale IC) ~1000,000
Name of Integrated Circuits Number of Transistors
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Gate ElectrodePoly Si
Gate InsulatorSiO2
Drain
SiSubstrate
Source
Channel N-MOS (N-type MOSFET)
Gate ElectrodePoly Si
Gate InsulatorSiO2
SubstrateSi
Use Gate Field Effect for switching
ee
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N-MOS
Source Drain
Source Drain
(N-type MOSFET)
Gate
P-MOS (P-type MOSFET)
Gate
Hole flow
Electron flow
Current flow
Current flow
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OFF Gate
Source
DrainSource
Drain
ON
Electrons
1 V
1 V0 V
0 V
Gate
1 V
1 V0 V
1 VElectron flow
High PotentialRegion
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OFF
OFF
Gate bias
Gate biasNegative voltage
Positive
Current
Negative
Current
ON
ON
Dra
in C
urre
nt
Dra
in C
urre
nt
Positive voltage
Threshold voltage
Threshold voltage
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CMOS
Complimentary MOS
Inverter
PMOS
NMOS
When NMOS is ON, PMOS is OFFWhen PMOS is ON, NMOS is OFF
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InputOutput
0 V
NMOS (OFF)
PMOS (ON)
1 V
1 V
0 V
0 V
1 V (0V)
(0 V)
(-1 V)
(-1V)
S
G
D
D
B
B
G
S
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InputOutput
1 V
NMOS (ON)
PMOS (OFF)
0 V
1 V
0 V
0 V
1 V (0V)
(0 V)
(0 V)
(-1V)
S
G
D
D
B
B
G
S
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Output
Inverter
Input Output
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0 1 0 1
1 0 1 0
1
0
Outputτ τ τ
1
0
1
03τ 3τ
Oscillator
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Outputτ τ
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1 0 1
1 0 1
1
1
Outputτ τ
1 1
Latch (Memory)
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VD
C
CVD2
1
2P =
VD
C
Q Charge Q Discharge
1 cycle Clock frequency f
fCVD2
1
2P =
CMOS: Low Power: No DC current from Power supply to the ground
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ANDInput 1 1 1 0 0Input 2 1 0 1 0Output 1 0 0 0
NAND= NOT・ANDInput1 1 1 0 0Input2 1 0 1 0Output 0 1 1 1
1V 1V
2 input NAND Circuit
Input 1
Input 1
Input 2
Input 2
Output
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CMOS Technology: Indispensible for our human society
Al the human activities are controlled by CMOS
living, production, financing, telecommunication, transportation, medical care, education, entertainment, etc.
Without CMOS:
world economical activities immediately stop.
Cellarer phone dose not exists
Needless to say, but….
There is no computer in banks, and
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1900 1950 1960 1970 2000
VacuumTube
Transistor IC LSI ULSI
10 cm cm mm 10 µm 100 nm
In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.
10-1m 10-2m 10-3m 10-5m 10-7m
Downsizing of the components has been the driving force for circuit evolution
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Downsizing1. Reduce Capacitance
Reduce switching time of MOSFETsIncrease clock frequency
Increase circuit operation speed2. Increase number of Transistors
Parallel processingIncrease circuit operation speed
Thus, downsizing of Si devices is the most important and critical issu38
Downsizing contribute to the performance increase in double ways 一石二鳥
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Late 1970’s 1µm: SCEEarly 1980’s 0.5µm: S/D resistanceEarly 1980’s 0.25µm: Direct-tunneling of gate SiOLate 1980’s 0.1µm: ‘0.1µm brick wall’(various)
2000 50nm: ‘Red brick wall’ (various)
2000 10nm: Fundamental?
Period Expected Cause limit(size)
Many people wanted to say about the limit. Past predictions were not correct!!
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Historically, many predictions of the limit of downsizing.VLSI text book written 1979 predict that 0.25 micro-meter would be the limit because of direct-tunneling current through the very thin-gate oxide.
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41C. Mead L. Conway
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VLSI textbookFinally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide .....begin to make the devices of smaller dimension unworkable.
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Potential Barrier
Wave function
Direct-tunneling effect
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G
SD
Gate Oxide
Gate OxideGate Electrode
Si Substrate
Direct tunneling leakage current start to flow when the thickness is 3 nm.
Direct tunnelingcurrent
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Direct tunneling leakage wfound to be OK! In 1994!
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.40.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.10.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.020.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.40.0 0.5 1.0 1.5
Vd (V)
Id (m
A / μ
m)
Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm
Gate electrode
Si substrate
Gate oxide
MOSFETs with 1.5 nm gate oxide
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G
S D
Lg
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Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.40.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.40.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.10.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.10.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.020.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.020.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.40.0 0.5 1.0 1.5
Vd (V)
Id (m
A/ μ
m)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.40.0 0.5 1.0 1.5
Vd (V)
Id (m
A/ μ
m)
Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm
Gate leakage: Ig ∝ Gate Area ∝ Gate length (Lg)
Id
Drain current: Id ∝ 1/Gate length (Lg)Lg small,
Then, Ig small, Id large, Thus, Ig/Id very small
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G
S D
Ig Id
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Never Give Up!
There would be a solution!
Think, Think, and Think!
Or, Wait the time!Some one will think for you
No one knows future!
Do not believe a text book statement, blindly!
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Qi Xinag, ECS 2004, AMD47
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Gate Oxd
Channel
Electronwavelength
10 nm
Channel length?Downsizing limit?
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5 nm gate length CMOS
H. Wakabayashi et.al, NEC
IEDM, 2003
Length of 18 Si atoms
Is a Real Nano Device!!
5 nm
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Gate Oxd
Channel
Electronwavelength
10 nm
Tunnelingdistance
3 nm
Atomdistance
0.3 nm
Channel lengthGate oxide thickness
Downsizing limit!
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Electronwavelength
10 nm
Tunnelingdistance
3 nm
Atomdistance
0.3 nm
MOSFET operation
Lg = 2 ~ 1.5 nm?Below this, no one knows future!
Prediction now!
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Maybe, practical limit around 5 nm.
Vg
Id
Vth (Threshold Voltage)
Vg=0V
SubthreshouldLeakage Current
When Gate length Smaller, Subthrehold Leakage Current Larger
Subthreshold CurrentIs OK at Single Tr.
But not OKFor Billions of Trs.
ONOFF
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Vg (V)
Log Id
10-6A10-7A10-8A10-9A10-10A
Vg = 0VVthVth
Subthresholdleakage currentincrease Vth lowering
We have to reduce theSupply voltage.
Then Vth should be lowered.
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Electronwavelength
10 nm
Tunnelingdistance
3 nm
Atomdistance
0.3 nm
MOSFET operationLg = 2 ~ 1.5 nm?
Below this, no one knows future!
Prediction now!
Practical limit for integrationLg = 5 nm?
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Ultimate limitation
10-5
10-4
10-3
10-2
10-1
100
101
102
1970 1990 2010 2030 2050
MPU LgJunction depthGate oxide thickness
Direct-tunneling
ITRS Roadmap(at introduction)
Wave length of electron
Distance between Si atomsSize
(µm
), Vo
ltage
(V)
Min. V supply
10 nm3 nm
0.3 nm
ULTIMATELIMIT
However,Gate oxide thickne2 orders magnitude smaller
Close to limitation!!
Lg: Gate length downsizing will continue to another 10-15 years 55
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By Robert Chau, IWGI 200
0.8 nm Gate Oxide Thickness MOSFETs operat
0.8 nm: Distance of 3 Si atoms!!
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So, we are now in the limitation of downsizing?
Do you believe this or do not?
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There is a solution!To use high-k dielectrics
Thin gate SiO2Thick gate high-k dielectrics
Almost the same electric characteristics
However, very difficult and big challenge!Remember MOSFET had not been realizedwithout Si/SiO2!
K: Dielectric Constan
Thick
Small leakageCurrent
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Historical Trend of New Material for Gate Stack
1st FET LSIPMOS
NMOS CMOSIC
Gate insulator
Gate electrode
1960 1970 1980 1990 2000 05
MOSFETGate Stackin production
SiO2 SiOxNy
DoublePoly SiAl N+Poly Si
Silicide above Poly Si electrode TiSi2 CoSi2WSi2MoSi2 NiSi
MOSFET
DRAM Capacitor
NV Memory
Analog/RF
Al2O3, ZrO2
Ni3Si4 Stack NO(Si3N4/SiO2) R&D for high-k
NO, AO (Al2O3/SiO2)
Recent new high-kPure Si Period
(O)NO, Si3N4
(O)NO, Ni3Si4 Ta2O5 , Al2O3,
Ta2O5 ,
Hfbase
DoubleMetal
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R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
●
● Gas or liquidat 1000 K
●H
○Radio activeHe
● ● ● ● ● ●Li Be
B C N O F Ne① ● ● ● ●NaMg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt
○La Ce Pr Nd PmSmEuGdTbDyHoEr TmYb Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr
★
☆
Candidates
● ●Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①
○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr
★
☆
②
③
Unstable at Si interfaceSi + MOX M + SiO2①
Si + MOX MSiX + SiO2
Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability
La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer
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0 10 20 30 40 50Dielectric Constant
4
2
0
-2
-4
-6
SiO2
Ban
d D
isco
ntin
uity
[eV]
Si
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Constan
Band offset
Oxide
Leakage Current by Tunneling
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62
Intel’s announcement, January 26, 2007, and IEDM Dec 2007
Hafnium-based high-k material by ALD: EOT= 1nmSpecific gate metals ( Intel’s trade secret)
Different Metals for NMOS and PMOSUse of 193nm dry lithography
From 65 nm to 45 nm Tech.Tr density: 2 times increaseTr switching power: 30% reduction Tr switching speed: 20% improvementS-D leakage power: 5 times reductionGate oxide leakage: 10 times reduction
45nm processors (Core™2 family processors "Penryn") running Windows* Vista*, Linux* etc.
45nm production in the second half of 2007
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63
PMOS
High-k gate insulator MOSFETs for Intel: EOT=1nm
EOT: Equivalent Oxide Thickness
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64
History and future of TransistorShrinking, Shrinking, and Shrinking!
Integration density: 1/L2 Increase
Switching speed CV/I Decrease
C, V ∝ L
Power consumption CV2/2 Decrease
C: Capacitance V: Voltage
1970
Gate lengthGate Oxd Thickness
10,000 nm200725 nm
100 nm 1 nm
and then, Shrinking, Shrinking, and Shrinking!
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65Year
Pow
er p
er M
OSF
ET (P
)
P∝L
g 3
(Scaling)
EOT Limit0.7~0.8 nm
EOT=0.5nm
TodayEOT=1.0nm
Now
45nm nodeLg=22nm
One order of Magnitude
Si
HfO2
Metal
SiO2/SiON
Si
High-k
Metal
Direct ContactOf high-k and Si
Si
MetalSiO2/SiON
0.5~0.7nm
Introduction of High-kStill SiO2 or SiONIs used at Si interface
For the past 45 yearsSiO2 and SiON
For gate insulator
EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.
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66
R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
●
● Gas or liquidat 1000 K
●H
○Radio activeHe
● ● ● ● ● ●Li Be
B C N O F Ne① ● ● ● ●NaMg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt
○La Ce Pr Nd PmSmEuGdTbDyHoEr TmYb Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr
★
☆
Candidates
● ●Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①
○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr
★
☆
②
③
Unstable at Si interfaceSi + MOX M + SiO2①
Si + MOX MSiX + SiO2
Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability
La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer
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1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
0 0.5 1 1.5 2 2.5 3
EOT ( nm )
Cur
rent
den
sity
( A
/cm
2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)
Gate Leakage vs EOT, (Vg=|1|V)
La2O3
HfO2
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EOT = 0.48 nmTransistor with La2O3 gate insulator
Our results
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69
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d
(V)
W/L = 50µm /2.5µm
Vd (V) Vd (V) Vd (V)
EOT=0.37nm
Vth=-0.04VVth=-0.05VVth=-0.06V
EOT=0.37nm EOT=0.40nm EOT=0.48nmW/L = 50µm /2.5µm W/L = 50µm /2.5µm
0.48 0.37nm Increase of Id at 30%
La2O3
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New material research will give us many future possibilities and the most importantfor Nano-CMOS!
New material for Metal gate electrodeNew material for High-k gate dielectric
New materialFor Metal S/D
New channel material
Not only for high-k!
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magnification
6 µm NMOS LSI in 1974
5. S/D
Layers
3. Gate oxide
1. Si substrate2. Field oxide
4. Poly Si
6. Interlayer7. Aluminum 8. Passivation
Si substrate
Field SiO2
ILD (InterlayerDielectrics)
Al interconnects
Passivation (PSG)
(SiO2 + BPSG)Si substrate
Field SiO2
ILD (InterlayerDielectrics)
Al interconnects
Passivation (PSG)
(SiO2 + BPSG)
Poly Si gate electrode
Gate SiO2
Source / Drain
Poly Si gate electrode
Gate SiO2
Source / Drain
Materials1. Si
3. BPSG
5. PSG4. Al
2. SiO2
Atoms1. Si
4. B
(H, N, Cl)
2. O3. P
5. Al
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Y. Nishi, Si Nano Workshop, 2006,
(S. Sze, Based on invited talk at Stanford Univ., Aug. 1999)
Al
SiO2
Si
Poly Si
Si3N4
Air
HSQ
Polymer
TiN
TaN
Cu
Low-kdielectrics
Metals
La2O3
Ta2O5
HfO2
ZrO2
ZrSixOy
RuO2
Pt
IrO2
Y1
PZT
BST
High-kdielectrics
Electrode materials
Ferroelectrics
PtSi2WSi2CoSi2TiSi2MoSi2TaSi2
Silicides
W
1970 1980 1990 20001950 2010
Al
SiO2
Si
Ge SemiconductorsIII-V
Just examples!Many other candidatesNew materials
NiSi silicide
SiGe Semiconductor
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Perc
enta
ge o
f are
a in
SoC
[%]
2001 2004 2007 2010 2013 20160
20
40
60
80
100
Year
Memory
Logic
Due to design productivity, yield, and power
ITRS’ 2000: Y, Nishi, Si Nano Workshop, 2006
Memory area will increase
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32 Gb and 16Gb NAND, SAMSUNG
Now: After 45 Years from the 1st single MOSFE
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Capacity Node 1st FabricationProduction
512Mbit 120nm 2000 2001
1Gbit 100nm 2001 2002
2Gbit 90nm 2002 2003
4Gbit 70nm 2003 2004
8Gbit 60nm 2004 2005
16Gbit 50nm 2005 2006
32Gbit 40nm
256Gbit 20nm
Even Tbit would be possible in future!
Samsung’s NAND flash trend
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Already 32 Gbit: larger than that of world populationcomparable for the numbers of neuronsin human brain
Samsung announced 256 Gbit will be produced in 2010.Only 4 years from now.256Gbit: larger than those of # of stars in galaxies
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Moore’s Law & More
More Moore and More than Moore
http://strj-jeita.elisasp.net/pdf_ws_2005nendo/9A_WS2005IRC_Ishiuchi.pdf
ITRS 2005 EditionQuestion what is the other side of the cloud? 77
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We could keep the Moore’s law after 2020Without downswing the gate length
What is Moore’s law.to increase the number (#) of Tr. In a chip
Now, # of Tr. in a chip is limited by power.key issue is to reduce the power.to reduce the supply voltage is still effective
To develop devices with sufficiently high drain current under low supply voltage is important.
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F.-L.Yang, VLSI2004
FinFET to Nanowire
Ion/Ioff=230000Ion/Ioff=52200
Channel conductance is well controlled by Gateeven at L=5nm
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Selection of MOSFET structure for high conduction:Nano-wire or Nano-tube FETs is promising
3 methods to realize High-conduction at Low voltageM1.Use 1D ballistic conduction
M2.Increase number of quantum channel
M3.Increase the number of wire or tube per area3D integration of wire and tubes
For suppression of Ioff, the Nanowire/tube is also good.80
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1D conduction per one quantum channel:G = 2e2/h = 77.8 µS/wire or tuberegardless of gate length and channel material
That is 77.8 µA/wire at 1V supply
This an extremely high value
However, already 20mA/wire was obtained experimentaly by Samsung
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1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
Bulk
DG
dia~3nm
dia~10nm
ITRS (SOI)
ITRS (DG)
ITRS(Bulk)
Si Nanowire
Ion (uA/um)
Ioff
(nA
/um
)
1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
Bulk
DG
dia~3nm
dia~10nm
ITRS (SOI)
ITRS (DG)
ITRS(Bulk)
Si Nanowire
Ion (uA/um)
Ioff
(nA
/um
)Off Current
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Increase the Number of quantum channels
Energy band of Bulk Si
Eg
By Prof. Shiraishi of Tsukuba univ.
Energy band of 3 x 3 Si wire
4 channels can be used
Eg
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Maximum number of wires per 1 µm
Surrounded gate type MOS
Front gate type MOS 165 wires /µm
33 wires/µm
High-k gate insulator (4nm)Si Nano wire (Diameter 2nm)
Metal gate electrode(10nm)
Surrounded gate MOS
30nm
6nm6nm pitchBy nano-imprint method
30nm pitch: EUV lithograpy
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SiSiGe
SiSiGe
...
Selective EtchingDry EtchingSi/SiGe multistacked wafer
H2 Annealing
SiSiGeSi
(c) Selective Etching
(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer
(d) H2 Annealing
(e) Gate Oxide (f) Gate, S/D Formation
SiSiGeSi
(c) Selective Etching
(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer
(d) H2 Annealing
(e) Gate Oxide (f) Gate, S/D Formation
Increase the number of wires towards vertical dimension
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2015 2020 2025 2030 20352015 2020 2025 2030 2035
Cloud
Beyond the horizon
2010
?More Moore
ITRS Beyond CMOS
? ? ?? ? ? More Moore ??
ITRS
PJT(2007~2012)
2007
Horizon
Extended CMOS: More Moore + CMOS logic
Ribbon
Tube
Extended CMOS
Si Fin, Tri-gate
Si Nano wire
III-V及びGe Nano wire
製品段階
開発段階
研究段階
Production
Research
Development
Natural direction of downsizing
Diameter = 2nm
Si Channel
Nanowire
Tube, Ribbon
Selection
-
Problem:Mechanical Stress, Roughness
1D - High conduction
More perfect crystal
CNT
Graphene
Diameter = 10nm Problem:Hiigh-k gate oxides, etching of III-V wire
Further higher conductionBy multi quantum channel Selection
Our new roadmap
High conductionBy 1D conduction
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Scaling proceeds
Siz
e(Gate length etc)
Saturation of Downsizing
2020?
5 nm?
New Materials, New Process, New Structure(Logic, Memory)
Hybrid integration of different functional Chip Increase of SOC functionality
3D integration of memory cell3D integration of logic devices
Low cost for LSI processRevolution for CR,Equipment, Wafer
Miniaturization of Interconnects on PCB(Printed Circuit Board)
Introduction of algorithmof bio-systemBrain of insects, human
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Brain Ultra small volumeSmall number of neuron cellsExtremely low power
Real time image processing(Artificial) Intelligence3D flight control
Sensor
InfraredHumidityCO2
Mosquito
Dragonfly is further highperformance
System andAlgorism becomes more important!
But do not know how?
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Thank you for your attention!
89