Fundamentals of Computer Organization and Design978-0-387-21566-2/1.pdf · Fundamentals of Computer...

Fundamentals of Computer Organization and Design

Sivarama P. DandamudiSchool of Computer Science

Carleton University

September 22, 2002

TEXTS IN COMPUTER SCIENCE

EditorsDavid Gries

Fred B. Schneider

SpringerNew YorkBerlinHeidelbergHong KongLondonMilanParisTokyo

TEXTS IN COMPUTER SCIENCE

Alagarand Periyasamy, Specification of Software Systems

Apt and Olderog, Verification of Sequential and ConcurrentPrograms, Second Edition

Back and von Wright, Refinement Calculus

Beidler, Data Structures and Algorithms

Bergin, Data Structure Programming

Brooks, C Programming: The Essentials for Engineers and Scientists

Brooks, Problem Solving with Fortran 90

Dandamudi, Fundamentals of Computer Organization and Design

Dandamudi, Introduction to Assembly Language Programming

Fitting, First-Order Logic and Automated Theorem Proving,Second Edition

Griilmeyer, Exploring Computer Science with Scheme

Homer and Selman, Computability and Complexity Theory

Immerman, Descriptive Complexity

Jalote, An Integrated Approach to Software Engineering, Second Edition

Kizza, Ethical and Social Issues in the Information Age, Second Edition

Kozen, Automata and Computability

{continued ufler index)

Sivarama P. Dandamudi

FUNDAMENTALS OFCOMPUTER ORGANIZATION

AND DESIGN

With 361 Illustrations

Springer

Sivarama P. DandamudiSchool of Computer ScienceCarieton UniversityOttawa. Ontario K1S 5B6, [email protected]

Series Editors:David Gries Fred B. SchneiderDepartment of Computer Science Department of Computer Science415 Boyd Graduate Studies Upson Hall

Research Center Cornell UniversityThe University of Georgia Ithaca, NY 14853-7501, USAAthens, GA 306D2-7404, USA

Cover illustration: "Outpouring." by Pam Clocksin: used with permission.

Library oi Cono/ess Cataloging in-Publication DataDandaniudi, Sivarama P., 1955-

Fundamentais of computer organization and deslgn/Sivarama P. Dandamudi.p. cm.

ncludes bibliographical references and Index.ISBN 0-387-95211-X (tic; alk. paper!1, Computer engineering. I. Title.

TK7B85 D283 2002621.39'1— dc21 2002024154

ISBN 0-367-96211-X Printed on acid-free paper.

£ 2003 Springer-Verlag New York, Inc.Ail rights reserved. This work may not be translated or copied In whole or in part without the written permission olthe publisher (Springer-Verlag New York, Inc., 175 Fifth Avenue, New York, NY 10010, USA), except lor briet excerptsIn connection with reviews or scholarly analysis. Use In connection with any to rn of Information storage and retrieval,electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developedis forbidden.The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are notidentified as such, is noi to be taken as an expression of opinion as to whether or not they are subject to proprietaryrights.

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Springer-Verlag New York Berlin HeidelbergA member of BertelsmanitSpringer Science+Business Media GmbH

Tomy parents, Subba Rao and Prameela Rani,

my wife, Sobha,and

my daughter, Veda

Preface

Computer science and engineering curricula have been evolving at a faster pace to keep up withthe developments in the area. This often dictates that traditional courses will have to be com-pressed to accommodate new courses. In particular, it is no longer possible in these curriculato include separate courses on digital logic, assembly language programming, and computerorganization. Often, these three topics are combined into a single course. The current textbooksin the market cater to the old-style curricula in these disciplines, with separate books availableon each of these subjects. Most computer organization books do not cover assembly languageprogramming in sufficient detail. There is a definite need to support the courses that combineassembly language programming and computer organization. This is the main motivation forwriting this book. It provides a comprehensive coverage of digital logic, assembly languageprogramming, and computer organization.

Intended UseThis book is intended as an undergraduate textbook for computer organization courses offeredby computer science and computer engineering/electrical engineering departments. Unlikeother textbooks in this area, this book provides extensive coverage of assembly language pro-gramming and digital logic. Thus, the book serves the needs of compressed courses.

In addition, it can be used as a text in vocational training courses offered by communitycolleges. Because of the teach-by-example style used in the book, it is also suitable for self-study by computer professionals and engineers.

vii

viii Preface

PrerequisitesThe objective is to support a variety of courses on computer organization in computer scienceand engineering departments. To satisfy this objective, we assume very little background onthe part of the student. The student is assumed to have had some programming experience in astructured, high-level language such as C or Java™. This is the background almost all studentsin computer science and computer engineering programs typically acquire in their first yearof study. This prerequisite also implies that the student has been exposed to the basics of thesoftware-development cycle.

FeaturesHere is a summary of the special features that set this book apart:

• Most computer organization books assume that the students have done a separate digitallogic course before taking the computer organization course. As a result, digital logicis covered in an appendix to provide an overview. This book provides detailed cover-age of digital logic, including sequential logic circuit design. Three complete chaptersare devoted to digital logic topics, where students are exposed to the practical side withdetails on several example digital logic chips. There is also information on digital logicsimulators. Students can conveniently use these simulators to test their designs.

• This book provides extensive coverage of assembly language programming, comprisingassembly language of both CISC and RISC processors. We use the Pentium as the rep-resentative of the CISC category and devote more than five chapters to introducing thePentium assembly language. The MIPS processor is used for RISC assembly languageprogramming. In both cases, students actually write and test working assembly languageprograms. The book’s homepage has instructions on downloading assemblers for bothPentium and MIPS processors.

• We introduce concepts first in simple terms to motivate the reader. Later, we relate theseconcepts to practical implementations. In the digital logic part, we use several chips toshow the type of implementations done in practice. For the other topics, we consistentlyuse three processors—the Pentium, PowerPC, and MIPS—to cover the CISC to RISCrange. In addition, we provide details on the Itanium and SPARC processors.

• Most textbooks in the area treat I/O and interrupts as an appendage. As a result, thistopic is discussed very briefly. Consequently, students do not get any practical experienceon how interrupts work. In contrast, we use the Pentium to illustrate their operation.Several assembly language programs are used to explain the interrupt concepts. We alsoshow how interrupt service routines can be written. For instance, one example in thechapter on interrupts replaces the system-supplied keyboard service routine by our own.By understanding the practical aspects of interrupt processing, students can write theirown programs to experiment with interrupts.

Preface ix

• Our coverage of system buses is comprehensive and up-to-date. We divide our coverageinto internal and external buses. Internal buses discussed include the ISA, PCI, PCI-X,AGP, and PCMCIA buses. Our external bus coverage includes the EIA-232, SCSI, USB,and IEEE 1394 (FireWire) serial buses.

• Extensive assembly programming examples are used to illustrate the points. A set ofinput and output routines is provided so that the reader can focus on developing assemblylanguage programs rather than spending time in understanding how input and output canbe done using the basic I/O functions provided by the operating system.

• We do not use fragments of assembly language code in examples. All examples arecomplete in the sense that they can be assembled and run to give a better feeling as tohow these programs work.

• All examples used in the textbook and other proprietary I/O software are available fromthe book’s homepage (www.scs.carleton.ca/˜sivarama/org_book). In ad-dition, this Web site also has instructions on downloading the Pentium and MIPS assem-blers to give opportunities for students to perform hands-on assembly programming.

• Most chapters are written in such a way that each chapter can be covered in two or three60-minute lectures by giving proper reading assignments. Typically, important conceptsare emphasized in the lectures while leaving the other material in the book as a readingassignment. Our emphasis on extensive examples facilitates this pedagogical approach.

• Interchapter dependencies are kept to a minimum to offer maximum flexibility to instruc-tors in organizing the material. Each chapter clearly indicates the objectives and providesan overview at the beginning and a summary and key terms at the end.

Instructional SupportThe book’s Web site has complete chapter-by-chapter slides for instructors. Instructors can usethese slides directly in their classes or can modify them to suit their needs. Please contact theauthor if you want the PowerPoint source of the slides. Copies of these slides (four per page)are also available for distribution to students. In addition, instructors can obtain the solutionsmanual by contacting the publisher. For more up-to-date details, please see the book’s Webpage at www.scs.carleton.ca/˜sivarama/org_book.

Overview and OrganizationThe book is divided into eight parts. In addition, Appendices provide useful reference material.Part I consists of a single chapter and gives an overview of basic computer organization anddesign.

Part II presents digital logic design in three chapters—Chapters 2, 3, and 4. Chapter 2covers the digital logic basics. We introduce the basic concepts and building blocks that weuse in the later chapters to build more complex digital circuits such as adders and arithmeticlogic units (ALUs). This chapter also discusses the principles of digital logic design usingBoolean algebra, Karnaugh maps, and Quine–McCluskey methods. The next chapter deals

x Preface

with combinational circuits. We present the design of adders, comparators, and ALUs. Wealso show how programmable logic devices can be used to implement combinational logiccircuits. Chapter 4 covers sequential logic circuits. We introduce the concept of time throughclock signals. We discuss both latches and flip-flops, including master–slave JK flip-flops.These elements form the basis for designing memories in a later chapter. After presenting someexample sequential circuits such as shift registers and counters, we discuss sequential circuitdesign in detail. These three chapters together cover the digital logic topic comprehensively.The amount of time spent on this part depends on the background of the students.

Part III deals with system interconnection structures. We divide the system buses into in-ternal and external buses. Our classification is based on whether the bus interconnects compo-nents that are typically inside a system. Part III consists of Chapter 5 and covers internal systembuses. We start this chapter with a discussion of system bus design issues. We discuss both syn-chronous and asynchronous buses. We also introduce block transfer bus cycles as well as waitstates. Bus arbitration schemes are described next. We present five example buses including theISA, PCI, PCI-X, AGP, and PCMCIA buses. The external buses are covered in Part VIII, whichdiscusses the I/O issues.

Part IV consists of three chapters and discusses processor design issues. Chapter 6 presentsthe basics of processor organization and performance. We discuss instruction set architecturesand instruction set design issues. This chapter also covers microprogrammed control. In addi-tion, processor performance issues, including the SPEC benchmarks, are discussed. The nextchapter gives details about the Pentium processor. The information presented in this chapteris useful when we discuss Pentium assembly language programming in Part V. Pipelining andvector processors are discussed in the last chapter of this part. We use the Cray X-MP systemto look at the practical side of vector processors. After covering the material in Chapter 6,instructors can choose the material from Chapters 7 and 8 to suit their course requirements.

Part V covers Pentium assembly language programming in detail. There are five chaptersin this part. Chapter 9 provides an overview of the Pentium assembly language. All necessarybasic features are covered in this chapter. After reading this chapter, students can write simplePentium assembly programs without needing the information presented in the later four chap-ters. Chapter 10 describes the Pentium addressing modes in detail. This chapter gives enoughinformation for the student to understand why CISC processors provide complex addressingmodes. The next chapter deals with procedures. Our intent is to expose the student to the un-derlying mechanics involved in procedure calls, parameter passing, and local variable storage.In addition, recursive procedures are used to explore the principles involved in handling recur-sion. In all these activities, the important role played by the stack is illustrated. Chapter 12describes the Pentium instruction set. Our goal is not to present the complete Pentium instruc-tions, but a representative sample. Chapter 13 deals with the high-level language interface,which allows mixed-mode programming in more than one language. We use C and assemblylanguage to illustrate the principles involved in mixed-mode programming. Each chapter usesseveral examples to show how various Pentium instructions are used.

Part VI covers RISC processors in two chapters. The first chapter introduces the generalRISC design principles. It also presents details about two RISC processors: the PowerPC and

Preface xi

Intel Itanium. Although both are considered RISC processors, they also have some CISC fea-tures. We discuss a pure RISC processor in the next chapter. The Itanium is Intel’s 64-bitprocessor that not only incorporates RISC characteristics but also several advanced architec-tural features. These features include instruction-level parallelism, predication, and speculativeloads. The second chapter in this part describes the MIPS R2000 processor. The MIPS sim-ulator SPIM runs the programs written for the R2000 processor. We present MIPS assemblylanguage programs that are complete and run on the SPIM. The programs we present here arethe same programs we have written in the Pentium assembly language (in Part V). Thus, thereader has an opportunity to contrast the two assembly languages.

Part VII consists of Chapters 16 through 18 and covers memory design issues. Chapter 16builds on the digital logic material presented in Part II. It describes how memory units can beconstructed using the basic latches and flip-flops presented in Chapter 4. Memory mappingschemes, both full- and partial-mapping, are also discussed. In addition, we discuss how inter-leaved memories are designed. The next chapter covers cache memory principles and designissues. We use an extensive set of examples to illustrate the cache principles. Toward the endof the chapter, we look at example cache implementations in the Pentium, PowerPC, and MIPSprocessors. Chapter 18 discusses virtual memory systems. Note that our coverage of virtualmemory is from the computer organization viewpoint. As a result, we do not cover those as-pects that are of interest from the operating-system point of view. As with the cache memory, welook at the virtual memory implementations of the Pentium, PowerPC, and MIPS processors.

The last part covers the I/O issues. We cover the basic I/O interface issues in Chapter 19.We start with I/O address mapping and then discuss three techniques often used to interfacewith I/O devices: programmed I/O, interrupt-driven I/O, and DMA. We discuss interrupt-drivenI/O in detail in the next chapter. In addition, this chapter also presents details about externalbuses. In particular, we cover the EIA-232, USB, and IEEE 1394 serial interfaces and the SCSIparallel interface. The last chapter covers Pentium interrupts in detail. We use programmingexamples to illustrate interrupt-driven access to I/O devices. We also present an example toshow how user-defined interrupt service routines can be written.

The appendices provide a wealth of reference material needed by the student. Appendix Aprimarily discusses computer arithmetic. Character representation is discussed in Appendix B.Appendix C gives information on the use of I/O routines provided with this book and the Pen-tium assembler software. The debugging aspect of assembly language programming is dis-cussed in Appendix D. Appendix E gives details on running the Pentium assembly programson a Linux system using the NASM assembler. Appendix F gives details on digital logic sim-ulators. Details on the MIPS simulator SPIM are in Appendix G. Appendix H describes theSPARC processor architecture. Finally, selected Pentium instructions are given in Appendix I.

AcknowledgmentsSeveral people have contributed to the writing of this book. First and foremost, I would like tothank my wife, Sobha, and my daughter, Veda, for enduring my preoccupation with this project.

I thank Wayne Yuhasz, Executive Editor at Springer-Verlag, for his input and feedback in

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developing this project. His guidance and continued support for the project are greatly appreci-ated. I also want to thank Wayne Wheeler, Assistant Editor, for keeping track of the progress.He has always been prompt in responding to my queries. Thanks are also due to the staff atSpringer-Verlag New York, Inc., particularly Francine McNeill, for its efforts in producing thisbook. I would also like to thank Valerie Greco for doing an excellent job of copyediting thetext.

My sincere appreciation goes to the School of Computer Science at Carleton University forallowing me to use part of my sabbatical leave to complete this book.

FeedbackWorks of this nature are never error-free, despite the best efforts of the authors and othersinvolved in the project. I welcome your comments, suggestions, and corrections by electronicmail.

Ottawa, Ontario, Canada Sivarama P. DandamudiDecember 2001 [email protected]

http://www.scs.carleton.ca/˜sivarama

ContentsPreface vii

PART I: Overview 1

1 Overview of Computer Organization 31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1.1 Basic Terms and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2 Programmer’s View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.1 Advantages of High-Level Languages . . . . . . . . . . . . . . . . . . . . . 101.2.2 Why Program in Assembly Language? . . . . . . . . . . . . . . . . . . . . . 11

1.3 Architect’s View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.4 Implementer’s View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.5 The Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5.1 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.5.2 RISC and CISC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.6.1 Basic Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.6.2 Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.6.3 Two Important Memory Design Issues . . . . . . . . . . . . . . . . . . . . . 24

1.7 Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.8 Interconnection: The Glue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301.9 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.9.1 The Early Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311.9.2 Vacuum Tube Generation: Around the 1940s and 1950s . . . . . . . . . . . 311.9.3 Transistor Generation: Around the 1950s and 1960s . . . . . . . . . . . . . 321.9.4 IC Generation: Around the 1960s and 1970s . . . . . . . . . . . . . . . . . 321.9.5 VLSI Generations: Since the Mid-1970s . . . . . . . . . . . . . . . . . . . . 32

1.10 Technological Advances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331.11 Summary and Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351.12 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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PART II: Digital Logic Design 39

2 Digital Logic Basics 412.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.2 Basic Concepts and Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.2.1 Simple Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.2.2 Completeness and Universality . . . . . . . . . . . . . . . . . . . . . . . . . 442.2.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.3 Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.3.1 Expressing Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 492.3.2 Logical Circuit Equivalence . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.4 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542.4.1 Boolean Identities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542.4.2 Using Boolean Algebra for Logical Equivalence . . . . . . . . . . . . . . . 54

2.5 Logic Circuit Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552.6 Deriving Logical Expressions from Truth Tables . . . . . . . . . . . . . . . . . . . . 56

2.6.1 Sum-of-Products Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562.6.2 Product-of-Sums Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.6.3 Brute Force Method of Implementation . . . . . . . . . . . . . . . . . . . . 58

2.7 Simplifying Logical Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582.7.1 Algebraic Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582.7.2 Karnaugh Map Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602.7.3 Quine–McCluskey Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.8 Generalized Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712.9 Multiple Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732.10 Implementation Using Other Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.10.1 Implementation Using NAND and NOR Gates . . . . . . . . . . . . . . . . 752.10.2 Implementation Using XOR Gates . . . . . . . . . . . . . . . . . . . . . . . 77

2.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782.12 Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792.13 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3 Combinational Circuits 833.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833.2 Multiplexers and Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.2.1 Implementation: A Multiplexer Chip . . . . . . . . . . . . . . . . . . . . . . 863.2.2 Efficient Multiplexer Designs . . . . . . . . . . . . . . . . . . . . . . . . . 863.2.3 Implementation: A 4-to-1 Multiplexer Chip . . . . . . . . . . . . . . . . . . 873.2.4 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.3 Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893.3.1 Decoder Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903.3.2 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Contents xv

3.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943.4.1 A Comparator Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953.5.1 An Example Adder Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.6 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983.6.1 Programmable Logic Arrays (PLAs) . . . . . . . . . . . . . . . . . . . . . . 983.6.2 Programmable Array Logic Devices (PALs) . . . . . . . . . . . . . . . . . . 100

3.7 Arithmetic and Logic Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033.7.1 An Example ALU Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4 Sequential Logic Circuits 1094.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094.2 Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114.3 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.3.1 SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144.3.2 Clocked SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154.3.3 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.4 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164.4.1 D Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164.4.2 JK Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174.4.3 Example Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.5 Example Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204.5.1 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204.5.2 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.6 Sequential Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274.6.1 Binary Counter Design with JK Flip-Flops . . . . . . . . . . . . . . . . . . 1274.6.2 General Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132


PART III: Interconnection 145

5 System Buses 1475.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475.2 Bus Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.2.1 Bus Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505.2.2 Bus Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525.2.3 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

5.3 Synchronous Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535.3.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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5.3.2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545.3.3 Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

5.4 Asynchronous Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575.5 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.5.1 Dynamic Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595.5.2 Implementation of Dynamic Arbitration . . . . . . . . . . . . . . . . . . . . 161

5.6 Example Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655.6.1 The ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665.6.2 The PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685.6.3 Accelerated Graphics Port (AGP) . . . . . . . . . . . . . . . . . . . . . . . 1805.6.4 The PCI-X Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825.6.5 The PCMCIA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905.8 Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

PART IV: Processors 195

6 Processor Organization and Performance 1976.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1986.2 Number of Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

6.2.1 Three-Address Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996.2.2 Two-Address Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006.2.3 One-Address Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016.2.4 Zero-Address Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026.2.5 A Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046.2.6 The Load/Store Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 2066.2.7 Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3 Flow of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086.3.1 Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086.3.2 Procedure Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

6.4 Instruction Set Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136.4.1 Operand Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2146.4.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156.4.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166.4.4 Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6.5 Microprogrammed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2196.5.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256.5.2 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.6 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366.6.1 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376.6.2 Execution Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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6.6.3 Means of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386.6.4 The SPEC Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241


7 The Pentium Processor 2517.1 The Pentium Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517.2 The Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2537.3 The Pentium Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

7.3.1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2567.3.2 Pointer and Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2577.3.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2577.3.4 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

7.4 Real Mode Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607.5 Protected Mode Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 265

7.5.1 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2657.5.2 Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2667.5.3 Segment Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 2687.5.4 Segmentation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697.5.5 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2707.5.6 Which Segment Register to Use . . . . . . . . . . . . . . . . . . . . . . . . 270


8 Pipelining and Vector Processing 2738.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748.2 Handling Resource Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778.3 Data Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

8.3.1 Register Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798.3.2 Register Interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

8.4 Handling Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828.4.1 Delayed Branch Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . 2838.4.2 Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

8.5 Performance Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2868.5.1 Superscalar Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878.5.2 Superpipelined Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888.5.3 Very Long Instruction Word Architectures . . . . . . . . . . . . . . . . . . . 290

8.6 Example Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918.6.1 Pentium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918.6.2 PowerPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948.6.3 SPARC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978.6.4 MIPS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

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8.7 Vector Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2998.7.1 What Is Vector Processing? . . . . . . . . . . . . . . . . . . . . . . . . . . . 3008.7.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3018.7.3 Advantages of Vector Processing . . . . . . . . . . . . . . . . . . . . . . . . 3038.7.4 The Cray X-MP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3048.7.5 Vector Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3068.7.6 Vector Stride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3088.7.7 Vector Operations on the Cray X-MP . . . . . . . . . . . . . . . . . . . . . 3098.7.8 Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

8.8 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3128.8.1 Pipeline Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3128.8.2 Vector Processing Performance . . . . . . . . . . . . . . . . . . . . . . . . 314


PART V: Pentium Assembly Language 319

9 Overview of Assembly Language 3219.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3229.2 Assembly Language Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3229.3 Data Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

9.3.1 Range of Numeric Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 3269.3.2 Multiple Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279.3.3 Multiple Initializations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3299.3.4 Correspondence to C Data Types . . . . . . . . . . . . . . . . . . . . . . . . 3309.3.5 LABEL Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

9.4 Where Are the Operands? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3329.4.1 Register Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3329.4.2 Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3339.4.3 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3349.4.4 Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

9.5 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3389.5.1 The mov Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3389.5.2 The xchg Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3399.5.3 The xlat Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

9.6 Pentium Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . 3409.6.1 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3409.6.2 Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3459.6.3 Iteration Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3529.6.4 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3549.6.5 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3579.6.6 Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

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9.7 Defining Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3649.7.1 The EQU Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3649.7.2 The = Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

9.8 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669.9 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3689.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3799.11 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3809.12 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

10 Procedures and the Stack 38710.1 What Is a Stack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38810.2 Pentium Implementation of the Stack . . . . . . . . . . . . . . . . . . . . . . . . . 38810.3 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

10.3.1 Basic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39010.3.2 Additional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

10.4 Uses of the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39310.4.1 Temporary Storage of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 39310.4.2 Transfer of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39410.4.3 Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

10.5 Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39410.6 Assembler Directives for Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . 39610.7 Pentium Instructions for Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . 397

10.7.1 How Is Program Control Transferred? . . . . . . . . . . . . . . . . . . . . . 39710.7.2 The ret Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

10.8 Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39910.8.1 Register Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39910.8.2 Stack Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40210.8.3 Preserving Calling Procedure State . . . . . . . . . . . . . . . . . . . . . . . 40610.8.4 Which Registers Should Be Saved? . . . . . . . . . . . . . . . . . . . . . . 40610.8.5 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

10.9 Handling a Variable Number of Parameters . . . . . . . . . . . . . . . . . . . . . . 41710.10 Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42010.11 Multiple Source Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

10.11.1 PUBLIC Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42710.11.2 EXTRN Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

10.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43010.13 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43110.14 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

11 Addressing Modes 43511.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

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11.2 Memory Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43711.2.1 Based Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43911.2.2 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43911.2.3 Based-Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

11.3 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44111.4 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

11.4.1 One-Dimensional Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 44911.4.2 Multidimensional Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45011.4.3 Examples of Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

11.5 Recursion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45511.5.1 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456


12 Selected Pentium Instructions 47112.1 Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

12.1.1 The Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47212.1.2 The Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47412.1.3 The Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47712.1.4 The Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47912.1.5 The Auxiliary Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48012.1.6 The Parity Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48112.1.7 Flag Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

12.2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48412.2.1 Multiplication Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48512.2.2 Division Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48812.2.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

12.3 Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49712.3.1 Indirect Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49712.3.2 Conditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

12.4 Implementing High-Level Language Decision Structures . . . . . . . . . . . . . . . 50412.4.1 Selective Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50412.4.2 Iterative Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

12.5 Logical Expressions in High-Level Languages . . . . . . . . . . . . . . . . . . . . 51012.5.1 Representation of Boolean Data . . . . . . . . . . . . . . . . . . . . . . . . 51012.5.2 Logical Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51112.5.3 Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51112.5.4 Evaluation of Logical Expressions . . . . . . . . . . . . . . . . . . . . . . . 511

12.6 Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51512.6.1 Bit Test and Modify Instructions . . . . . . . . . . . . . . . . . . . . . . . . 51512.6.2 Bit Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

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12.7 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51612.8 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

12.8.1 String Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52612.8.2 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52712.8.3 String Processing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 53612.8.4 Testing String Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . 540


13 High-Level Language Interface 55113.1 Why Program in Mixed-Mode? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55213.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55213.3 Calling Assembly Procedures from C . . . . . . . . . . . . . . . . . . . . . . . . . 554

13.3.1 Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55413.3.2 Returning Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55613.3.3 Preserving Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55613.3.4 Publics and Externals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55713.3.5 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

13.4 Calling C Functions from Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . 56213.5 Inline Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

13.5.1 Compiling Inline Assembly Programs . . . . . . . . . . . . . . . . . . . . . 56513.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56613.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56713.8 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

PART VI: RISC Processors 569

14 RISC Processors 57114.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57214.2 Evolution of CISC Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57214.3 RISC Design Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

14.3.1 Simple Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57514.3.2 Register-to-Register Operations . . . . . . . . . . . . . . . . . . . . . . . . 57614.3.3 Simple Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 57614.3.4 Large Number of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57614.3.5 Fixed-Length, Simple Instruction Format . . . . . . . . . . . . . . . . . . . 577

14.4 PowerPC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57814.4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57814.4.2 PowerPC Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

14.5 Itanium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59014.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

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14.5.2 Itanium Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59414.5.3 Handling Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60414.5.4 Predication to Eliminate Branches . . . . . . . . . . . . . . . . . . . . . . . 60514.5.5 Speculative Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60614.5.6 Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610


15 MIPS Assembly Language 61515.1 MIPS Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

15.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61615.1.2 General-Purpose Register Usage Convention . . . . . . . . . . . . . . . . . 61715.1.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61815.1.4 Memory Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

15.2 MIPS Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61915.2.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62015.2.2 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62115.2.3 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62315.2.4 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62715.2.5 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62715.2.6 Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62815.2.7 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62815.2.8 Branch and Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 630

15.3 SPIM System Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63215.4 SPIM Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63415.5 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63615.6 Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64315.7 Stack Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

15.7.1 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64915.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65715.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65815.10 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

PART VII: Memory 663

16 Memory System Design 66516.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66616.2 A Simple Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

16.2.1 Memory Design with D Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . 66716.2.2 Problems with the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

16.3 Techniques to Connect to a Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66916.3.1 Using Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

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16.3.2 Using Open Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 66916.3.3 Using Tristate Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

16.4 Building a Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67316.5 Building Larger Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

16.5.1 Designing Independent Memory Modules . . . . . . . . . . . . . . . . . . . 67616.5.2 Designing Larger Memories Using Memory Chips . . . . . . . . . . . . . . 678

16.6 Mapping Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68116.6.1 Full Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68116.6.2 Partial Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

16.7 Alignment of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68316.8 Interleaved Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

16.8.1 The Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68516.8.2 Synchronized Access Organization . . . . . . . . . . . . . . . . . . . . . . . 68616.8.3 Independent Access Organization . . . . . . . . . . . . . . . . . . . . . . . 68716.8.4 Number of Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68816.8.5 Drawbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689


17 Cache Memory 69317.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69417.2 How Cache Memory Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69517.3 Why Cache Memory Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69717.4 Cache Design Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69917.5 Mapping Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

17.5.1 Direct Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70317.5.2 Associative Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70717.5.3 Set-Associative Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

17.6 Replacement Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71117.7 Write Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71317.8 Space Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71517.9 Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71717.10 Types of Cache Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71817.11 Types of Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

17.11.1 Separate Instruction and Data Caches . . . . . . . . . . . . . . . . . . . . . 71917.11.2 Number of Cache Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72017.11.3 Virtual and Physical Caches . . . . . . . . . . . . . . . . . . . . . . . . . . 722

17.12 Example Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72217.12.1 Pentium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72217.12.2 PowerPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72417.12.3 MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

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17.13 Cache Operation: A Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72717.13.1 Placement of a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72717.13.2 Location of a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72817.13.3 Replacement Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72817.13.4 Write Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

17.14 Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72917.14.1 Cache Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72917.14.2 Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72917.14.3 Degree of Associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731


18 Virtual Memory 73518.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73618.2 Virtual Memory Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

18.2.1 Page Replacement Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . 73818.2.2 Write Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73918.2.3 Page Size Tradeoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74018.2.4 Page Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

18.3 Page Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74118.3.1 Page Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

18.4 The Translation Lookaside Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 74318.5 Page Table Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

18.5.1 Searching Hierarchical Page Tables . . . . . . . . . . . . . . . . . . . . . . 74518.6 Inverted Page Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74618.7 Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74818.8 Example Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

18.8.1 Pentium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75018.8.2 PowerPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75418.8.3 MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756


PART VIII: Input and Output 765

19 Input/Output Organization 76719.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76819.2 Accessing I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

19.2.1 I/O Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77019.2.2 Accessing I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

19.3 An Example I/O Device: Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . 77219.3.1 Keyboard Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77219.3.2 8255 Programmable Peripheral Interface Chip . . . . . . . . . . . . . . . . . 772

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19.4 I/O Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77419.4.1 Programmed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77519.4.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

19.5 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78419.5.1 Parity Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78419.5.2 Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78519.5.3 Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

19.6 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79119.6.1 Serial Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79419.6.2 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

19.7 Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80119.7.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80119.7.2 Additional USB Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . 80219.7.3 USB Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80319.7.4 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80319.7.5 USB Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80519.7.6 USB Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

19.8 IEEE 1394 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81019.8.1 Advantages of IEEE 1394 . . . . . . . . . . . . . . . . . . . . . . . . . . . 81019.8.2 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81119.8.3 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81219.8.4 Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81319.8.5 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81519.8.6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

19.9 The Bus Wars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82019.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82119.11 Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82319.12 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

20 Interrupts 82520.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82620.2 A Taxonomy of Pentium Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 82720.3 Pentium Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

20.3.1 Interrupt Processing in Protected Mode . . . . . . . . . . . . . . . . . . . . 82920.3.2 Interrupt Processing in Real Mode . . . . . . . . . . . . . . . . . . . . . . . 829

20.4 Pentium Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83120.4.1 DOS Keyboard Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83220.4.2 BIOS Keyboard Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

20.5 Pentium Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84220.6 Pentium Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

20.6.1 How Does the CPU Know the Interrupt Type? . . . . . . . . . . . . . . . . . 84720.6.2 How Can More Than One Device Interrupt? . . . . . . . . . . . . . . . . . . 848

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20.6.3 8259 Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . 84820.6.4 A Pentium Hardware Interrupt Example . . . . . . . . . . . . . . . . . . . . 850

20.7 Interrupt Processing in the PowerPC . . . . . . . . . . . . . . . . . . . . . . . . . . 85520.8 Interrupt Processing in the MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85720.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85920.10 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86020.11 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

APPENDICES 863

A Computer Arithmetic 865A.1 Positional Number Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

A.1.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867A.2 Number Systems Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

A.2.1 Conversion to Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868A.2.2 Conversion from Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . 870A.2.3 Conversion Among Binary, Octal, and Hexadecimal . . . . . . . . . . . . . 871

A.3 Unsigned Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874A.3.1 Arithmetic on Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . 875

A.4 Signed Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881A.4.1 Signed Magnitude Representation . . . . . . . . . . . . . . . . . . . . . . . 882A.4.2 Excess-M Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882A.4.3 1’s Complement Representation . . . . . . . . . . . . . . . . . . . . . . . . 883A.4.4 2’s Complement Representation . . . . . . . . . . . . . . . . . . . . . . . . 886

A.5 Floating-Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887A.5.1 Fractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887A.5.2 Representing Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . 890A.5.3 Floating-Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . 891A.5.4 Floating-Point Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896A.5.5 Floating-Point Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . 896

A.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897A.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898A.8 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900

B Character Representation 901B.1 Character Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901B.2 Universal Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903B.3 Unicode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903B.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904

C Assembling and Linking Pentium Assembly Language Programs 907C.1 Structure of Assembly Language Programs . . . . . . . . . . . . . . . . . . . . . . 908

Contents xxvii

C.2 Input/Output Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910C.2.1 Character I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912C.2.2 String I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912C.2.3 Numeric I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

C.3 Assembling and Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915C.3.1 The Assembly Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915C.3.2 Linking Object Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

C.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924C.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925C.6 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

D Debugging Assembly Language Programs 927D.1 Strategies to Debug Assembly Language Programs . . . . . . . . . . . . . . . . . . 928D.2 DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

D.2.1 Display Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930D.2.2 Execution Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933D.2.3 Miscellaneous Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934D.2.4 An Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

D.3 Turbo Debugger TD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938D.4 CodeView . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943D.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944D.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944D.7 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945

E Running Pentium Assembly Language Programs on a Linux System 947E.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948E.2 NASM Assembly Language Program Template . . . . . . . . . . . . . . . . . . . . 948E.3 Illustrative Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950E.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955E.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955E.6 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

F Digital Logic Simulators 957F.1 Testing Digital Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957F.2 Digital Logic Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

F.2.1 DIGSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958F.2.2 Digital Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959F.2.3 Multimedia Logic Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . 961F.2.4 Logikad Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962

F.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966F.4 Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966F.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

xxviii Contents

G SPIM Simulatorand Debugger 969

G.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969G.2 Simulator Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972G.3 Running and Debugging a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

G.3.1 Loading and Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973G.3.2 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

G.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977G.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977G.6 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

H The SPARC Architecture 979H.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979H.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980H.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982H.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984

H.4.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984H.4.2 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 984H.4.3 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986H.4.4 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987H.4.5 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988H.4.6 Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988H.4.7 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

H.5 Procedures and Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . 993H.5.1 Procedure Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993H.5.2 Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994H.5.3 Stack Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995H.5.4 Window Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

H.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000H.7 Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000H.8 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000

I Pentium Instruction Set 1001I.1 Pentium Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

I.1.1 Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001I.1.2 General Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002

I.2 Selected Pentium Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004

Bibliography 1033

Index 1037

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