Fundamental Algorithms for System Modeling, Analysis, and … · 2018-04-05 · EECS 144/244, UC...

Fundamental Algorithms for System Modeling, Analysis, and Optimization

Edward A. Lee, JaijeetRoychowdhury, Sanjit A. SeshiaUC BerkeleyEECS 144/244Fall 2011

Copyright © 2010-11, E. A. Lee, J. Roychowdhury, S. A. Seshia, All rights reserved

Lecture 1: Introduction, Logistics

EECS 144/244, UC Berkeley: 2

Algorithms in the Design & Analysis of Complex Systems


Modeling, Design, Analysis

Modeling is the process of gaining a deeper understanding of a system through imitation. Models specify what a system does.

Design is the structured creation of artifacts. It specifies how a system does what it does. This includes optimization.

Analysis is the process of gaining a deeper understanding of a system through dissection. It specifies why a system does what it does (or fails to do what a model says it should do).


The VisionDesign is a SCIENCE:

No matter what the application is, there are common features

Foundational work in mathematical modeling, algorithms, methodologies

To demonstrate the value of design SCIENCE, apply the foundational work to a variety of areas from electronics, to automotive, to avionics, to intelligent buildings, to biologicalsystems

A. Sangiovanni-Vincentelli


Lecture Outline

Introduction to Edward, Jaijeet, Sanjit, and all of you

Flavors of Modeling, Analysis, Optimization Digital systems

Cyber-Physical systems

Continuous-time systems

Course logistics


Academic background: Yale University (BS, 1979) MIT (SM, 1981) UC Berkeley (PhD, 1986)

Professional highlights: Bell Labs MTS (1979-1982) Founder and Senior Tech. Advisor, BDTI (1992-present) Chair of EE (2005-2006) Chair of EECS (2006-2008)

Edward A. LeeRobert S. Pepper Distinguished ProfessorEECS DepartmentUniversity of California, Berkeley

Research focus: design, modeling, and simulation of embedded, real‐time computational systems.

Research focus: design, modeling, and simulation of embedded, real‐time computational systems.


Jaijeet Roychowdhury

Past: PhD: UCB EECS (1993)

Bell Labs (1993-2000)

CeLight (2000-2001)

Univ. of Minnesota (2001-2008)

co-founder, Berkeley Design Automation (2003)

Research interests: modelling/simulation of continuous-time systems

widely-separated time scale problems

noise and variability

automated macromodelling


Sanjit A. Seshia

Theory Practice+

Example: GameTime: Timing analysis of embedded software by game-theoretic online learning

Algorithms (constraint solving, optimization, learning), Formal Methods (model checking, computational logic)

CAD for VLSI, Computer Security, Embedded Systems,Program Analysis

Research theme:Algorithms & Formal Methods for Dependable Computing

Associate Professor, EECSB.Tech, IIT BombayM.S. & Ph.D., Carnegie Mellon Univ.


Introductions to All of You

Your name, research/professional interests, grad/undergrad


Topics we will study in this course

Design Flows (very briefly)

Methodology of going from a model to implementation

Algorithms for Discrete Models Boolean function representation and manipulation

Algorithms for Continuous Models Solving non-linear equations

Algorithms for Cyber-Physical Models Scheduling for real-time systems

Cross-cutting Topics Timing analysis

From Algorithms to Software How to write well-structured, efficient code


Part I: Digital Systems


10 stars11

10 states100,000


Computer-Aided Design (CAD) for ICs / Electronic Design Automation (EDA)

731M transistors

CADTools


Evolution of Digital IC Design

Effort

(EDA tools effort)

Results

(Design Productivity)

a

b

s

q0

1

d

clk

Transistor entry

Schematic Entry

RTL Synthesis

What’s next?

McKinsey S-Curve

K. Keutzer


Evolution of the EDA Industry

Effort

(EDA tools effort)

Results

(Design Productivity)

a

b

s

q0

1

d

clk

Transistor entry - Calma, Computervision

Schematic Entry - Daisy, Mentor, Valid

Synthesis - Cadence, Synopsys

What’s next?

McKinsey S-Curve

K. Keutzer


Transistor Era

Key tools: Transistor-level layout – e.g.

Calma workstation Transistor-level simulation – e.g.

Spice Bonus: transistor-level

compaction – e.g. Cabbage

Size of circuits: 10’s of transistors to few thousand

Key abstractions and technologies: Transistor-level modeling,

simulation Logical gates- NAND, NOR, FF

and cell libraries Layout compactionK. Keutzer


Gate-level Schematic Era

Key tools: gate-level layout editor – Daisy,

Mentor, valid workstation

Gate-level simulator

Automated place and route

Size of circuits: 3,000 – 35,000 gates (12,000 to 140,000 transistors)

Key abstractions and technologies:

Logic-level simulation

Cell-based place and route

Static-timing analysis

a

b c_out

sumAdd_half_0_delay

a

b c_out

sumAdd_half_0_delay

(a b) c_in

(a + b) c_in + ab

(a b) c_in

a

b

c_in sum

c_out

ab

(ab)

Add_full_0_delay

w1

w2

w3

FAab

c_in

sumc_out

K. Keutzer


RTL Synthesis Era

Key tools: Hardware-description language

simulator – Verilog, VHDL

Logic synthesis tool - Synopsys

Automated place and route –Cadence, Avant!, Magma

Size of circuits: 35,000 gates to …?

Key abstractions and technologies: HDL simulation

Logic synthesis

Cell-based place and route

Static-timing analysis

Automatic-test pattern generation

Equivalence checking / verification

module Half_adder (Sum, C_out, A, B);output Sum, C_out;input A, B;

xor M1 (Sum, A, B); and M2 (C_out, A, B);

endmodule

module Full_Adder (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;Half_adder M1 (w1, w2, a, b);Half_adder M2 (sum, w3, w2, c_in);or M3 (c_out, w2, w3);

endmodule

module Full_Adder_4 (sum, c_out, a, b, c_in);output [3:0]sum;output c_out;input [3:0] a, b;input c_in;wire c_in2, c_in3, c_in4;Full_adder M1 (sum[0], c_in2, a[0], b[0], c_in);Full_adder M2 (sum[1], c_in3, a[1], b[1], c_in2);Full_adder M3 (sum[2], c_in4, a[2], b[2], c_in3);Full_adder M4 (sum[3], c_out, a[3], b[3], c_in4);

endmodule

K. Keutzer


RTL Synthesis Era

a

b c_out

sumAdd_half_0_delay

a

b c_out

sumAdd_half_0_delay

(a b) c_in

(a + b) c_in + ab

(a b) c_in

a

b

c_in sum

c_out

ab

(ab)

Add_full_0_delay

w1

w2

w3

FAab

c_in

sumc_out

module Half_adder (Sum, C_out, A, B);output Sum, C_out;input A, B;

xor M1 (Sum, A, B); and M2 (C_out, A, B);

endmodule

module Full_Adder (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;Half_adder M1 (w1, w2, a, b);Half_adder M2 (sum, w3, w2, c_in);or M3 (c_out, w2, w3);

endmodule


endmodule

K. Keutzer


RTL Synthesis Flow

RTLSynthesis

HDL

netlist

logicoptimization

netlist

Library/modulegenerators

physicaldesign

layout

HDLsimulation


endmodule

K. Keutzer


Transistor countdoubling roughlyevery two years

[wikipedia]


1

Log

ic T

rans

isto

rs p

er C

hip

(K)

Pro

du

c tiv

ity

Tra

ns.

/Sta

ff -

Mo.

10

100

1,000

10,000

100,000

1,000,000

10,000,000

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./S.M.

Source: SEMATECH19

81

198 3

198 5

198 7

198 9

199 1

199 3

199 5

199 7

199 9

200 3

200 1

200 5

200 7

200 9

xxx

x xx

x

Productivity Gap

Productivity Gap: Need for Improved CAD Tools


Major Challenges for Digital Design Today

Verification: Pre-silicon and post-siliconVerification is 70% of the pre-silicon design costPost-silicon validation is 35% of entire design cost

Error Resilience and SecurityScaling to 45 nm and below increasing probability of

device failure (e.g. single event upset)• E.g.: Amazon S3 outage for 8+ hours due to single bit flip

Increasing concern about security problems in hw or at the hw-sw interface

Design for ConcurrencyHow do we design 100+ core chip? Design of “network

on chip” poses serious design challenges.

Low Power/Energy First-class design concern; poses challenges for

verification


Part II: Cyber-Physical Systems

EECS 144/244, UC Berkeley: 25Courtesy of Kuka Robotics Corp.

Cyber-Physical Systems (CPS):Orchestrating networked computational resources with physical systems

Courtesy of Doug SchmidtCourtesy of Doug Schmidt

Power generation and distribution

Courtesy of General Electric

Military systems:

E-Corner, Siemens

Transportation(Air traffic control at SFO)

Avionics

Telecommunications

Factory automation

Instrumentation(Soleil Synchrotron)

Daimler-Chrysler

Automotive

Building Systems


CPS Example – Printing Press

• High‐speed, high precision• Speed: 1 inch/ms

• Precision: 0.01 inch

‐> Time accuracy: 10us

• Open standards (Ethernet)• Synchronous, Time‐Triggered

• IEEE 1588 time‐sync protocol

• Application aspects• local (control)

• distributed (coordination)

• global (modes)

Bosch‐Rexroth


Another Example of a CPS Application

STARMAC quadrotor aircraft (Tomlin, et al.)

Modeling:•Flight dynamics•Modes of operation•Transitions between modes•Composition of behaviors•Multi-vehicle interaction

Design:•Processors•Memory system•Sensor interfacing•Concurrent software•Real-time scheduling

Analysis•Specifying safe behavior•Achieving safe behavior•Verifying safe behavior•Guaranteeing timeliness


Typical Structure of a Cyber-Physical System

Composition of heterogeneous components and models.


Problems to Solve:

• Design of real-time software

• Processor selection and modeling

• Execution time analysis

• Design of custom hardware

• Network selection and modeling

• Sensor selection and modeling

• Joint dynamics of software and physical processes

• Validation (ensuring safety, liveness, correct functionality)

• Certification (satisfying customers, regulatory agencies).


A “Success” Story

The Boeing 777 was Boeing’s first fly-by-wire aircraft. It is deployed, appears to be reliable, and is succeeding in the marketplace. Therefore, it must be a success. However…



In “fly by wire” aircraft, certification of the software is extremely expensive. Regrettably, it is not the software that is certified but the entire system. If a manufacturer expects to produce a plane for 50 years, it needs a 50-year stockpile of fly-by-wire components that are all made from the same mask set on the same production line. Even a slight change or “improvement” might affect behavior and require the software to be re-certified.



Apparently, the software does not specify the behavior that was certified.

Fly-by-wire is about controlling the dynamics of a physical system. It is not about the transformation of data, which is what Turing/Church “computation” does.


A Key Challenge on the Cyber Side:Real-Time Software

Correct execution of a program in C, C#, Java, Haskell, etc. has nothing to do with how long it takes to do anything. All our computation and networking abstractions are built on this premise.

Programmers have to step outside the programming abstractions to specify timing behavior.


Compensating for this deficiency with algorithms

Execution time analysis:

Architectural modeling:• Two coupled pipelines (7-stage)• Shared instruction & data cache• Cache/Pipeline interaction

Plus program analysis:• Artificially simple example from Airbus• Simple control structures• Twelve independent tasks

Plus optimization algorithms:• Integer linear programming (ILP)

Leads to worst-case execution time (WCET).C. Ferdinand et al., “Reliable and precise WCET determination for a real-life processor.” EMSOFT 2001.


Cyber Physical Systems:Computational +

Physical

CPS is Multidisciplinary

Computer Science:

Carefully abstracts the physical world

System Theory:

Deals directly with physical quantities


Part III: Continuous-Time Systems

J. Roychowdhury, University of California at Berkeley Slide 38

CAD at Berkeley: History CAD research at Berkeley: design tools

late 60s and 70sCANCER, SPICE (Rohrer, Nagel, Cohen, Pederson, ASV, Newton, etc.)

SPLICE (Newton)

80sMAGIC (Ousterhout et. al.)

espresso (Brayton, ASV, Rudell, Wang et. al.)

MIS (Brayton, ASV, et. al.)

90sSIS, HSIS (Brayton, ASV et. al.)

VIS (Brayton, ASV, Somenzi et. al.)

Ptolemy (Lee et. al.)

2000sMVSIS (Brayton, Mishchenko et. al.)

BALM (Mishchenko, Brayton et. al.)

ABC (Mishchenko, Brayton et. al.)

MetroPolis, Metro II, Clotho (ASV et. al.)

Ptolemy II, HyVisual (Lee et. al.)

UCLID, Beaver (Seshia et. al.)


Course Logistics


Webpage, Books, etc.

The course webpage is the definitive source of information

http://embedded.eecs.berkeley.edu/eecsx44/

We’ll also use bSpace

No textbook. Readings will be posted / handed out for each set of lectures.

Some references will be placed on reserve in Engineering library.

GSI: Wenchao Li

See webpage for office hours, etc.


Format of Lectures

2 1.5 hour lectures per week (MW 2:30 – 4 pm)

1 hr “discussion” section each Wed 11-12

(usually a topic supporting homeworks/projects; sometimes an extension of lectures)


Grading

2 Midterms (20% each)

8-10 homework assignments (total ~ 25%)

1 course project (~ 35%)

Course project:

Graduate students (244): Must investigate a novel research idea

Undergraduates (144): Encouraged to do 244-style project (join with grads!); also permitted to do implementation projects or literature surveys

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