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Functional Verification of Dynamically Reconfigurable Systems (Version 2.3b)
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Transcript of Functional Verification of Dynamically Reconfigurable Systems (Version 2.3b)
Functional Verification ofDynamically Reconfigurable Systems(Version 2.3b)
Mr. Lingkan (George) Gong, Dr. Oliver Diessel The University of New South Wales, Australia
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Outline
• Objectives & Motivation• Challenges in Verifying Dynamically
Reconfigurable Systems (DRS)• Proposed Solution: The ReSim Library• Example Designs• Conclusions
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Objectives & Motivation
• Dynamically Reconfigurable Systems (DRS)– Improved flexibility– Better resource utilization
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Objectives & Motivation• Functional Verification
– Bottleneck of all hardware designs– Most costly bugs occur in system integration stage– DRS designs Involve activities that don’t exist in static designs (e.g., module swapping, … )
• It is essential to perform simulation-based verification of Dynamically Reconfigurable Systems (DRS)1 bug/6 lines of RTL code
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Objectives & Motivation
• “Partial Reconfiguration itself can not be simulated … ”– Xilinx UG702 (Partial Reconfiguration User Guide) – Can simulate Static + A; Static +B; But not the process of
swapping out A and swapping in B
• Objective– Support the simulation of the reconfiguration process– Support the simulation and functional verification of integrated
Dynamically Reconfigurable Systems (DRS)
Dynamically ReconfigurableSystem (Static part)
Dynamic part:Module A
Dynamic part: Module B
Dynamic part:Module B
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Objectives & Motivation
• Focus on detecting functional bugs– e.g. Cycle mismatch– Assuming there is no timing violation, no errors in the bitstream,
no glitch in the reconfiguration process
• Focus on systematic verification– Correctly verified sub-systems, while necessary, are not sufficient– Recommend to simulate the design BEFORE running it on the
target device
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Challenges in Verifying DRS
• DRS-specific design considerations
Configuration Port (e.g. ICAP)
Configuration Memory
FPGA Fabric
User Design
application data
Staticmodule
Reconfigurablemodule B
Reconfigurablemodule A
bitstream transfer
bitstream data
potential trafficcontention Reconfigurable
module A
Reconfigurablemodule B
swap modulesaccording to the bitstreams
Disable , isolate, restart
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Challenges in Verifying DRS• DRS-specific bugs
– BEFORE Reconfiguration Handshake errors (e.g., deadlock) Fail to save module state …
– DURING Reconfiguration: Errors in bitstreams (e.g., if a design “assemble” bitstreams at run time, bugs can be introduced to the
generated bitstreams) Errors in transferring bitstreams (e.g., traffic contention, encryption …) Fail to isolate the module undergoing reconfiguration …
– AFTER Reconfiguration Errors in resetting the module Errors in state restoration …
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Challenges in Verifying DRS
• Accuracy v.s. Productivity– Simulation accuracy Modeling the entire FPGA fabric
Configuration Port (e.g. ICAP)
Configuration Memory
FPGA Fabric
User Design
application data
Staticmodule
Reconfigurablemodule B
Reconfigurablemodule A
bitstream data
Models for the FPGA fabric not available Even if available, it is not efficient to simulate the FPGA
fabric (Low Productivity)
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Challenges in Verifying DRS
• Accuracy v.s. Productivity– Simulation productivity DO NOT model the FPGA fabric
User Design
application data
Staticmodule
Reconfigurablemodule B
Reconfigurablemodule A
Does not model bitstream traffic Assume zero or constant reconfiguration delay Does not trigger module swapping Does not model spurious module outputs Low accuracy
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Challenges in Verifying DRS
• Accuracy v.s. Productivity– Simulation accuracy DO model the FPGA fabric– Simulation productivity DO NOT model the FPGA fabric
• It is essential to balance “accuracy” & “productivity” when simulating partial reconfiguration
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ReSim
• Core idea– Model the fabric at such a level of detail that is just
enough for RTL simulation of DRS
User Design
application data
Staticmodule
configuration_port : artifact
extended_portal:artifact
Simulation-only Layer
Reconfigurablemodule B
Reconfigurablemodule A
Simulation-only bitstream (SimB)
bitstream transfer
potential trafficcontention
switch moduleaccording to SimB
Errorsource
During reconfiguration, inject errors to the static region
"activate" the new module if and only if the all bytes of the bitstream is successful transferred
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ReSim
• Simulation-only bitstreams (SimB)– Capture the essence of a real bitstream, but with reduced
size
DRS_DESIGN_TOP
RR0
RM0
RM1
RR1 RM0 RM1 RM2 RM3
RR2 RM0
Module B
Module A
* Use module ID, region ID as Frame Address
* Use ReSim-specificfields as configurationdata
bottom-half
top-half
con
figu
rati
on c
olu
mn
configuration row
RA
CA
FPGA_FLOOR_PLAN
CLB
s
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ReSim• Capabilities and Limitations
– BEFORE Reconfiguration Handshake errors (e.g., deadlock) Fail to save module state …
– DURING Reconfiguration: Errors in bitstreams (e.g., if a design “assemble” bitstreams at run time, bugs can be introduced to the
generated bitstreams) Errors in transferring bitstreams (e.g., traffic contention, encryption …) Fail to isolate the module undergoing reconfiguration …
– AFTER Reconfiguration Errors in resetting the module Errors in state restoration …
RED: Only on Target deviceBLUE: Only by ReSimGRAY: More Efficient by ReSim
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ReSim
• Capabilities and Limitations– ReSim assists in testing fabric-independent part of the
design– After simulation, test & debug fabric-dependent part on
the target device (using Chipscope)
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ReSim
• Reusability– Codegen: automatic generation of artifacts– OO: override the default behavior of artifacts
CodeGeneration
HDL (VHDL/Verilog) Simulation-only Layer
(SystemVerilog)HDL (VHDL/Verilog)
Implementation using FPGA tools
FunctionalSpecification
Simulation using the ReSim library
.tcl script (parameter description file)
namespace import ReSim::*
# interface signalscreate_portmap "my_if" "clk"add_port "my_if" "rst_n" inadd_port "my_if" "data" out 32…# module namescreate_region "my_region" "my_if" ...add_module "my_region" "Maximum"add_module "my_region" "Swap"…# target device familycreate_device "my_device" VIRTEX4
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Example Designs
• Example Designs– XDRS.QUICKSTART– XDRS.SINGLE– XDRS.MULTIPLE– FPCIe– State_Migration
• Derived from ReSim case studies– See “ReSim Case Studies” for more information on development progress,
bugs detected and lessons learned.
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Example Design: XDRS
• XDRS: a generic DRS computing platform– Similar to Erlangen Slot Machine, a general-purpose
reconfigurable compute engine (Bobda et al. FCCM 2005)
Reconfigurable Region
Reconfiguration Controller: ICAPI
Producer
ICAP
Memory Interface
Isolation
application data
bitstream
reqn, ackn
Off-chip Memory
Maximum/Reverse
XDRS Specification (Partial Reconfiguration part) ======================== BEFORE Reconfiguration. (Synchronization) - use a reqn/ackn signals to handshake - not acknowledge until RM is IDLE
DURING Reconfiguration. (Isolation) - use an isolation module to drive default values to the static region
AFTER Reconfiguration. (Initialization) - reset the newly-configured RM
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Example Design: XDRS
• Example simulation waveform– @t1: Sync, @t2: Transfer a bitstream, @t3: Extract
RRID/RMID@t4: Inject errors, @t5: Swap module, @t6: Reset
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Example Design: XDRS
• Example bug that was detected– Hold the "reset" signal of a module during reconfiguration
producer_ready
consumer_ready
consumer_error
Module A/BProducer
producer_ready
consumer_ready
consumer_error
Isola
tion
producer_ready
consumer_ready
consumer_error
x
x
0
0
0
1
Normal operation:Transfer is successful
Normal operation:Transfer is cancelled
Bug 1:Outputs not isolated during reconfiguration
Bug 2:Transfer is not cancelled during reconfiguration
Correct:Assert consumer_error during reconfiguration
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Example Design: XDRS
• Regression and coverage analysis
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Example Design: FPCIe• FPCIe
– Derived from Fast PCIe configuration (XAPP883) ~3500 lines of Verilog code + Coregen code (the PCIe endpoint)
– Integrate ReSim with the original testbench 150 lines of Tcl script (120 IO signals) 10 lines of Verilog code to instantiate the generated artifacts 110 lines of Verilog code to send SimBs to the DUT
ICAPPR Loader
Sw
itch
er
Reconfigurable Region:
PCIe core application: Bus-master DMA
PCIe endpoint
Shared datapath betweenapplication data &bitstream data
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Example Design: FPCIe
• Example simulation waveform– @t1: Transfer a bitstream over PCIe, @t2: Swap module,
@t3: Application logic starts operating
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Example Design: State_Migration
• State_Migration– Derived from Microprocessor Peripheral reconfiguration
(UG744)– Modified the hardware to use PPC440 & xps_icapi– Modified the software to save RM state via ICAP
The modified software is composed of fabric-independent C code and fabric-dependent C code
xps_mathxps_icapi
DDR2 Memory
ICAP
Reconfigurable Region: Adder / Maximum
xps_uart
To host PC
microprocessor bus:PLBv46
PPC440microprocessor
periodic application
xps_math driverxps_icapi driver
ReSimVirtex-5
Software
SW: fabric-independent partSW: V5 & ReSim
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Example Design: State_Migration
• Example simulation waveform– @t1: Read ICAP IDCODE (ReSim’s IDCODE=0x0c1b2011)
@t2: Issue GCAPTURE@t3: Configuration readback
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Conclusions
• Accuracy v.s. Productivityproductivity
accuracy
High-level modelinge.g. C/C++/SystemC
RTL simulatione.g. Verilog/VHDL
Timing simulation(i.e., simulating the design netlist)
Fabric-accurate simulation(i.e., simulating the FPGA fabric)
+
+
+x
x
ReChannelOSSS+R
VMUXDCS
x
+ Static designs
x DRS designs
xReSim
ReSim is - more productive than fabric-accurate simulation- more accurate than MUX-based simulation
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Conclusions
• It is essential to simulate partial reconfiguration– Activities such as bitstream traffic, triggering condition, state saving and restoration,
isolation of the reconfigurable region, …
• It is essential to balance accuracy & productivity– Modeling the FPGA fabric is not productive– MUX-based simulation is not accurate
• ReSim– Models the fabric at such a level of detail that is just enough for RTL simulation of DRS– A reusable simulation library
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More Infomation
• ReSim Home Page– http://code.google.com/p/resim-simulating-partial-reconfiguration/
• ReSim Document– ReSim User Guide– ReSim Case Studies
• Contact– Mr. Lingkan Gong,
http://code.google.com/p/resim-simulating-partial-reconfiguration/wiki/Lingkan_Gong – Dr. Oliver Diessel, http://www.cse.unsw.edu.au/~odiessel/
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Thank you