The DIALOG chip in the front-end electronics of the LHCb Muon Detector
Front End Electronics for the SPD of LHCb
description
Transcript of Front End Electronics for the SPD of LHCb
Università di Roma 'La Sapienza' 28-06-2002Universitat de Barcelona
Front End Electronics for the SPD of LHCb
Electronics in Experimental High Energy Physics
Xavier Vilasís-CardonaEnginyeria i Arquitectura La Salle
URL - Barcelona
The collaboration in Barcelona Universitat de
Barcelona Lluis Garrido Ricardo Graciani David Gascón Ernest Aguiló Miriam Calvo Sergio Gómez Sebastià Bota Atilà Herms Angel Diéguez Xavier Cano
Enginyeria i Arquitectura La Salle Rafael Ballabriga Sonia Luengo Mar Roselló Jordi Riera Xvc
Outlook
What is LHC ? What is LHCb ? The SPD Photomultipliers Very Front End Electronics The ASIC Front End Electronics
LHC : the future collider at CERN
Proton-Proton Starting 2007 Find the Higgs Find new physics 4 detectors
Alice Atlas CMS LHCb
LHC : some data Energy at collision: 7 TeV (1700 TeV for ions) Dipole field at 7 TeV: 8.3 T Bunch spacing: 7.5 m Bunch separation: 24.95 ns Particles per bunch: 10^11 Current: 0.56 A Luminosity: 10^34 cm^2 s Energy per beam up to 0.35 GJ Stored magnetic energy up to 1.29 GJ per
sector TOTAL STORED ENERGY = 11 GJ
LHCb A single-arm
spectrometer covering min ~15 mrad
(beam pipe and radiation)
max ~300 mrad (cost optimisation)
Precise measurements of CP violation B mesons CKM matrix elements
LHCb : what is CP violation ? CPT is an exact symmetry
• C charge conjugation• P parity• T time reversal
CP is almost exact CP violation explains matter-antimatter asymmetry
LHCb : the trigger
LHCb = 1000k channels : too much data The multi-level trigger chain
Logging rate 200 Hz (20 MB/s) 200 TB/year All LHC experiments: 5-8 PB/year
Input rate Latency B/s
Level 0 40 MHz 3.2 μs 1 TB/s
Level 1 1 MHz 256 μs 4 GB/s
Level 2 40 kHz 10 ms
Level 3 5 kHz 200 ms
SPD Scintillator Pad Detector In front of the
calorimeter Discriminates photons
from electrons at level 0 of trigger
spd ps ecal
spd ps ecal
e
SPD structure 6000 Scintillator Pads Helicoidal WLS optic fibers 64 channel PMT (Hamamatsu) 1 bit per channel at 40 MHz Synchronisation issues
Send bit to PreShower
Compare to a variable threshold
Radiation hard
SPD signal shape
Few photoelectrons Irregular signal shape Extended over 25 ns Non-uniform PMT gain
SPD electronics design
ASIC : why an ASIC ?
6000 channels : minimal area /ch Processing speed 40 MHz Power consumption < 2 W / 64 channels Analog Processing + Digital Control Signal range. 0 to 5 MIP (0 to 650 mV) Electronics resolution 5% of 1 MIP Dynamic range: 40 dB (7 bits)
ASIC Structure
AD
+
- 17 %
+
m bits
Serial interfacefor thresholdprograming
PMT chan. 1
PMT chan. 2
Vref (or DAC range)
Digital differentiallink to PS FE
AD
+
+ n/2 links
PMT chan. n
IntegratorSingle to
differential
SPD VFEcontrol unit
Track & Hold Pile-upsubtract Comparator
Digitalmultiplexer
- 17 %
- 17 %
- 17 %
Channel clocks
generation(CMOS & ECL)
Clock frequency
division by 2
Bunch crossing
clock (40 MHz) Clock delay(about 2 ns)
ECL internal CLock
(20 MHz)
- 17 %
ASIC characteristics
ProgrammableProgrammable Thresholds per sub-channel Subtraction: from 0% up to 40% of the signal T0: done externally with a delay unit (LAL design)
0.8 m AMS BiCMOS Technology Dual channel Fully differential Working at 3.3V SEU and SEL protection
Triple voting Guard rings
Review of ASIC runs RUN1 (Sep 2000)
Test separate blocs 1 full channel
RUN2 (Jun 2001) 4 full channels ECL vs CMOS output
RUN3 (Jan 2002) New tunnable substractor 1 full channel with digital control On-chip DAC to program thresholds
RUN4 (Sep 2002) 1 Complete processing channel Separate blocs + digital control Works at 3.3 V to reduce power consumption Fully differential preamplifier added before the integration
stage to meet PMT DC current limit requirements
ASIC : RUN 4 layout
ASIC : integrator
ASIC : Track and Hold
ASIC : substractor
ASIC : latched comparator
Offset ( (Output Zero Error): ): <OZE> = + 38.6 mV<OZE> = + 38.6 mV ioio = 70 mV r.m.s. = 70 mV r.m.s. Gain: <Vo/Vi> = 16.51 (for a<Vo/Vi> = 16.51 (for a typical input pulse) typical input pulse) ioio = = 0.091 0.091 r.m.s.r.m.s. (0,55%)(0,55%) Treset = = 5.5 ns (for 1 V output)5.5 ns (for 1 V output) Noise EEnono < 2 mV r.m.s < 2 mV r.m.s (Using scope, C.F. 6)(Using scope, C.F. 6)
EEnono < 1 mV r.m.s < 1 mV r.m.s (Discriminator sweep of thresholds)(Discriminator sweep of thresholds)
-1500
-1000
-500
0
500
1000
1500
-100,0 -90,0 -80,0 -70,0 -60,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0
Threshold [mV]
Histogram for threshold sw eepDifferentiated histogram
-66 -64 -62 -60 -58 -56 -54
0
200
400
600
800
1000
Data: Data1_B'Model: Gauss Chi^2= 2081.19889R^2 = 0.98682 y0 51.68159 ±23.05052xc -61.70164 ±0.05011w 1.62784 ±0.11995A 1609.67905±130.96337
Diff
eren
tial h
isto
gram
Threshold [mV]
B'
ASIC : integrator measurements 10 circuits
-2500,00
-2000,00
-1500,00
-1000,00
-500,00
0,00
500,00
1000,00
1500,00
2000,00
2500,00
-4000,00 -3000,00 -2000,00 -1000,00 0,00 1000,00 2000,00 3000,00 4000,00
Input Signal [mV]
Th
resh
old
[m
V]
R2B02
R2B04
R2B05
R2B06
R2B07
R2B08
R2B09
R2B01
R2B10
ASIC : integrator linearity
ASIC : programmable substractor
Gain of the controlable block of the subtractor = f(Vb) (10 samples)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
3,5 3,7 3,9 4,1 4,3 4,5 4,7 4,9
0102030405060708091001_soldat
VFE Board description
100 boards7x12 cmMultiplexed LVDS
Very Front End Board
Test beam boards
Sep 2001: RUN 2, 4 full channels/ 4-layer board•ECL vs CMOS output•Clock signal distribution•Power Supply distribution
June 2002: RUN 2, 4 full channels / 4-layer board•Improvements in board design•Signals distribution
June 2002: RUN 3, 1 full channel and digital control/ 6-layer board
•Digital signal distribution vs analog signal distribution•Noise effect vs number of layers
Front End Board
Control Unit : •Bus Bridge•Programmable Delays
1 Control Unit every 4 VFE Boards5 Control Units in a Front End Board6 Front End Boards
Conclusions