Front-end CMOS Electronics for Monolithic Integration with CMUT Arrays: Circuit Design and

Initial Experimental Results

Gokce Gurun1, Muhammad Shakeel Qureshi1, Mujdat Balantekin1, Rasim Guldiken2, Jaime Zahorian1, Sheng-Yu Peng,1 Arindam Basu1, Mustafa Karaman3, Paul Hasler1, Levent Degertekin1,2

1School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, 2School of Mechanical

Engineering Georgia Institute of Technology, Atlanta, GA, 3Isik University, Istanbul, Turkey

Abstract—This paper discusses design of CMOS-ASICs for monolithic integration of CMUT arrays by post-CMOS fabrication. We describe design strategies for monolithic integration and demonstrate the advantages of CMUT-on-CMOS approach. On the same wafer, separate sets of IC cells are designed to interface different types of CMUT arrays for IVUS and ICE applications. Circuit topologies include resistive feedback transimpedance amplifiers on the receiver side, along with multiplexers and buffers. Gains and bandwidths of receiving amplifiers are optimized separately to fit different array specifications such as number of elements, element size and operation bandwidth. To drive CMUTs a high voltage pulser array is designed in the same 3.3V unmodified CMOS technology by combining existing technological layers in an unconventional way. CMUT arrays are then built on top of the custom made 8” wafer containing these circuits fabricated in a 0.35µm standard CMOS process. We present initial characterization of the CMOS electronics and pulse-echo measurements obtained post-CMOS fabricated CMUT elements.

Keywords- Monolithic, integration, CMUTs, electronics, input referred noise, transimpedance, capacitive interface circuit

I. INTRODUCTION

To meet the demands of medical ultrasound imaging using high density arrays with CMUT technology, specialized integrated circuits should be custom designed. Because the parasitic interconnect capacitance is a significant factor degrading the SNR, monolithic integration emerges as a viable option. Silicon-based CMUTs enable different array structures and are especially suitable for various levels of electronics integration. Integrated electronics reduces cable count, mitigates parasitic effects and lowers overall cost, and hence is a key factor for successful implementation of catheter-based imaging arrays.

Single-chip or hybrid electronics integration is required for arrays with small element size. Hybrid integration of CMUT array and CMOS electronics through flip-chip bonding is demonstrated in [1]. Approaches to single-chip integration of CMOS and CMUT devices include interleaved CMOS-MEMS integration, where CMUTs are fabricated as an intermediate step in CMOS process flow [2, 3], and CMOS before MEMS

where CMUTs are fabricated on CMOS electronics [4, 5].

In this paper we present CMOS design aspects for CMUT-on-CMOS integration. We designed the electronics using the TSMC 0.35μm two-polysilicon four-metal CMOS process for 8” wafers. Each wafer contains many chips of size 2 cm × 2cm (reticle) containing many smaller IC cells (Fig. 1). We optimized integrated cells with significant design effort to meet the specifications for three different arrays designed for IVUS and ICE applications. The number of receive and transmit elements, operation bandwidth and calculated device capacitances of CMUT arrays used in these applications are presented in Table 1. In this paper we focus our discussion to one particular integrated cell designed for dual ring array to explain the design process.

This research is funded by NIH- NHLBI (Grant No: 1 R01 HL082811-01) and Boston Scientific Corp.

TABLE I. SUMMARY OF TYPICAL CMUT PARAMETERS

Dual Ring Array

Annular Array

Linear Array

# of Elements 32 RX – 24 TX 64 RX – 48 TX

8 RX 16 RX

64 RX

Operation Freq 15 - 25MHz 10 - 50MHz 3-13MHz Element Area 70 μm × 70 μm 100000 μm2 172000 μm2

RCMUT ~1MΩ 53kΩ 31.25kΩ

CCMUT 145fF 3pF 5.1pF

Fig.1. Picture of the 8” CMOS Wafer (left), layout and picture of the reticle (right)

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Digital Object Identifier: 10.1109/ULTSYM.2008.0096

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II. ELECTRONIC CELL DESIGN

Our previous dual-ring imaging study [6] included a 32 RX – 24 TX element CMUT array and 4 IC chips surrounding the array, along with a glass layer to help routing. CMUT arrays and IC chips were placed on glass interface chip which was then placed on a 64 pin chip carrier for testing. Such configuration requires more than 100 wirebonds for connections which is quite prone to errors. Hence, CMUT-on-CMOS approach is also a remedy for that as it eliminates all those wirebonds.

We designed and fabricated an IC chip to test monolithic implementation of a dual ring array for forward-looking IVUS imaging. A micrograph of this IC is shown in Fig. 2. The chip has a die-size of 2 mm × 2 mm. It includes all the components of the imaging device, such as transmitters, receivers and control logic. It was optimized to interface a dual-ring array with 32 receive and 24 transmit elements. The chip includes 4 sets of pulser arrays, each containing 6 pulsers. Those pulser arrays are connected to 24 CMUT Tx element connections. There are 4 sets of receiver arrays. Each receiver array includes 8 transimpedance amplifiers, one 8×1 multiplexer and a buffer to drive cable and pad capacitances. Chip has total of 4 parallel outputs having one from each set of receiver arrays. Digital control block is designed to synchronize transmit and receive element operations in the dual-ring array. It includes an 8 bit counter that generates control bits for pulser and receiver arrays.

III. RECEIVER DESIGN

A. Transistor Feedback TIA Design

A resistive feedback transimpedance amplifier is a popular topology as a front-end receiver for low-noise detection. Shunt-shunt feedback presents low input impedance to the high-impedance CMUT, thereby alleviating the effects of parasitic

capacitances and preventing significant signal loss. Hence we designed a resistive feedback transimpedance amplifier. Although differential ended structures are good for common-mode noise rejection, unused differential input adds extra input referred noise. Therefore we implemented the core amplifier with a single ended common source amplifier to optimize noise performance (Fig. 3). We used a cascoded structure to get a higher gain from the core amplifier and to get a higher gain-bandwidth for the closed loop transimpedance amplifier. Layout of the TIA fits in 70×140 μm2 which is equal to the total area of one transmit and one receive CMUT elements. We implemented the feedback resistor using an NMOS transistor in triode region. Effective resistance value of the triode region transistor is given by:

( )( )STCTRLox

FVVVL

WCR

−−=

κμ1 (1)

Use of a transistor operating in triode region is advantageous because implementing high resistance values on chip with polysilicon requires high area usage and accompanies large parasitic feedback capacitances. Also, effective resistance of that transistor can be tuned with the control voltage which in turn can control the gain and bandwidth. Additionally, if needed, this feature can also be used for time gain control.

We tested the frequency response of our designed transistor feedback TIA using 8753ES Agilent Network Analyzer. We measured a transimpedance gain of up to 80 dBΩ that corresponds to 10 kΩ transimpedance gain with 20-MHz bandwidth. Due to the test setup, effective input capacitance includes pad capacitances and wirebond capacitances on the range of 5pF. Hence, for CMUT-on-CMOS case where parasitic capacitances are minimum, bandwidth of this TIA can be tuned for higher values in the 50-60MHz range suitable for the high frequency annular array (Table 1).

B. Low Noise Transimpedance Amplifier Design

Optimum transducer sensitivity in terms of maximizing signal-to-noise ratio (SNR) requires designing the receiving electronics that will introduce the lowest possible noise for given bandwidth and element size specifications.

(a) (b)

Fig.3. (a) Resistor Feedback and Transistor Feedback TIA (b) Core Amplifier

Fig.2. Micrograph of the Dual Ring Imaging IC

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Overall system noise with all the noise sources including the CMUT element and the receiving TIA is shown in Fig. 5. Note that CMUT element is represented with an AC equivalent resistor and a capacitor value. In terms of noise, that resistor value contributes a thermal noise to the overall noise expression and hence should be taken into consideration. Input referred current noise is given by:

2,

2,22

,2

, // CMUTRfCMUT

ampeqfampeqtoteq i

RR

viii +++= (2)

Here ieq,amp2 & veq,amp

2 are the input equivalent current and voltage noise sources of the core amplifier. if

2 and iR,CMUT2 are

the representations of the feedback resistance noise and CMUT related thermal noise respectively. In that equation, for a typical TIA design with bandwidth around tens of MHz range and typical values of RF and RCMUT, contribution of veq,amp

2 can be neglected. Than the total equivalent input current noise spectrum is given as:

CMUTfm

dParCMUTampintoteq

R

kT

R

kT

g

iCCCi

44)(

2

22

,22

, ++++= ω (3)

It is important to notice that the overall noise includes the CMUT thermal noise. Receiver design optimization helps until the point where CMUT noise starts to dominate. Especially for small CMUT elements with very high equivalent resistance, and very low capacitance value, noise due to CMUT is very low. For those elements good noise performance on the electronics part helps to increase SNR considerably. Inspecting the above noise expression, it can be seen that parasitic capacitance values that are much higher than the CMUT capacitance degrades the noise performance significantly. For those cases, reducing the parasitic capacitance helps reducing the noise level. As mentioned earlier, parasitic effects are mostly due to the wire-bonding and pad capacitances and can be eliminated by monolithic integration. Also, for better noise performance one should increase RF to reduce the additional thermal noise generated by the feedback resistor. Increasing RF value also introduces higher sensitivity. However, there is an upper limit for value of RF, as bandwidth is inversely proportional to that value and the total capacitance

at the input. For CMUT-on-CMOS case the parasitic input capacitance is much smaller and thus Rf value can be designed with values much higher than that is possible with wirebonding.

IV. PULSER DESIGN

Traditionally voltage pulses are provided off-chip for ultrasound systems. However, as the monolithic integration of CMUT arrays and the electronics is more desirable, various techniques of generating high voltage pulses on chip have been investigated. To generate high voltage pulses BCD (Bipolar/CMOS/DMOS) is a suitable technology [7]. Although high voltage devices in those technologies show good performance, fabrication in those is very complex and costly. Another approach to get high voltage devices is to modify the layout of regular devices from a low voltage process to get low cost high voltage elements [8-10]. This can only be achieved by carefully considering the underlying breakdown mechanisms in MOS transistors. We designed a high voltage pulser based on “Extended Drain NMOS” design which is compatible with the fabrication of low voltage devices because it doesn’t require any additional fabrication steps. Layout of traditional NMOS and layout of designed EDNMOS can be seen in Fig. 6.

We tested designed high voltage NMOS device and observed a breakdown voltage of 35 V. Note that breakdown voltage of regular devices in that technology is less than 10 volts. To drive CMUT elements a high voltage pulser array which uses the pulser in Fig. 7 and the mentioned 35V breakdown NMOS is used. Fig. 7 shows a 2MHz and 25V pulse obtained from the pulser element driving a total cable and scope capacitance of 8pF. When driving a small capacitance CMUT element, this pulser is expected to generate wideband pulses. For example, with a 200fF dual ring CMUT array element, the pulse bandwidth would be 80MHz.

V. PULSE ECHO RESULTS FROM MONOLOTIC CMUT-CMOS DEVICE

For initial testing, we performed pulse-echo measurements with a CMUT array on an IC consisting of transimpedance amplifiers, multiplexers and buffers to drive 50 Ω and 12 pF cables. The CMUT test array consists of 5 RX and 6 TX elements fabricated on top of this particular cell (Fig. 8). The electronics shows no degradation after CMUT fabrication.

Fig.5. Schematic of a CMUT element together with the TIA front end including all the noise sources.

Fig.4. Transimpedance Gain Characterization

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The CMUTs are biased with 20-V and an external 10-Vpp pulse in a 5-mm deep oil bath is applied to one of the transmitters. With transimpedance gain of 500 kΩ and 3-MHz bandwidth, an echo signal of 28-dB SNR is obtained without any averaging. Although the ultimate CMUTs we design are for higher frequency operation this test is limited by the low TIA bandwidth that stems from an issue with the fabricated on-chip resistors. We resolved this resistor problem in the new set of wafers and demonstrated higher frequency operation as shown in Fig. 4.

VI. CONCLUSION

We discussed design and implementation of custom ASICs including special interconnect structures for post-CMOS CMUT fabrication, low-noise, and high-gain receiver arrays in 0.35μm standard CMOS process. By combining existing technological layers in an unconventional way in the same low voltage process, high voltage devices with breakdown voltages up to 35 V were achieved. Initial tests demonstrated successful operation of the monolithic CMUT-on-CMOS arrays. We also discussed advantages of CMUT-on-CMOS approach in detail in terms of receive sensitivity and noise.

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[4] R.A. Noble et al, “A cost-effective & manufacturable route to the fabrication of high-density 2D cMUT arrays & signal conditioning electronics on the same silicon substrate”, Proc. IEEE, Ultras. Sym, Vol. 2, pp. 941-944, 2001.

[5] Daft, C.; Calmes, S.; da Graca, D.; Patel, K.; Wagner, P.; Ladabaum, I., "Microfabricated ultrasonic transducers monolithically integrated with high voltage electronics," Ultrasonics Symposium, 2004 IEEE , vol.1, no., pp. 493-496 Vol.1, 23-27 Aug. 2004

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Fig.7. Pulser Element (left) and pulser output voltage with low voltage input pulse (right)

Fig.6. Regular NMOS structure (top) and extended Drain NMOS structure (bottom)

Fig.8. CMUT elements on CMOS (top), Pulse-Echo response (bottom)

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