Frequency planning part 1 - TI.com
Transcript of Frequency planning part 1 - TI.com
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Frequency planning part 1 TI Precision Labs – Clock and timing system design considerations
Presented by Rob Rodrigues
Prepared by Hao Zheng
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Clock generator overview
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.
.
....
PLL1
PLL2
D0
M
U
X
Reference
Input D1
D2
D3_4
Output 0
Output 1
Output 2
Output 3
Output 4
1/N
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
25MHz 156.25MHz
Frequency calculation
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R = 1
4.8 ~ 5.4 GHz
D = 31,
32,
33,
34
5000MHz
N = 200
Locked
25MHz
32,
156.25MHz
4800 / 156.25 = 30.72
5400 / 156.25 = 34.56
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Frequency calculation (cont.)
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
25MHz 156.25MHz
R = 1
25MHz
4.8 ~ 5.4 GHz
D = 31,
32,
33,
34 5156.25MHz
N + NUM/DEN = 206 + 1/4
Locked
33,
156.25MHz
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One PLL, two output frequencies
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N = 200
R DividerReference Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s) 1/D0
1/D1
4.8 ~ 5.4 GHz
25 MHz R = 1
25MHz
2500MHz
5000MHz
7500MHz . . .
100MHz
156.25MHz
D0 = 50
D1 = 32
5000MHz
100MHz
156.25MHz
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R DividerReference Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s) 1/D0
1/D1
48MHz 48MHz
One PLL, two output frequencies (cont.)
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2.4 ~ 2.8 GHz
24 MHz
32.768kHz
R = 1
N = 200
24MHz
2400MHz D0 = 50
D1 = 73242
2.56 ppm
0 ppm
D1 and D2
must be
divisible by 4,
5, or 6
32.768kHz
1/P
Prescaler/4, /5, /6
1/CH
Channel divider
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To find more clocks and timing technical resources and search products, visit ti.com/clocks
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Short Quiz
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1. True or False:
The relationship between fVCO (VCO frequency), D (output divider value) and fout (output
frequency) is fout = fVCO * D
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Short Quiz
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1. True or False:
The relationship between fVCO (VCO frequency), D (output divider value) and fout (output
frequency) is fout = fVCO * D
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Short Quiz
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2. Choose one:
The relationship between fPD (phase detector frequency), N (N divider value), NUM (numerator of
fractional divider), DEN (denominator of fractional divider) and fVCO for fractional PLL is
(a) fVCO = fPD * (N - NUM/DEN) (b) fVCO = fPD * (N + NUM/DEN) (c) fVCO = fPD / (1/N + NUM/DEN)
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Short Quiz
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2. Choose one:
The relationship between fPD (phase detector frequency), N (N divider value), NUM (numerator of
fractional divider), DEN (denominator of fractional divider) and fVCO for fractional PLL is
(a) fVCO = fPD * (N - NUM/DEN) (b) fVCO = fPD * (N + NUM/DEN) (c) fVCO = fPD / (1/N + NUM/DEN)
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Short Quiz
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3. True or False:
There is only one combination of reference input frequency, phase detector frequency and divider
values that can generate the desired output frequency fout,
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Short Quiz
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3. True or False:
There is only one combination of reference input frequency, phase detector frequency and divider
values that can generate the desired output frequency fout,
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Short Quiz
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4. Choose all that apply:
Which constraints determine the relationship between fVCO, fout1 (frequency of output 1), fout2
(frequency of output 2) fVCO_min and fVCO_max for generating 0ppm outputs?
a) fVCO is common multiple of fout1 and fout2
b) fVCO/N = integer
c) fVCO_min < fVCO < fVCO_max
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Short Quiz
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4. Choose all that apply:
Which constraints determine the relationship between fVCO, fout1 (frequency of output 1), fout2
(frequency of output 2) fVCO_min and fVCO_max for generating 0ppm outputs?
a) fVCO is common multiple of fout1 and fout2
b) fVCO/N = integer
c) fVCO_min < fVCO < fVCO_max
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