Fractional-Order Differentiators and Integratorswith Reduced Circuit Complexity

Panagiotis Bertsias*, Leila Safarit , Shahram Minaei+, Ahmed Elwakil§ and Costas Psychalinos**Electronics Laboratory, Department of Physics, University of Patras, 26504 Rio Patras, Greece ({panosber; cpsychal}@upatras.gr)

tIndependent Researcher, Tehran, Iran (leilasafari@yahoo.com)+Department of Electronics and Communications Engineering, Dogus University, Kadikoy, 34722 Istanbul, Turkey (sminaei@dogus.edu.tr)

§Department of Electrical and Computer Engineering, University of Sharjah, ShaIjah, P.O. 27272, Emirates (elwakil@ieee.org)

Abstract-Fractional-order differentiation and integration stagesare essential building blocks for performing signal processingusing fractional-order calculus. One important characteristic offractional-order differentiators/integrators is the circuit complex­ity of the integer-order topologies required for approximatingsuch stages. The already introduced schemes suffer from this ob­stacle, making the derived structures power demanding. A simplestructure, constructed from 21 MOS transistors and 3 dc currentsources, which is capable of approximating fractional-orderdifferentiators and integrators is presented in this paper. Otherattractive benefits of the proposed scheme are the electronictuning capability as well as the capability for implementationin monolithic form. The evaluation of its behavior is performedusing Cadence and the Design Kit provided by the AustrianMikro Systems (AMS) 0.35p.m CMOS process.

Index Terms-Fractional-order circuits, fractional-order in­tegrators, fractional-order differentiators, CMOS analog inte­grated circuits.

I. INTRODUCTION

As fractional-order capacitors are not yet commerciallyavailable [1], the implementation of fractional-order differen­tiation/integration stages can be performed either: a) throughthe substitution of fractional-order capacitors by appropriatelyconfigured RC networks [2], [3], [4], or b) through the imple­mentation of the integer-order transfer function derived by ap­plying an approximation of the integro-differential Laplacianoperator (sO!) using an appropriate rational transfer function[5], [6], [7]. The first approach suffers from absence of theon-the-f1y adjustment of the characteristics of the approxi­mated dilferentiator/integrator, in the sense that the wholecircuit must be re-designed in order to change the frequencycharacteristics of the stage. Voltage-mode implementations ofthe second approach have been reported in the literature, indiscrete IC component form mainly using Operational Ampli­fiers (op-amps) or Current Feedback Operational Amplifiers(CFOAs) as active elements, and in monolithic form usingOperational Transconductance Amplifiers (OTAs) as activeelements [8]. The employment of OTAs offers the advantages

This work is supported by the General Secretariat for Research andTechnology (GSRT) and the Hellenic Foundation for Research and Innovation(HFRl).This article is based upon work from COST Action CA15225, a net­work supported by COST (European Cooperation in Science and Technology).

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of the electronic tuning adjustment of the frequency character­istics of the differentiator/integrator as well as the capability ofimplementation in monolithic form. Another already reportedimplementation is based on the concept of current-mode signalprocessing and, therefore, current-mirrors (CMs) were thebasic building blocks for implementing the desired transferfunction [9]. These topologies also offer the benefits of theOTA-C implementations thanks to the employment of thesmall-signal parameter of the MOS transistor for realizing therequired time-constants. The price paid for the aforementionedachievements is that both types of implementations offerincreased circuit complexity. In terms of MOS transistor count,that makes them a non-attractive choice in applications wherelow-power consumption is critical for the performance of thesystem, such as bio-impedance portable devices [10].In order to overcome this obstacle, a novel topology is pre­sented where the number of the required MOS transistors hasbeen reduced in comparison with the corresponding alreadypublished structures and, simultaneously, it still oflers thebenefits of electronic tuning of the characteristics of thediflerentiator/integrator and the capability for silicon imple­mentation.This paper is organized as follows: the presentation of thefractional-order topology, along with the corresponding designequations, are given in Section II, while the behavior of theproposed implementation is evaluated in Section III using theAnalog Design Environment of the Cadence software and theDesign Kit provided by the AMS 0.35p.m CMOS process.

II. PROPOSED FRACTIONAL-ORDERDlFFERENTlATOR/INTEGRATOR TOPOLOGY

The transfer function of a fractional-order differentia­tion/integration stage is given as:

(1)

where for 0 < a < 1 corresponds to a differentiator, whilefor -1 < a < 0 the transfer function of an integrator isderived. Also, the time-constant (T) is related to the unity­gain frequency (wo ) of the stage according to the formula:Wo = l/T. The magnitude frequency response, derived from(1), is given by the expression: H(w) = (w/wot, while the

Fig. I. Current-mode fractional-order differentiator/integrator [9].

(6)

t o1G 9=19=2

o C 1 C 2 (3)iin 82 + 29=1 8 + 9=19=2 '

C 1 C 1 C 2

i 02G 29m 1 81 C 1 (4)

tin 82 + 29=1 8 + 9=19=2 'C 1 C 1 C 2

t 03 G 28 2(5)

iin 82 + 29=1 8 + 9=19=2 'C 1 C 1 C 2

1,2) and Gj (j = 0,1,2) are bias currents and the scalingfactors, respectively. A number of 39 MOS transistors and 3 dccurrent sources are required for its full transistor level imple­mentation. In addition, the dc power dissipation of the circuitis equal to [(5 + G 2 )10 + (7 + Gdlo1 + (6 + G o )102] VDD .The proposed fractional-order differentiator/integrator topol­ogy is depicted, in simplified form, in Fig. 2. Consideringthe small-signal equivalent circuits of the MOS transistorswithout their internal parasitic capacitances, and assuming thatMp I-Mp2 are identical transistors, it is derived after a routinealgebraic analysis that

with 9m1 and 9m2 being the small-signal transconductancesof MOS transistors Mp 1 and Mn2, respectively.Owing to the fact that the output current (i out ) is formed as:

;0'" i out = i o1 + i 02 + i 03, then according to (3)-(5), the realizedtransfer function takes the following form

. G 8 2 + 2G 1 8 + ~H (8) == tout = 2 T1 T1 T2

in 8 2 + 2 8 + _1_~ 71 7172

phase response L1i..(w) = em/2 is constant over the frequency.The transfer function in (1) can be approximated around the

Fig. 2. Simplified circuitry of the proposed fractional-order differentia­tor/integrator.

7 ( 8 - 2a2

)72 ="2 a2 + 3a + 2 (7)

Fig. 3. Full circuitry of the proposed fractional-order differentiator/integrator.

unity-gain frequency using the Continued Fraction Expansion(CFE) tool [11]; for this purpose, the second-order expressionis an efficient choice in terms of circuit complexity, magnitudeand phase accuracy. The derived integer-order transfer functionis given by (2)

(2)

An implementation of the transfer function in (2) has beenintroduced in [9] and it is recalled in Fig. 1, where 10 , 10i (i =

where the time-constants in (6) are defined as: 71 = Cd9m1and 72 = C2 /9m2, The calculation of the time-constants7i (i = 1, 2) and scaling factors G j (j = 0, 1, 2) is performedby equating the corresponding coefficients of the transferfunctions in (2) and (6). Thus, the derived design equationsare summarized in (7)-(8)

_ (a2

- 3a + 2)71 - 27 8 _ 2a2 '

G _ a 2 + 3a + 2 G _ a 2 - 3a + 2 (8)2 - a 2 _ 3a + 2 ' G 1 = 1, 0 - a 2 + 3a + 2

The complete circuitry of the fractional-order differentia­tor/integrator is depicted in Fig. 3, where it is readily obtained

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The obtained frequency responses for both differentiator and

TABLE [ASPECT RATIOS OF THE MOS TRANSISTORS IN FIG. 3.

IDifferentiatod

105

Freq (HZ)

(a)

105

Freq (HZ)

(b)

---=

" ......

20

115 '.

10

-15

-10

-60~~orl-80

104

CD 5~c 0'0;

CJ -5

1Bl (/-iA) 6.5 (5) 15 (3.3) 44(2.1)1B2 (/-iA) 40 (7.2) 60 (4) 110( 1.7)

G2 2.5(0.4) 5(0.2) 11.8(0.09)Gl 1(1) 1(1) 1(1)Go 0.4(2.5) 0.2(5) 0.09(11.8)

Fig. 4. Frequency responses of the circuit in Fig. 3 (a) gain, and (b) phase.

I Parameter I a - 0 3(-03) I a - 0 5(-05) I a - 0 7(-07) I

TABLE IIVALUES OF DC BIAS CURRENTS (lB3 = 50/-iA) AND THEIR SCALING

FACTORS FOR THE TOPOLOGY IN FIG. 3.

80~~~,,--~~~~------~

~------60

40

g> 20 - - approximation"'0 _0' = 0.3 simulation--; 0 -a =0.5 simulation~ -a = 0.7 simulationii: -20" -",--"",__'---_~;:;~~~~:.~~.=-:-'

integrator are given by the plots in Fig. 4, where an error lessthan 10% in phase is achieved in the range (12kHz, 550kHz)for the differentiator and (12kHz, 800kHz) for the inte­grator. The time-domain behavior of the proposed topol­ogy has been evaluated through its stimulation by a si­nusoidal signal with 100kHz frequency and 1f.lA ampli­tude. The derived output waveforms, depicted in Fig. 5confirm their correct operation. The electronic tuning ca­pability of the proposed topology is demonstrated by theplots in Fig. 6, where the gain responses of the differentia­tor for (JEl, I B2 )={(3.8, 15),(15,60),(60, 240)}f.lA and ofthe integrator for (JEl, IB2)= {(0.8, 1),(3.3,4),(13, 16)}f.lA,are given. The corresponding unity-gain frequencies were{42,100, 220}kHz for the differentiator, while the corre­sponding values for the integrator were {40, 100, 207}kHz.The behavior of the proposed topology in terms of the effectof MOS transistors parameter mismatching and process pa-

I Aspect Ratio (/-im! /-im)TransistorMn2, Mn3, Mn6, Mn8 10/2

Mn5 2/2Mp1, Mp2 20/2

Mp3, Mp5, Mp9 10/2

III. SIMULATION RESULTSThe behavior of the proposed fractional-order differentia­

tor/integrator was evaluated using the Cadence software withthe Design Kit provided by the AMS 0.35f.lm CMOS process.For this purpose differentiators and integrators with unity-gainfrequency fa = 100kHz and orders a = {±0.3, ±0.5, ±0.7}will be realized. The power supply voltages for the topology inFig. 3 were chosen as VDD = - Vss = 1.5V, and VB = 0.6V,while IB3 = 50f.lA. The capacitor values for the differentiatorwere G1 = 40pF and G2 = 500pF , and for the integratorwere G1 = 80pF and G2 = 600pF. The MOS transistoraspect ratios are provided in Table I, while in Table II thevalues of the bias currents I El and I B2 as well as theirscaling factors, for the differentiator and integrator (betweenparentheses), are summarized.

that the number of the required MOS transistors and dc currentsources is equal to 21 and 3, respectively. Therefore the num­ber of MOS transistors is almost halved in comparison with thetopology in Fig. I, without increasing the number of currentsources. The dc power dissipation of the topology in Fig. 3 isequal to [(2 + G 2)IB3 + (4 + 2G 1)IEl + (2 + G o)IB2 ]VDD .

Assuming that IB3 = la, IBI = 101 and IB2 = 102 ,the power dissipation is lower than that required for thecircuit in Fig. I. Therefore, the proposed circuit offers thebenefits of reduced circuit complexity and, also, power dis­sipation. Considering that the MOS transistors operate inthe strong inversion region, the transconductances gml andgm2 are expressed as: gml = J2Kp (WjL)Mpl IEl and

gm2 = J2Kn(WjL)Mn2IB2, where K p and K n are thetransconductance factors of Mp 1 and Mn2, respectively, andI El , I B2 are the corresponding bias currents.Therefore, thetime-constants are electronically controllable through the dcbias currents giving the attractive feature of the adjustablecharacteristics of the differentiator/integrator. It must be alsomentioned at this point that the topology in Fig. 3 has potentialfor operation at very high frequencies and this is originatedfrom the fact that it could be easily become capacitor-less byomitting the passive capacitors G1 and G2 and consideringonly the gate-source capacitance (Ggs ) of transistors Mpl andMn2. This was also the concept of the topology introducedin [12], where G1 = 2Ggs ,Mpl and G2 = 2Ggs ,Mn2, and,consequently, the topology in Fig. 3 is a modified version ofthat topology.

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1.5 .---------r-----.-----,---------,------,--------,

Differentiator'.

0.5

-0.5

-1

25.0

VI 20.0QIQ.E 15.0'"Vl

'010.0oz 5.0

0.0

Mean = 22.19617mStd Dev = 220.964m

I Iii i I I I I I

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.1Gain (dB)

(a)

IV. CONCLUSION

45I I

44I I I

43

Mean =41.2813Std Dev = 1.02714

41 42Phase (deg)(b)

4039I I

38

20.0

0.0

:D 15.0Q.E~ 10.0'0

~ 5.0

REFERENCES

[I] A. Agambayev, S. Patole, M. Farhat, A. Elwakil, H. Bagci, and K. N.Salama, "Ferroelectric fractional-order capacitors," ChemElectroChem,2017.

[2] G. Carlson and C. Halijak, "Approximation of fractional capacitors(l/s)l/n by a regular Newton process," IEEE Transactions on CircuitTheory, vol. I I, no. 2, pp. 210-213, 1964.

[3] A. G. Radwan, A. M. Soliman, and A. S. Elwakil, "First-order filtersgeneralized to the fractional domain," Journal of Circuits, Systems, andComputers, vol. 17, no. 01, pp. 55-66,2008.

[4] J. Valsa and J. Vlach, "RC models of a constant phase element,"International Journal of Circuit Theory and Applications, vol. 41, no. I,pp. 59-67, 2013.

[5] T. J. Freeborn, B. Maundy, and A. S. Elwakil, "Field programmableanalogue array implementation of fractional step filters," lET Circuits,Devices & Systems, vol. 4, no. 6, pp. 514-524, 2010.

[6] G. Tsirimokou and C. Psychalinos, "Ultra-low voltage fractional-orderdifferentiator and integrator topologies: an application for handling noisyecgs," Analog Integrated Circuits and Signal Processing, vol. 81, no. 2,pp. 393--405, 2014.

[7] J. Jerabek, R. Sotner, J. Dvorak, J. Polak, D. Kubanek, N. Herencsar,and J. Koton, "Reconfigurable fractional-order filter with electronicallycontrollable slope of attenuation, pole frequency and type of approxi­mation," Journal of Circuits, Systems and Computers, vol. 26, no. 10,p. 1750157,2017.

[8] G. Tsirimokou, C. Psychalinos, A. S. Elwakil, and K. N. Salama,"Electronically tunable fully integrated fractional-order resonator," IEEETransactions on Circuits and Systems II: Express Briefs, 2017.

[9] P. Bertsias, C. Psychalinos, A. G. Radwan, and A. S. Elwakil, "High­frequency capacitorless fractional-order CPE and FI emulator," Circuits,Systems, and Signal Processing, pp. 1-20, 10 2017.

[10] O. G. Martinsen and S. Grimnes, Bioimpedance and BioelectricityBasics. Academic Press, 2014.

[II] B. Krishna, "Studies on fractional order differentiators and integrators:A survey," Signal Processing, vol. 91, no. 3, pp. 386--426,2011.

[12] L. Safari, S. Minaei, and B. Metin, "A low power current controllablesingle-input three-output current-mode filter using mos transistors only,"AEU-International Journal of Electronics and Communications, vol. 68,no. 12, pp. 1205-1213,2014.

Fig. 7. Monte-Carlo statistical plots for the differentiator (0: = 0.5) topology(a) gain, and (b) phase at unity-gain frequency.

807560 65 70time (l1s)

55

20

15 IIntegrator!

10

co 5:E!-c 0

'(ij<.9 -5

-10

-15

-20104 105

Freq (Hz)

-1.5 '-----_-----'-__---'---__-L-_~ __----"--_------.J

50

Fig. 5. Time-domain output waveforms for the fractional-order differentia­torlintegrator (0: = ±0.5) stimulated by a (100kHz, 1/J,A) input current.

Fig. 6. Demonstration of the electronic tuning capability of the proposedfractional-order differentiator/integrator (0: = ±0.5).

A novel simple realization of fractional-order differen­tiator/integrator is presented in this paper. It preserves theattractive feature of electronic adjustment of its characteris­tics and, simultaneously, the number of MOS transistors isalmost halved in comparison with the corresponding alreadypublished implementation. In addition, the simulated sensi­tivity characteristics prove the robustness of the proposedtopology. Therefore, it could be employed for realizing high­performance fractional-order systems, including fractional­order element emulators and filters [8].

rameters variations has been evaluated using the Monte-Carloanalysis tool, for N = 100 runs. The obtained statistical plotsabout the gain and phase responses of the differentiator, witha = 0.5, at 100kHz are demonstrated in Fig. 7. The standarddeviation of the gain is about 0.2dB and for the phase the valueis 1°. The corresponding results in the case of integrator were0.2dB and 2°, respectively. Therefore, the proposed topologyoffers reasonable sensitivity characteristics.

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