PowerPoint Presentation

Finite State Machines

FSM in generalA state machine is an effective way to implement control functions.A state machine works in two phases.The new state is calculatedThe new state is sampled into a registerA basic form of state machine is a sequential circuit in which the next state and the circuit outputs depend on the current state and the inputs. 2Basic of a Finite State MachineCombinational LogicState registersCurrent stateNext stateClockinputsoutputsDQIn the picture we identify two blocks: combinational logic block and state registers.3How many statements? - Structure and readabilityTwo statements: It will be easier to detect possible errors of the VHDL model in the waveform if one has access to the intermediate NEXT_STATE. So the time and location where the error occurs for the first time can be determined exactly and with that the source of the error. The two statements version is therefore the better version for debugging.One statement: But one is normally interested in the actual changes of the states of the automaton, only. These changes can then be observed from the outside of the module. The one process description is more adequate for this view. Additionally, the graphical description, which is often used as a specification for the VHDL model, resembles more a one statement than a two statements description => better version for understanding4Simplest Finite State Machine: Output=Current State orMedvedev FSMCombinational LogicState registersCurrent stateNext stateClockinputsoutputsDQ5Medvedev FSM equivalent descriptionTwo statements description: A description for each blockState