FPGA Implementation of Denoising in OFDM Systems using DSP Design Module

FPGA Implementation of Denoising in OFDM Systems using DSP Design Module

Prof. Brian L. EvansPhD Students

Jing Lin, Yousof Mortazavi, Marcel Nassar & Karl NiemanWireless Networking and Communications Group

Department of Electrical and Computer EngineeringCockrell School of Engineering

The University of Texas at Austin

May 10, 2012

Outline

Part I• Algorithm Description• Project Goals• System Design and ImplementationPart II• DemonstrationPart III• Conclusions and Discussion

2Outline | Background | System Design and Implementation | Conclusions

Impulsive Noise in Communication Systems

3

3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6x 10

6

-200

-100

0

100

200

samples Index

Vol

tage

Lev

el

Wireless CommunicationSources

Uncoordinated transmission

Computational PlatformClocks, buses and processorsOther embedded transmitters

Antennas

Baseband Processor

Non-CommunicationSources

Electromagnetic radiation

Outline | Background | System Design and Implementation | Conclusions

Noise Measurement

BackgroundNoise

4

Impulsive Noise in OFDM Systems

• FFT spreads received impulsive noise across all FFT bins

• SNR of each FFT bin is decreased• Receiver communication performance degrades

IFFT Filter + FFTEqualizer

and detectorVector

of symbolamplitudes(complex)


Channel

Receiverx y

Gaussian (g) + ImpulsiveNoise (e)

Impulsive Noise Mitigation (Denoising)

• N FFT bins (tones)• Transmitter null tones have zero power• Received null tones contain noise

• Impulsive noise estimation• Exploit sparse structure of null tones• FJ is over complete dictionary• e is sparse vector• g is complex Gaussian (g = F w)

5

IFFT Filter + + FFTEqualizer

and detectorImpulsive

noise estimation

Gaussian (w) + ImpulsiveNoise (e)

Vectorof symbolamplitudes(complex)

+-

Channel

Receiver

J is set of null tones (i.e. xj = 0)F is N x N FFT matrix

x y

|J| x N

6

Sparse Bayesian Learning (SBL)Step 1: Maximum likelihood estimate of hyper-parameters

Step 2: Estimate e from posterior mean:

Matrix MultiplyMatrix Inverse

Norm


-10 -5 0 5 1010

-5

10-4

10-3

10-2

10-1

SNR (dB)

Sym

bol E

rror R

ate

No cancellationSBL w/ null tonesSBL w/ all tones

~10dB~6dB

Project GoalsFrom theory to implementation:• understand computational requirements• determine real-time constraints in target application• find feasible solution

Steps involved:• develop floating-point model and simulator• fixed-point transformation• hardware/software partitioning• implementation


Chassis

NI Flex RIO(NI PXIe-7965R)SBL

Hardware

FPGA (hardware)

RT Host (software)

SBLSoftware

SimulatorNI Embedded Controller

(NI PXIe-8133)

NI PXIe Chassis(NI PXIe-1082)

System Design and Implementation Using NI Products

NI LabVIEW RT

NI LabVIEW FPGADSP Design Module


SBLHardware

SBLSoftware

Current Hardware/Software Partitioning


SBL Software

SBL Hardware

N = 128M = 32

(diagonal)

scalar

Computational Requirements for Powerline Communications

Major operations• N-point fast Fourier transform (N=128)• vector dot product (length 32, 128)• matrix-vector multiplication (32x128) x (128x1) • matrix-matrix multiplication (128x32) x (32x128)• matrix inversion (32x32)• multiple iterations per symbol (30 or more)

Real-time requirementprocessing time < OFDM symbol duration (231.7- 2240 µs)


FPGA hardware design using NI DSP Design ModuleDSP Diagram implements • FFT (N=128)• accumulators, adders, subtracters, multipliers• vector scaling (element-by-element)• 2-norm calculation (squaring + accumulating)


Fixed Point Transformation


Fixed Point Model of Computations in FPGA


Designing Wordlengths• MATLAB

• Displays statistics • Allows analysis of bit allocation• Graphical control• Automatic Settings

• LabVIEW• Used max/min (absolute value) to understand range at each node• Saturation indicators • Tedious manual process• Better to iterate in LabVIEW RT than on FPGA

14

Compile Results

FPGA hardware implementation can exploit parallelism by using more adders and multipliers!

Parallelism and pipelining can increase the maximum frequency.


Advantages of NI DSP Design Module

FPGA implementation is greatly simplified!Good level of abstraction to focus on algorithm development and increase productivity, rather than worry about:• clock domains• FIFOs and sizing• handshaking (e.g. data valid, ready for input, output ready, etc.)• DMA transfers between FPGA and host• etc.

Can do a lot with very little/no LabVIEW FPGA coding

Automatic test bench generation also very useful!


More advanced use of NI DSP Design Module

Matrix operations are not currently supported

May create custom “DSP Blocks” to load in DSP Diagram

Custom (high performance) blocks are coded in LabVIEW FPGA at a lower abstraction (requires more experience)

Implemented a 32x32 matrix-matrix complex multiply using 128 (out of 640) hardware multipliers on Virtex-5 SX95T FPGA


Example 32 Element Vector Dot Product

Can make high performance blocks, with a little wiring!


Example 32x32 Matrix Matrix Multiply


LabVIEW FPGA IP Builder• Fortunately, a new NI product called IP Builder can

simplify custom hardware design using more “software-like” structures


DEMO


Future Work at UTImplement more blocks in hardware

• Use IP Builder for matrix operations• QR decomposition in FPGA• Inversion with QR

Develop sequential version of algorithm with hardware implementation in mind

Use ADC/DAC and physical channel instead of simulator


Thank you for your attention!

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FPGA Implementation of Denoising in OFDM Systems using DSP Design Module

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