Fpga Class 2

47
FPGA Night Class #2 Unallocated Space, Severn MD [email protected] Presenter: David Protzman

description

2nd lecture of FPGA (field programmable gate array) class. Learn electronics.

Transcript of Fpga Class 2

  • FPGA NightClass #2Unallocated Space, Severn [email protected]: David Protzman

  • Agenda A few words about Unallocated Space Overview of last class Download example code Launching ISE Build example project Launching Impact, Mojo Loader, and Adept Uploading bit file to FPGA Tweaking example project Loading the simulator Simulate example project UCF files Viewing RTL and technology schematics Questions/Comments/Concerns

  • Unallocated Space ~ 3 years old Free to the public Run by donations Memberships available

    $25/mo - Check-in card $50/mo - Storage space and 2U of server space $100/mo - Key (upon approval) to Unallocated Space

    Suggested donation for this class: $5

  • Previous Class What is an FPGA?

    Slices, Configurable logic blocks, muxes, flip flops, etc Different brands of FPGAs

    Xilinx, Altera, Lattice Types of Xilinx FPGAs

    Spartan, Virtex, Artix, Kintex, Easy Path Difference between CPLD and FPGA Special parts of an FPGA

    DCM, PLL, DSP, RAM, IO Brief talk about ISE

  • Downloading Example Code We will be using GitHub Goto https://github.com/Unallocated

    This contains all of the Unallocated Space projects You want FPGA_NIGHT

  • Downloading Example Code

  • Downloading Example Code Extract code somewhere useful

    Make sure to remember where!! Well come back to these files later

  • Launching ISE - Windows Look for ISE Design Suite 32/64 Bit Command Prompt

  • Launching ISE - Windows Type ise (no quotes) and press enter

  • Launching ISE - Linux Bring up a terminal Figure out where ISE was installed

    Most likely in /opt/Xilinx/14.7/ If you dont know, then you can try this

    find / -name ise -executable 2>/dev/null Determine if you are using 32 or 64 bit by running

    uname -r You have 64 bit if you see x86_64

    For 64 bit run (Substitute PathToISE with the path to your ISE location) source PathToISE/ISE_DS/settings64.sh

    For 32 bit run (Substitute PathToISE with the path to your ISE location) source PathToISE/ISE_DS/settings32.sh

  • Launching ISE - Linux Example

  • Launching ISE - Linux This terminal now knows how to launch all of the ISE tools Simply run

    ise

  • Launching ISE - OSX

    Xilinx does not support OSX at *ALL*

  • Launching ISE Try to use the launcher for the correct architecture

    If you are running a 64 bit OS, run the 64 bit version Failure to run the correct version can cause

    Crashes Impact might not work (Weird library issues)

  • Opening Example Project

  • Opening Example Project

    Choose the correct folder for your board

  • Opening Example Project

  • Opening Example Project

  • Opening Example Project

  • Opening Main VHDL Source

    Double click

  • Opening Main VHDL Source

  • Building the Design

    Double Click

  • Building the Design This part will take some time The design will go through the following steps

    Synthesis Implementation

    Translate Map Place and Route

    Bit file generation

  • Programming Programming the FPGA is done using JTAG Boards may have special software, or use Impact

    Mojo - Mojo Loader (http://embeddedmicro.com/tutorials/mojo/installing-mojo-loader/)

    Basys2, Nexys3, Atlys - Adept (http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2)

    Spartan 3 Core Development Kit - Impact (Part of ISE)

  • Mojo Loader For Linux, you might have to run it as root

    Open a terminal and change directory to the mojo-loader folder Run:

    ./mojo-loader sudo ./mojo-loader

    For Windows you just need to double click on mojo-loader.exe

    Uncheck this for now

  • Mojo Loader

    Change this to * since the output file from ISE is a .bit, not a .bin

  • Mojo Loader

    Click Load to upload the bit file to the FPGA

  • Digilent Adept - Windows Go to http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828

    &Prod=ADEPT2 and download the Adept System

  • Digilent Adept - Windows Make sure that the Runtime and Application are selected

  • Digilent Adept - WindowsYour FPGA should show up here once connected to the computer

    Click here to select the bit file to upload

    Click here after selecting the file. This will upload the bit file to the FPGA

    This drop down will hold previously loaded bit files

  • Digilent Adept - Linux Go to http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828

    &Prod=ADEPT2 and download the Linux Runtime and Utilities files for your OS Check uname -r for 32/64 bit

  • Digilent Adept - Linux Extract the contents of the Runtime file

    Run the following command sudo ./install.sh

    Accept all defaults unless you want to change the install location Extract the contents of the Utilities file

    Run the following command sudo ./install.sh

    Accept all defaults unless you want to change the install location Run the following command with the board plugged in to verify installation

    djtgcfg enum This command should list your device

  • Digilent Adept - Linux There is not GUI :( Programming is done with the following command

    Nexys3 djtgcfg prog -i 0 -d Nexys3 -f myBitFile.bit

    Atlys djtgcfg prog -i 0 -d Atlys -f myBitFile.bit

    The -i is the device index in the JTAG chain. For programming the FPGA, this will just be 0. To store to the flash, this value might change

    The -d is the device name (output from the enum command earlier) The -f is the path to the bit file that will be sent to the FPGA

  • Impact - Windows & Linux The tool is the same for both Windows and Linux Get back to the terminal/console that ISE was launched from

    If you are running Linux, you will need to either open a new terminal or press CTRL+Z, then type bg (no quotes) to background the ISE process.

    Instead of ise, run impact (no quotes on either)

  • Impact - Windows & LinuxLeave this be as it will attempt to automatically detect your FPGA

    Make sure that your board is plugged up before clicking OK!

  • Impact - Windows & Linux

    If the FPGA and JTAG programmer are plugged up and everything went right, you should see Identify Succeeded

    This is the FPGA part that was found in the boundary scan

    Click Yes to select a bit file to upload

  • Impact - Windows & Linux

    Find the bit file you want to upload to the FPGA

    Click Open once you have the file selected

  • Impact - Windows & Linux

    Click No

  • Impact - Windows & Linux

    Here you have the option to verify that the program was successful. Leave unchecked for quicker uploads.

    Click OK to close

  • Impact - Windows & Linux1. Right click on the chip

    2. Select Program

  • Blinky Blinky Everyone should now have all 8 LEDs flashing ~ every second!

  • Tweaking the Example Find the following line

    if(divider = X/2) then Divide X by 2

    Ex: if X was 100000000 (one hundred million), change it to 50000000

    (fifty million) Double click on Generate Programming File again Upload resulting bit file to the FPGA What happened to the speed the LEDs blink at?

  • Loading the Simulator

  • Loading the SimulatorClick this radio button

  • Loading the Simulator

    UCF file is gone

  • Loading the SimulatorClicking on the VHDL file should cause the bottom panel to show ISim Simulator

  • Loading the Simulator

    Double click on this


Speedster7t FPGA Datasheet (DS015) - Achronix · 2021. 3. 2. · Speedster7t FPGA Datasheet (DS015) Preliminary Data 7 Chapter - 1: Overview Introducing the Speedster7t FPGA Family

Speedster7t FPGA Datasheet (DS015) - Achronix · 2021. 3. 2. · Speedster7t FPGA Datasheet (DS015) Preliminary Data 7 Chapter - 1: Overview Introducing the Speedster7t FPGA Family

Performance of a high-throughput tracking processor ... · FPGA Switch FPGA Switch FPGA Engine FPGA Switch Engine Detector layers To DAQ 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 track / cell

Performance of a high-throughput tracking processor ... · FPGA Switch FPGA Switch FPGA Engine FPGA Switch Engine Detector layers To DAQ 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 track / cell

2. Cnnecst-Why the use of FPGA?

2. Cnnecst-Why the use of FPGA?

LT Medium - InnovateAsia FPGA Design Contest 5G Algorithm... · 2015-05-28 · code files; 2. FPGA design document, Verilog RTL hardware description program, FPGA ... Code：code

LT Medium - InnovateAsia FPGA Design Contest 5G Algorithm... · 2015-05-28 · code files; 2. FPGA design document, Verilog RTL hardware description program, FPGA ... Code：code

Transformer less fpga controlled 2 stage isolated

Transformer less fpga controlled 2 stage isolated

EDA (CS286.5b) Day 11 Scheduling (List, Force, Approximation) N.B. no class Thursday (FPGA) …

EDA (CS286.5b) Day 11 Scheduling (List, Force, Approximation) N.B. no class Thursday (FPGA) …

How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

1 FPGA Boards and FPGA-based Supercomputers. 2 ECE 448 FPGA and ASIC Design with VHDL Resources PCI .

1 FPGA Boards and FPGA-based Supercomputers. 2 ECE 448 FPGA and ASIC Design with VHDL Resources PCI .

Fpga Class 1

Fpga Class 1

Best Practices For Efficient And Effective FPGA Designosmcontent.s3.amazonaws.com/embedded-techcon/Class Presentatio… · Best Practices For Efficient And Effective FPGA Design ...

Best Practices For Efficient And Effective FPGA Designosmcontent.s3.amazonaws.com/embedded-techcon/Class Presentatio… · Best Practices For Efficient And Effective FPGA Design ...

Unit 2 PLD & FPGA

Unit 2 PLD & FPGA

FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

FPGA Based System Design Unit-2

FPGA Based System Design Unit-2

Verilog FPGA-2

Verilog FPGA-2

Digital Synthesizer Built with Virtex 2 FPGA

Digital Synthesizer Built with Virtex 2 FPGA

 · CME3000-C FPGA Data Sheet v1.1 Web: . capital-micro.com Page 2 of 72 CME3000-C FPGA

 · CME3000-C FPGA Data Sheet v1.1 Web: . capital-micro.com Page 2 of 72 CME3000-C FPGA

Spartan-3 FPGA HDL Coding Techniques Part 1. Fundamentals of FPGA Design 1 day Designing for Performance 2 days Advanced FPGA Implementation 2 days Intro.

Spartan-3 FPGA HDL Coding Techniques Part 1. Fundamentals of FPGA Design 1 day Designing for Performance 2 days Advanced FPGA Implementation 2 days Intro.

Power and a New Class of Future FPGA Architectures Sinan Kaptanoglu Actel, Fellow.

Power and a New Class of Future FPGA Architectures Sinan Kaptanoglu Actel, Fellow.

FPGA as a First-Class Citizen in Cloud Computing · • FPGA needs to communicate and work with other devices • No generic socket programming interface available for hardware •

FPGA as a First-Class Citizen in Cloud Computing · • FPGA needs to communicate and work with other devices • No generic socket programming interface available for hardware •

FPGA and ASIC Technology Comparison Part 1. Fundamentals of FPGA Design 1 day Designing for Performance 2 day s Advanced FPGA Implementation 2 days Intro.

FPGA and ASIC Technology Comparison Part 1. Fundamentals of FPGA Design 1 day Designing for Performance 2 day s Advanced FPGA Implementation 2 days Intro.