FPGA Based Data Processing for Real-time WSN Applications:

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FPGA BASED DATA PROCESSING FOR REAL-TIME WSN

APPLICATIONS: A SYNTHESIS

Presented by: Ilham AmezzaneLaRIT- Ibn Tofail University

June 1st 2016

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Outline Background Real-time WSN Design Challenges FPGA implementation Conclusion

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A vast majority of WSN applications are real-time: Surveillance systems, Biometric sensing, Intrusion detection, Environmental monitoring, Habitant and health monitoring, Object tracking

Real-time WSNs

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WSN design objectives Expected to be :

Autonomous Low Power Scalable Context aware Adaptable

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Sensor nodes

Sources: provide sensing measurements

Sinks: where information is required Could be the same sensor node,

or an external entity such mobile phone/PC

Is part of an external network (e.g., internet).

WSN Architecture

Source: http://web.it.usyd.edu.au/~comp5416/Slides/Week%2010%20-%20Wireless%20Sensor%20Network.pdf

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Severe resource restrictions: limited bandwidth limited storage capacity limited energy sources tight deadlines to deliver the data.

Real-time WSN Design Challenges

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Main Components of Sensor Node

Processing coreCommunication

Memory

Sensors

Power supply

Source: hscc.cs.nthu.edu.tw/~sheujp/lecture_note/13wsn/ppt/WSN_Chapter%25202_Single_node%2520Architecture.ppt+&cd=4&hl=en&ct=clnk&lr=lang_en%7Clang_fr

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Sensing module

ControllerCommunication

Memory

Sensors

Power supply

IR sensor1-10 Hz

Ultrasonic1-100Khz Gyroscope

10-500 Hz

Triple axis accelerometer10Hz-10Khz

Temperature and Humidity Sensor

0.1-1 Hz

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Bandwidth of the sensing process Plays a fundamental role in the design of a

WSN.

The amount of sensed data highly depends on the nature of the observed phenomenon and on the desired accuracy of the WSN [1].

Will impact the type of hardware used and the approach for wireless communication.


Memory

Sensors

Power supply

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Bandwidth of the sensing process For low-power WSNs, the bandwidth of the RF channel is usually in the

range of 100 kbit/s up to 1 Mbit/s [2].

When sensor data is sampled at a range within one order of magnitude of this bandwidth, the communication channel is likely to be overloaded and processing the data becomes mandatory [2].

Sensors requiring a sampling rate higher than 10 Hertz can already be considered as high-bandwidth sensing devices [2].

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Bandwidth of the sensing process The same processing approach can not be used for each of

these sensors [1].

Source: http://tuprints.ulb.tu-darmstadt.de/4159/7/diss.pdf

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Processing core Main tasks :

signal processing communication protocol resources management.

The choice of the processing core is a trade-off between performance, power consumption and cost.


Memory

Sensors

Power supply

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Main options: MCUs (Microcontrollers)

For general purposes Optimized for embedded applications

DSPs (Digital Signal Processors) Optimized for signal processing Low cost

ASICs (Application-Specific Integrated Circuits) High performance for special purpose Not flexible

FPGAs (Field Programmable Gate Arrays) Cost lower than ASICs Processing speed lower than ASICs


Memory

Sensors

Power supply

Processing core

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Traditionally, a sensor node has been generally designed based on MCU platform.

Stringent requirements in terms of real-time, low-cost and low-energy forced researchers to think about higher performance platforms: DSP, ASIC, and FPGA .

Processing core

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Communication module The essentially task is to “transmit”

and “receive” data between a pair of nodes

Energy characteristics Power consumption to send/receive

data Time and energy consumption to

change between different states


Memory

Sensors

Power supply

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Why is energy efficiency important ? In many WSN applications, the sensor nodes

are battery driven.

Energy efficiency is needed to: Prolong network lifetime. Ensure network performance.

Almost 80% of the energy consumed by a sensor node is due to data transmission. Hence, by minimizing the data size, a sensor node can save energy [3].


Memory

Sensors

Power supply

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Computation vs. communication energy cost Tradeoff?

Directly comparing computation/communication energy cost ratio is not possible.

Energy ratio of “sending one bit” vs. “computing one instruction”: Anything between 220 and 2900 in the literature.

To communicate (send & receive) one kilobyte = computing three million instructions!

Compute instead of communicate whenever possible. Key technique: In-network processing


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In-network Processing for high bandwidth sensing

In-mote processing approaches to handle high-bandwidth sensing in WSNs [4]

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In-network Processing: Node level approaches

Sensor nodes do not just make measurements, they also perform data processing.

Processed data contain the compact event patterns rather than raw data.

Addresses the issue of communication overhead, data transfer energy consumption, as well as the storage space and network bandwidth requirements.

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Data compression: size of data reduced by eliminating statistical redundancy.

Data prediction: the trend of the data is identified, allowing predicting future behaviour. Hence, sensors do not need to transmit the sensed data as long as they are within a certain threshold or error bound.

Difference-based approach: only the difference between successive observations is considered (suitable for low fluctuation rate).

In-network Processing: Node level approaches

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The majority of techniques uses centralized approach: all data is transmitted to the sink node for identifying certain

patterns. much communication overhead and delay the response time.

The techniques that uses distributed approach optimize response time and energy consumption. suitable for real-time applications

In-network Processing: Distributed level approaches

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Data fusion: sensor readings from multiple nodes are combined into a single data set by eliminating spatial or temporal redundancy.

Data aggregation: observations are reduced to statistical characteristics computed among the data sets provided by each node.

Incremental analysis: measurements from neighbors or past measurements are used to limit the computational burden of regenerating a new observation.

In-network Processing: Distributed level approaches

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Processing Aggregation exampleThe simplest in-network processing techniqueReduce number of transmitted bits/packets by applying an

aggregation function in the network

Sink

1

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Sink

1

1

1

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1

Data

1


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Hardware implementation In-network processing approaches introduce a computing

time delay. Their software implementation is time consuming since they

often require massive matrix multiplications .

Hardware implementation? MCUs show poor execution time and energy efficiency in

many complex computational cases.

DSPs cannot usually meet the high performance and low-power consumption requirements of sensor nodes.

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ASICs, are able to perform specific calculations much faster than a similar software routine, and more energy efficient. But on the other hand are more expensive, and less flexible.

Integrating a hardware accelerator would be a better alternative to ASICs and general purpose processors.

FPGAs offer a balance between the speed of ASICs and the flexibility of software.

Hardware implementation

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FPGAs have been favored due to the high efficiency provided by their architectural flexibility parallelismhigh performance reconfigurability

FPGA implemention

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Data Parallelism: Inherent parallelism whose only limitation is the amount of chip space. Corresponds to a replication of components on the chip area. The process can be parallelized such that many independent calculations can

be performed concurrently.

FPGA implementation

Circuit replication

Source: http://www.odbms.org/wp-content/uploads/2014/03/Data-Processing-on-FPGAs.pdf

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Pipeline Parallelism: Applies to situations where a given task can be broken down into a sequence

sub-tasks, which can then be computed on separate processing units. Intermediate results are forwarded from unit to unit.

High performance : FPGA contains logic components that can be programmed:

To perform complex mathematical functions. To speed up arithmetic applications via rapid multipliers and adders [5].

FPGA implementation

Source: http://www.odbms.org/wp-content/uploads/2014/03/Data-Processing-on-FPGAs.pdf

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Example:

In [6], a data prediction mechanism for data transmission reduction is implemented .

The technique is based on the least-mean-square (LMS) algorithm and has been implemented on a Spartan-3E FPGA (XC3S100E).

It was possible to reduce the communication with more than 90% with an error of 0.5 degrees using a temperature sensor.

FPGA implementation

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Runtime Reconfiguration

Is the ability to modify the functional configuration of an FPGA device during operation, through hardware changes [7].

Allow remote hardware updates and performance of sensor nodes.

The device can be modified for a given situation to quickly adapt to WSN application changes (context-awareness).

FPGA implementation

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Partial Runtime Reconfiguration

Is the ability to reconfigure a portion of an FPGA during runtime.

Mission-critical operations can be preserved while only part of the FPGA device is reconfigured, which allows real-time adaptive reconfiguration [7].

The primary advantages are: reduced power consumption (smaller devices), hardware reuse and flexibility.

FPGA implementation

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Example : FPGA handles data processing Microcontroller handles node communications

Also is in charge of receiving new FPGA hardware configuration

FPGA implementation

Source: www.ann.ece.ufl.edu/courses/eel6686_15spr/.../Presentation3_CM.pptx

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Challenges and limitations What part of a given problem should be developed as

dedicated hardware and what part is better written as software or executed on some other platform [8].

Energy consumption, especially when low power is required simultaneously with real-time and computational power.

An intelligent run time system is needed to ensure that power is saved and that timing constraints are meet when using partial reconfiguration for real time systems.

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Both WSNs and FPGAs are independent areas of research and their integration is an emerging area of research.

FPGAs offer increased performance compared to microprocessors and increased flexibility compared to ASICs, while maintaining low power consumption.

New and innovative WSN applications demand longer battery life and faster responses. FPGAs are prime candidates to fulfill these requirements.

Conclusion

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References [1] A. Wang and A. Chandrakasan. “Energy-efficient DSPs for wireless sensor networks”. In:IEEE Signal

Processing Mag. 19.4 (July 2002), pp. 68–78. ISSN: 1053-5888. DOI: 10.1109/MSP.2002.1012351. [2] Philipp, François. Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition

Monitoring. Universitäts- und Landesbibliothek Darmstadt, Darrmstadt. [Ph.D. Thesis], (2014) [3] Kimura, N.; Latifi, S. A Survey on Data Compression inWireless Sensor Networks. In Proceedings of the

International Conference on Information Technology: Coding and Computing, Las Vegas,NV, USA, 11–13 April 2005; Volume 2, pp. 8–13.

[4] P. J. Marrón et al. “Challenges of Complex Data Processing in Real World Sensor Network Deployments”. In: Proc. ACM Workshop on Real-World Wireless Sensor Networks (REALWSN). Uppsala, Sweden: ACM, June 2006, pp. 43–48. URL: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.71.6789.

[5] Lopez, S.; Sarmiento, R.; Potter, P.G.; Luk, W.; Cheung, P.Y.K. Exploration of Hardware Sharing or Image Encoders. In Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, Germany, 8–12 March 2010; pp. 1737–1742.

[6] Debono, C.; Borg, N. The Implementation of an Adaptive Data Reduction Technique for Wireless Sensor Networks. In Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, Sarjevo, Bosnia And Herzegovina, 16–19 December 2008; pp. 402–406.

[7] ALTERA. FPGA Run-Time Reconfiguration: Two Approaches. White Paper. March 2008, ver. 1.0. ftp://ftp.bittware.com/documents/fpga-run-time-reconfiguration.pdf

[8] Woods, Louis. FPGA-enhanced data processing systems. ETH-Zürich (2014). http://dx.doi.org/10.3929/ethz-a-010175511.

http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.71.6789

ftp://ftp.bittware.com/documents/fpga-run-time-reconfiguration.pdf

http://dx.doi.org/10.3929/ethz-a-010175511

FPGA Based Data Processing for Real-time WSN Applications:

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