FPGA BASED 2 2 MMSE MIMO-OFDM SYSTEM USING XILINX SYSTEM GENERATOR · Journal of Engineering and...

Journal of Engineering and Sustainable Development Vol. 21, No. 01, January 2017 www.jeasd.org (ISSN 2520-0917)

152

;

FPGA BASED 2×2 MMSE MIMO-OFDM SYSTEM USING

XILINX SYSTEM GENERATOR

Dr. Fadhil Sahib Hasan

*

Lecturer, Electrical Engineering Department, Al-Mustansiriayah University, Baghdad, Iraq

Abstract: Multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) is

a powerful technique to increase the capacity of wireless communication system and decrease the effect

of selective fading to flat fading channel. In this paper 2×2 MIMO-OFDM system is implemented using

Xilinx system generator (XSG). Simple MMSE equalizer is implemented at the receiver to detect the

signal over MIMO channel. The following features are implemented and added to the proposed system:

increasing security of the system using chaos based scrambling, using 16-ADQAM modulation to solve

the ambiguity problem and implement FFT in pipelining method. The results show that the original data

is recovered successfully at the receiver. The VHDL code file is generated for this system for Xilinx

Virtex-4 device for hardware implementation purposes. The system is routed in successfully using ISE

14.1 program with resources of 21% slices Flip Flop, 57% LUT, 71% occupied slices and 87% DSP 48s

numbers from the selected device. The Xilinx system generator is more flexible, easier, and reliable and

gives optimum design for FPGA technique comparing with conventional FPGA design.

Keywords: MIMO, OFDM, MMSE, Chaos based PRBG, ADQAM, Xilinx System Generator, FPGA.

باستخذام مولذ النظام MMSE MIMO-OFDM 2×2في بناء منظومة FPGAأعتماد

Xilinx

ذعرثش ذقُيح انًقسى انًرعايذ انرشدد رو انًذخالخ انًرعذدج وانًخشجاخ انًرعذدج اسهىب فعال نضيادج قذسج االسريعاب في اَظًح لخالصة:ا

ج انى ذىهيٍ يسطخ. في هزا انثذث ذى تُاء يُظىيح االذصال انالسهكيح وذقهيم ذأثيش انرىهيٍ االَرقائي نهقُا

. ذى اضافح انخصائص انرانيح MIMOنكشف االشاسج خالج قُاج MMSE Equalizer . ذى اسرخذاو ذقُيح Xilinxتأسرخذاو يىنذج َظاو

و تُاء انذانح 16ADQAMانغًىض تاسرخذاو انرضًيٍ نهًُظىيح: صيادج ايُيح انُظاو تاسرخذاو انرشفيش انقائى عهى انفىضىيح, دم يشكهح

FFT تاسرخذاو طشيقح االَاتية. انُرائج اثثرد تاٌ االشاسج االصهيح ذى اسرشجاعها عُذ انًسرهى تشكم صذيخ ونقذ ذى ذىنيذ يهف انشفشج

VHDL نهُظاو انًقرشح يع جهاصXilinx Virtex-4 ذى ذىجيه انُظاو تُجاح تاسرخذاو تشَايج .ISE 14.1 ششائخ ٪ 12تًىاسد Flip

Flop ,75 ٪ LUT ,52 4٪ 75و ٪ ششائخ انًذرهحs7 DSP اٌ يىنذ انُظاو . يٍ انجهاص انًذذدXilinx يعرثش اكثش يشوَح

. FPGAيقاسَه تانطشيقح انرقهيذيه نرصًيى FPGA,سهىنح , يىثىقيح ويعطي انرصًيى االيثم نرقُيح

1. Introduction

Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier

transmission. This technique transform a frequency selective channel into a group of flat

narrowband channels that it is immunity against large delay spreads of the wireless

channel by preserving orthogonality in the time and frequency domain[1]. This

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Vol. 21, No.01, January 2017

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153

technique can be integrated with multiple input multiple output (MIMO) system to

increase either communication diversity as space time block coding (STBC) [2]or

capacity as spatial multiplexing (SM)[3].

Field programmable gate array (FPGA) is widely used in communication system

because it enhances the processing speed, explored the parallelism in implementation

and reduces the cost of the design [1]. In the recent years, spatial multiplexing MIMO-

OFDM implementation by using FPGA technique becomes the most interest for the

researchers [4-11]. Kerttula [4] designed and implemented 2×2 MIMO-OFDM system

with List sphere detector (LSD) algorithm using FPGA. Yoshizawa [5] designed

minimum mean square error (MMSE) MIMO detection using pipeline processing for

2×2 and 8×8 MIMO-OFDM system. In the same year, Park [6] designed Pipelining

processing for fast Fourier transform (FFT) an applied to MIMO-OFDM system. In [7]

Chen implemented a 4×4 MIMO-OFDM software defined radio (SDR) system using

MMSE detector and convolutional code. MIMO channel estimation in MIMO-OFDM

system was designed and implementation in [8] and [9].Babu [10] optimized MIMO-

OFDM system using convolutional code and Viterbi decoder. Sathya [11] designed and

implemented Fixed Sphere Decoding (FSD) to reduce complexity in MIMO OFDM

detection.

In this paper 2×2 MMSE MIMO OFDM is implemented using Xilinx system

generator. Three points are added to enhance the system: increase the security using

chaos stream ciphering, use Angle differential QAM (ADQAM) to solve the ambiguity

problem and implement fast Fourier transform (FFT) in pipelining manner. Also the

system can be designed in optimal and flexible way using system generator (SG) tools.

2. Xilinx System Generator (XSG)

System generator (SG) is the one of useful Xilinx DSP design tool that provides over

90 blocks of DSP such as multiplexer, shift register, adder, accumulator and multipliers

for implementing specific application. Also provides complex DSP blocks such as

convolutional encoder, FIR filter and FFT. Designer in SG is thinking in the same

manner as Matlab Simulink environment and can be integrated with Simulink block set

to test or help in the design in friendly way. When the system is implemented using

Xilinx system generator the optimum hardware description language (HDL) netlists or

Bitstreams compilation file can be generated directly including synthesis and Xing flow

routing to be used for programming the FPGA device using Integrated System

Environment (ISE) design suite program. A testbench representation can be generated in

Matlab Simulink environment for use with Xilinx ISE simulator or ModelSim. XSG can

be specified at the hardware design details for the specific FPGA Xilinx device [18].

Fig. 1 shows the SG design flow.

The advantage of using System Generator can be summarized as: reducing the time

spent by the designer for simulation of the system, flexibility due to update the design

parameters in quickly and test the effect on the system, The HDL files of the system can

be generated using compilation for ISE and Xilinx FPGAs, XSG blockset can be


154

integrated with Matlab Simulinlk blocks for helping and co-simulating the system

designing, the design can be implemented in optimal way with minimum cost [18].

Figure 1. Design flow of SG [18].

3. Mmse Mimo-Ofdm System

The proposed 2×2 MMSE MIMO OFDM system is shown in Fig. 2. In the first, the

bit streams are scrambled using chaos technique to increase the security of information.

Then convolutional code is used to enhance error performance of the system. Block

interleaving is take place after that to delete the affect of burst errors, block interleaving

is used here for its simplicity. To overcome ambiguity problem in 16-QAM, 16-

ADQAM instead is used. Parsing makes data stream to be separated into multiple

independent channel each one is passing through 16 points IFFT and cyclic prefix with

4 points. 2×2 MIMO flat fading channel and AWGN are take place to produce the

received signal where MMSE MIMO detection is used at receiver side to detect the

multiple received data after remove cyclic prefix guard and FFT are taken. All other

blocks in the receiver side are designed in inverse mode to that at transmitter side to

recover the original stream bits. We assume here the MIMO channel parameters are

perfect estimated at input of MIMO detection. The detail description of MIMO OFDM

blocks are summarized in next subsections.

Figure 2. MMSE MIMO-OFDM system


155

3.1. Chaos Based Scrambling

The security of communication system can be increased by encrypt or scramble the

data source before sending across the channel. One of the popular encryption techniques

for digital communication is stream cipher. The stream cipher system depends on

pseudo random bit generator (PRBG) XOR with data source to produce the ciphered

message at the receiver side the original message can be deciphered by XOR with the

same key bit generator that is synchronized with that at transmitter side. PRBG can be

generated using linear feedback shift register (LFSR) [12] or using the chaos technique.

Chaos based PRBG is used in the last years for increasing the security of the systems

like communication and encryption message due to have more randomness and security

than LFSR [13].

In this paper, PRBG can be generated using two logistic maps that were proposed in

[14]. The simple mathematical model of the logistic map is expressed as [14]:

(1)

where Xn is a state variable, which lies in [0,1] values and is the system parameter. In

this paper . Figs. 3 and 4 show block diagram for chaos based PRBG and

scrambling system respectively. Two Chaotic logistic maps are used to generate PRNG

each with different initial conditions, X0=0.939243 and Y0=0.162343 for the first and

second generation respectively.The PRBG at receiver side is identical to that at

transmitter side. The key stream in the transmitter and receiver sides must be

synchronized to recover the original data source.

Figure 3. Block diagram of Chaos based PRBG

Figure 4. Block diagram of Chaos based scrambling System

Chaos based

PRBG

XOR Original Data

Stream Bits

Chaos based

PRBG

XOR Original Data

Stream Bits

synchronization

Ciphered

Data

Key

Stream

Received

Ciphered Data

PRBG=

X0=0.93924

3

Y0=0.16234

3

1010111010


156

3.2. Angle Differential Quadrature Amplitude Modulation (16-ADQAM)

The widely used in digital modulation is 16-QAM (Quadrature Amplitude

Modulation) because it has good power and spectral efficiency. Although the square

QAM has disadvantaged that it suffers from ambiguity problem. Therefore angle

differential QAM (ADQAM) was studied in [15] is used to solve this problem. This

study showed that 16-ADQAM has degraded in SNR about 0.5 dB only when compared

with coherent QAM over AWGN channel. In this paper, 16-ADQAM is implemented

using Xilinx system generator (XSG).

16-ADQAM requires four bits group and there are 24 possible transitions between

two consecutive transmitted symbols s(i) and s(i-1). The transmitted symbol s(i) can be

expressed in terms a quadrant center C(i), and a displacement D(i) as [15]:

s(i)=C(i)+D(i) (2)

C(i)=C(i-1) (3)

D(i)=D(i-1) (4)

where and are the differential angles which can be determined from the first

two bits (b0,b1) and second two bits (b2,b3)of QAM symbol respectively as shown in

Table 1.

Table 1. Dibit to differential angle mapping for and

s(0) is initialized by assuming C(0)=R1 and D(0)=R2 , where R1=2

represents the distance between the origin point and the quadrant center point, and R2

= is the distance between the quadrant center point and the constellation point.

At the receiver, the symbols s(i) are corrupted with AWGN , n(i). The receiver

symbols, y(i) can be written as [15]:

y(i)=s(i) + n(i) (5)

where is the phase ambiguity which takes any value between 0 and 3 in step .

A two stage differential decoding is used for 16-ADQAM demodulation. Substituting

Equation (2), get:

y(i)=C(i) + D(i) + n(i)

=Cr(i) + Dr(i) + n(i) (6)

Dibit

0 0 0

0 1 1 1 1 0


157

where Cr(i) and Dr(i) are the quadrant center and displacement symbols that are rotated

by angle respectively. Cr(i) can be detected from the received symbols, y(i) as [15]:

(7)

where sgn (.) is the signum function, real (.) is the real part of a complex signal and

imag(.) is the imaginary part. The differential angle can be detected from the

present and previous values of as [15]:

(8)

Dr(i) can be detected from the difference between y(i) and as [15]:

(9)

The differential angle can be detected from the present and previous values of

as [15]:

(10)

A two stage decoding of 16-ADAM system is shown in Fig. 5.

Figure 5. Block diagram of 16-ADQAM detection.

Sgn(.) Phase

Detector

z-1

Sgn(.)

z-1

Phase

Detector

y(i) (i)

(i-1)

(i)

(i-1)

(i)

(i)


158

3.3 Fast Fourier Transform (FFT)

16 points decimation in time fast Fourier Transform (FFT) algorithm can be

implemented by pipelining techniques in which different functions can be executed at

the same time therefore the throughput is increased [16]. However, the pipelining

required more hardware than to that of a system without pipelining. Fig. 6 shows flow

diagram of 16-point decimation in time FFT algorithm. To implement 16 points FFT,

four stages are required {stage_1, stage_2, stage_3 and stage_ 4} in this modules only

addition and subtraction operation required. Also three multiple modules {Multiple_1,

Multiple_2, and Multiple_3}is required where in this modules the incoming complex

samples from the previous module is multiplied by twiddle factor ,

.Inverse fast Fourier transform (IFFT) is implemented in the same

manner only twiddle factor is replaced by For Stage_1 module there are

8 functions of 2 points each with two complex additions. For Stage_2 module there are

4 functions of 4 points each with 4 complex additions. For Stage_3 module there are 2

functions of 8 points each with 8 complex additions. Stage_4 module has one function

of 16 points with 16 complex additions. Each of Mutilple_1, Mutilple_2 and Mutilple_3

has 8 complex multiplications. The total complex additions is 16×log2(16)=64 and the

total complex multiplications is (16/2)×log2(16)=32.

Figure 6. 16-points decimation in time FFT algorithm [19].


159

3.4 Mimo Detection

Spatial multiplexing (SM) technique increases the capacity gain linearly by increasing

number of transmitter and receiver antennas without requiring any additional spectral resources.

The relation between the transmitted and received signal for Nt transmitter antennas and Nr

receiver antennas MIMO channel is given by [5]:

(11)

where x=[x1, x2,…, ]T and y=[y1, y2, …, ]

T are transmitted and received symbol

vector respectively. n=[n1, n2, …, ] is additive white Gaussian noise vector with

variance . H is Nt× Nr MIMO channel matrix. For 2 ×2 MIMO channel:

(12)

Where h11,h12,h21 and h22 are random independent coefficients of channel matrix that are

generated from Gaussian random distribution and needed to be estimated at the receiver

side by using channel estimation techniques[7].

There are different MIMO detections techniques that are used to detect the original

data from the received signal in MIMO system. One of the simplest methods studied is

minimum mean square error (MMSE) linear detector. The output complex estimated

signal of MMSE detector can be expressed as [9]:

y (13)

where (.)H is Hermitian transpose and I is identity matrix of size Nt×Nr .

4. Mimo-Ofdm Implementation Using Xilinx System Generator

The block diagram of the proposed designed 2×2 MIMO-OFDM transceiver system

is shown in Fig. 7. Each block is built using Xilinx system generator (XSG) tools with

master clock period 10 ns. The parameters used for MIMO-OFDM system are

summarized in Table 2.

In transmitter side the random bit generator, with rate 100 Mbps, is scrambled using

chaos based stream ciphering method. The Convolution encoder encodes the binary

scrambled stream bits with code rate ½, the output rate becomes 200 Mbps, and then

matrix interleaver is used to produce interleaved stream bits. 16-ADQAM modulation is

used and produces complex modulated signals with symbol rate 50 M samples/s. The

signal then converted from serial to 2 parallel samples to get rate about 100 M samples

/s. The signal after will be passed through the Inverse Fast Fourier Transform (IFFT)

block to produce the OFDM signal, here we ignore adding cyclic prefix guard. The first

signal is send in one antenna and the other in the second antenna. This operation

increases the capacity of the system by two to become100 M sample/sec. After that the

signals are corrupted with MIMO channel with flat fading channel and AWGN


160

channels. In the receiving side linear MMSE MIMO detection is used to recover the

clean signals. Here we assume that the channel is perfected estimation therefore the

parameters of the channels are directed entered to the MMSE MIMO detection. All the

operations in the transmitted side are inversed in the received side to reconstruct the

binary stream bits. The detail descriptions of each block are illustrated in the next

subsections.

Table 2. MIMO-OFDM System Parameters

Clock Antenna

configuration Modulation

Number of

subcarrier

Coding

Coding

rate

MIMO

processing

MIMO

Signaling

100

MHz 2×2

OFDM with

16-ADQAM 16

Binary

convolutio

nal code

1/2 MMSE Spatial

Multiplexing

Figure 7. XSG block diagram of MIMO-OFDM transceiver.

4.1 Transmitter Section

4.1.1 Random Stream Bits generator

Random integer generator block in Simulink is used to generate random stream bits

with Bernoulli distribution function. The data rate is 100 M bps.

In

stream_input

0

reset

Din

Imagl_1

Imag_2

S2P2

Din

Real_1

Real_2

S2P1Resource

Estimator

Random

Integer

Random Integer

Generator1

IN1

IN2

ant1_real

P2S_2

IN1

IN2ant1_real

P2S_1

Din

reset

Dout1

Matrix Interleaver

Din

reset

Dout

Matrix DeInterleaver

R1

I1

R2

I2

h11_r

h11_i

h12_r

h12_i

h21_r

h21_i

h22_r

h22_i

Real1

Imag1

Real2

Imag2

MMSE MIMO Detection

In1

In2

In3

In4

Real1Imag1Real2Imag2h11_rh11_ih12_rh12_ih21_rh21_ih22_rh22_i

MIMO Channel

In1

In2

Out1

Out2

IFFT_2

In1

In2

Out1

Out2

IFFT_1

[reset]

Goto

O

ut Gateway Out3

Out

Gateway Out1

[reset]

From6

[reset]

From5

In1

In2

Out1

Out2

FFT_2

In1

In2

Out1

Out2

FFT_1

Error Rate

Calculation

Tx

Rx

Error Rate

Calculation

Display

z-268Delay

In1

Out1

PRBG

DeCiphering

input

reset

Output

Convolutional Decode

data

reset

Dserial

Convolutional Code

In1

Out1

PRBG

Ciphering

data

reset

QAM_I

QAM_Q

16ADQAM Mod

receiv ed_I

receiv ed_Q

reser

Out1

16ADQAM Demod

Sy stem

Generator


161

4.1.2 Data Ciphering Using Chaos

XSG block diagram of ciphering technique is shown in Fig. 8.The format operation

is 24 fixed point precision with 16 binary points.

Two chaotic logistic maps are implemented from Equation 1 and then compared

using relational block to obtain the PRBG that is used as key stream bits.

In chaotic logistic map generator, the single pulse is on only for one cycle to select

the initial condition. In the remaining time the feedback signal is selected in the

multiplexer.

Figure 8. XSG block diagram of ciphering mode.

4.1.3 Convolutional Encoder

The convolutional encoder 7.0 is Xilinx communication blockset that is IP core

implemented in XSG. Fig. 9 shows the convolutional code with the following

parameters: code rate=1/2, constraint length=7 and the code generator [133 171] in octal

form. The output of convolutional encoder is then converted to stream bits by using

parallel to serial converter.

Figure 9. XSG block diagram of convolutional code.

1

Dserial

1

enable1

1

enable

p

en

rst

sz-1

Parallel to Serial

data_in

rst

en

data_out_v

Convolution Encoder 7.0 castz

-2

Convert1

cast

Convert

2

reset

1

data

1

Out1

Out1

single plus1

Out1

single plus

a

b

a > b

Relational

sel

d0

d1

Mux1

sel

d0

d1

Mux

a

ba b

Mult3

a

ba b

Mult2

a

ba b

Mult1

a

ba b

Mult

xor

Logical1

z-1

Delay1

z-1

Delay

4

Constant5

1

Constant4

0.1623382568359375

Constant3

4

Constant2

1

Constant1

0.939239501953125

Constant

Assert

Assert1

a

b

a - b

AddSub1

a

b

a - b

AddSub

1

In1

Chaotic Logistic Map Generator-1

Chaotic Logistic Map Generator-2

Key stream Bits PRBG

Original Data Source

Ciphered Data

X0=0.939243

Y0=0.16234

3


162

4.1.4 Block Interleaver

Interleaving is effective way to delete the effect of burst errors due to channel noise.

It works by spread out the burst errors to be appeared as random at the decoder. One of

the most used type for interleaving is block interleaver.

A block interleaver is implemented by writing the bits into a matrix row by row and

then reading them column by column [17]. Fig. 10 shows XSG block diagram of block

interleaver for 4 4× matrix.

Figure 10. XSG block diagram of block interleaver.

4.1.5 16-ADQAM Modulator

XSG block diagram of 16-ADQAM modulation is shown in Fig. 11. The stream

interleaved data is converted to parallel four bits {b3b2b1b0} by using serial to parallel

blockset. Each two bit is concatenated to unsigned value using concatenate blockset and

used as addressing in RAM memory to select one of the following phase { 0 ,1.5708, -

1.5708, 3.141} with fixed point of word length=13 and fractional bits length=10, this is

suitable format for this function.

After that sine and cosine functions of the differential angle ( ) are calculated using

CORDIC SINCOS blockset to produce . Then, and are multiplied by

Cr(i-1) and Dr(i-1) respectively using complex multiplication (CM) block to produce

Cr(i) and Dr(i) as in (3) and (4) respectively. Complex multiplication block is shown in

1

Dout1

1

enable2

1

enable1

d

rst

en

qz-1

Register9

d

rst

en

qz-1

Register8

d

rst

en

qz-1

Register7

d

rst

en

qz-1

Register6

d

rst

en

qz-1

Register5

d

rst

en

qz-1

Register4

d

en

qz-1

Register31

d

en

qz-1

Register30

d

rst

en

qz-1

Register3

d

en

qz-1

Register29

d

en

qz-1

Register28

d

en

qz-1

Register27

d

en

qz-1

Register26

d

en

qz-1

Register25

d

en

qz-1

Register24

d

en

qz-1

Register23

d

en

qz-1

Register22

d

en

qz-1

Register21

d

en

qz-1

Register20

d

rst

en

qz-1

Register2

d

en

qz-1

Register19

d

en

qz-1

Register18

d

en

qz-1

Register17

d

en

qz-1

Register16

d

rst

en

qz-1

Register15

d

rst

en

qz-1

Register14

d

rst

en

qz-1

Register13

d

rst

en

qz-1

Register12

d

rst

en

qz-1

Register11

d

rst

en

qz-1

Register10

d

rst

en

qz-1

Register1

d

rst

en

qz-1

Register

sel

d0

d1

d2

d3

d4

d5

d6

d7

d8

d9

d10

d11

d12

d13

d14

d15

en

z-1

Mux

dout

LFSR1

en ++

Counter

castz

-5

Convert3

castz

-22

Convert1

castz

-6

Convert

2

reset

1

Din

Direction of writing

Dir

ecti

on

of

Rea

din

g


163

Fig. 12. Finally, the complex s(i) can be calculated using AddSub blockset between

Cr(i) and Dr(i) according to (2).

Figure 11. XSG block diagram of 16-ADQAM modulation.

Figure 12. XSG block diagram of two complex number multiplication.

4.1.6 Serial to parallel Converter

The serial 16-ADQAM symbols are converted from serial symbols to two parallel

symbols using serial to parallel block shown in Fig. 13.This produce two symbols one

to be used for the first channel and the other for second channel to produce two

transmits signal. We need two block of serial to parallel converter one for real and the

other for imaginary part.

Figure 13. XSG block diagram of serial to parallel converter.

Cr_real(i-1)

Cr_imag(i-1)

Dr_real(i-1)

Dr_imag(i-1)

Dr_real(i)

Dr_imag(i)

Cr_imag(i)

Cr_real(i)

s_real(i)

s_imag(i)

2

imag

1

real

addr

en

z-1

phase_Mapping2

addr

en

z-1

phase_Mapping1

1

enable3

1

enable21

enable1

[a:b]

b3

[a:b]

b2

[a:b]

b1

[a:b]

b0

s

rst

pz-1

Serial to Parallel

d

enqz

-1

Register7

d

enqz

-1

Register6

d

enqz

-1

Register5

d

enqz

-1

Register4

d

enqz

-1

Register3

d

enqz

-1

Register2

d

enqz

-1

Register17

d

enqz

-1

Register1

castz

-4

Convert3

castz

-14

Convert2cast

z-13

Convert1

hi

lo}

Concat2

hi

lo}

Concat1

z-11z

cos

sin

CORDIC SINCOS1

z-11z

cos

sin

CORDIC SINCOS

r1

i1

r2

i2

real

imag

CM2

r1

i1

r2

i2

real

imag

CM1

a

b

a + b

AddSub1

a

b

a + b

AddSub

2 reset

1 data

2

imag

1

real

a

ba b

Mult3

a

ba b

Mult2

a

ba b

Mult1

a

ba b

Mult

a

b

a + b

AddSub1

a

b

a - b

AddSub

4

i2

3

r2

2

i1

1

r1

2

Real_2

1

Real_1

1

enable2

d

en

qz-1

Register1

d

en

qz-1

Register

dout

LFSR1

en

z-4

Delay1

en

z-4

Delay

castz

-29

Convert3

castz

-30

Convert

1

Din


164

4.1.7 Inverse Fast Fourier Transform (Ifft)

In the first the signal is converted to parallel 16 samples as shown in Fig. 14. The

XSG block diagram of serial to parallel converter of 16 samples is shown in Fig. 15.

The complex parallel 16 samples are then ready to enter into IFFT to obtain OFDM

signal. IFFT converts the ADQAM signal from frequency to time domain. These 32

parallel complex symbols split into two frame each of 16 complex symbols. The first

frame entered the first IFFT block to produce the first OFDM complex signal and the

second 16 complex symbols are entered to the second IFFT block to produce the second

OFDM complex signal. Fig. 16 shows XSG block diagram of IFFT. In the first the 16

complex signals are shuffled according to bit reversal order. After that the shuffled data

is passing through Stage_1, Multiple_1, Stage_2, Multiple_2, Stage_3, Multiple_3 and

Stage_4 modules that it are implemented using XSG as shown in Figs. (17-23)

respectively. Each format operation is fixed points with 20 word length bit and 16

fractional bits. This format is optimum choose for IFFT when compared with that of

Matlab values we obtain about 0.005 mean square error.

Figure 14. XSG block diagram of IFFT.

Figure 15. XSG block diagram of serial to parallel 16 samples

2

Out2

1

Out1

Din

I_dataI_data1I_data2I_data3I_data4I_data5I_data6I_data7I_data8I_data9

I_data10I_data11I_data12I_data13I_data14I_data15S2P2

Din

I_dataI_data1I_data2I_data3I_data4I_data5I_data6I_data7I_data8I_data9

I_data10I_data11I_data12I_data13I_data14I_data15

S2P1 IN1IN2IN3IN4IN5IN6IN7IN8IN9IN10IN11IN12IN13IN14IN15In16

ant1_imag

P2S2

IN1IN2IN3IN4IN5IN6IN7IN8IN9IN10IN11IN12IN13IN14IN15In16

ant1_real

P2S1

R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16I1I2I3I4I5I6I7I8I9I10I11I12I13I14I15I16

Out_R1Out_R2Out_R3Out_R4Out_R5Out_R6Out_R7Out_R8Out_R9

Out_R10Out_R11Out_R12Out_R13Out_R14Out_R15Out_R16

Out_I1Out_I2Out_I3Out_I4Out_I5Out_I6Out_I7Out_I8Out_I9

Out_I10Out_I11Out_I12Out_I13Out_I14Out_I15Out_I16

IFFT1

2

In2

1

In1

16

I_data15

15

I_data1414

I_data13

13

I_data1212

I_data1111

I_data10

10

I_data99

I_data8

8

I_data7

7

I_data66

I_data5

5

I_data4

4

I_data3

3

I_data2

2

I_data1

1

I_data

1

enable2

d

en

qz-1

Register9

d

en

qz-1

Register8

d

en

qz-1

Register7

d

en

qz-1

Register6

d

en

qz-1

Register5

d

en

qz-1

Register4

d

en

qz-1

Register3

d

en

qz-1

Register2

d

en

qz-1

Register15

d

en

qz-1

Register14

d

en

qz-1

Register13

d

en

qz-1

Register12

d

en

qz-1

Register11

d

en

qz-1

Register10

d

en

qz-1

Register1

d

en

qz-1

Register

dout

LFSR1

en

z-8

Delay9

en

z-8

Delay8

en

z-8

Delay7

en

z-8

Delay6

en

z-8

Delay5

en

z-8

Delay4

en

z-8

Delay3

en

z-8

Delay2

en

z-8

Delay15

en

z-8

Delay14

en

z-8

Delay13

en

z-8

Delay12

en

z-8

Delay11

en

z-8

Delay10

en

z-8

Delay1

en

z-8

Delay

castz

-38

Convert3

castz

-39

Convert

1

Din


165

Figure 16. XSG block diagram of 16 points decimation in time IFFT.

Figure 17. Stage_1 Module of IFFT.

stage4

32

Out_I16

31

Out_I15

30

Out_I14

29

Out_I13

28

Out_I12

27

Out_I11

26

Out_I10

25

Out_I9

24

Out_I8

23

Out_I7

22

Out_I6

21

Out_I5

20

Out_I4

19

Out_I3

18

Out_I2

17

Out_I1

16

Out_R16

15

Out_R15

14

Out_R14

13

Out_R13

12

Out_R12

11

Out_R11

10

Out_R10

9

Out_R9

8

Out_R8

7

Out_R7

6

Out_R6

5

Out_R5

4

Out_R4

3

Out_R3

2

Out_R2

1

Out_R1

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

Din

Din1

Din2

Din3

Din4

Din5

Din6

Din7

Din8

Din9

Din10

Din11

Din12

Din13

Din14

Din15

I_data19

I_data1

I_data2

I_data3

I_data4

I_data5

I_data6

I_data7

I_data8

I_data9

I_data10

I_data11

I_data12

I_data13

I_data14

I_data15

shuffl ing_1_real

Din

Din1

Din2

Din3

Din4

Din5

Din6

Din7

Din8

Din9

Din10

Din11

Din12

Din13

Din14

Din15

I_data19

I_data1

I_data2

I_data3

I_data4

I_data5

I_data6

I_data7

I_data8

I_data9

I_data10

I_data11

I_data12

I_data13

I_data14

I_data15

shuffl ing_1_imag

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

multiple_3

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

multiple_1

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

Stage_3

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

Stage_2

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13

r14

r15

r16

i1

i2

i3

i4

i5

i6

i7

i8

i9

i10

i11

i12

i13

i14

i15

i16

output_R1

output_I1

output_R2

output_I2

output_R3

output_I3

output_R4

output_I4

output_R5

output_I5

output_R6

output_I6

output_R7

output_I7

output_R8

output_I8

output_R9

output_I9

output_R10

output_I10

output_R11

output_I11

output_R12

output_I12

output_R13

output_I13

output_R14

output_I14

output_R15

output_I15

output_R16

output_I16

Stage_1

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

R9

I9

R10

I10

R11

I11

R12

I12

R13

I13

R14

I14

R15

I15

R16

I16

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

OR9

OI9

OR10

OI10

OR11

OI11

OR12

OI12

OR13

OI13

OR14

OI14

OR15

OI15

OR16

OI16

Multiple_2

32

I16

31

I15

30

I14

29

I13

28

I12

27

I11

26

I10

25

I9

24

I8

23

I7

22

I6

21

I5

20

I4

19

I3

18

I2

17

I1

16

R16

15

R15

14

R14

13

R13

12

R12

11

R11

10

R10

9

R9

8

R8

7

R7

6

R6

5

R5

4

R4

3

R3

2

R2

1

R1

2*2 butterfly

32

output_I16

31

output_R16

30

output_I15

29

output_R15

28

output_I14

27

output_R14

26

output_I13

25

output_R13

24

output_I12

23

output_R12

22

output_I11

21

output_R11

20

output_I10

19

output_R10

18

output_I9

17

output_R9

16

output_I8

15

output_R8

14

output_I7

13

output_R7

12

output_I6

11

output_R6

10

output_I5

9

output_R5

8

output_I4

7

output_R4

6

output_I3

5

output_R3

4

output_I2

3

output_R2

2

output_I1

1

output_R1

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

R1

R2

I1

I2

OR1

OI1

OR2

OI2

32

i16

31

i15

30

i14

29

i13

28

i12

27

i11

26

i10

25

i9

24

i8

23

i7

22

i6

21

i5

20

i4

19

i3

18

i2

17

i1

16

r16

15

r15

14

r14

13

r13

12

r12

11

r11

10

r10

9

r9

8

r8

7

r7

6

r6

5

r5

4

r4

3

r3

2

r2

1

r1

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

Real

Imag

Complex subtraction

R1

I1

R2

I2

Real

Imag

Complex addition

4 I2

3 I1

2

R2

1

R1

2

Imag

1

Real

a

b

a + b

AddSub1

a

b

a + b

AddSub

4

I2

3

R2

2

I1

1

R1

2

Imag

1

Real

a

b

a - b

AddSub1

a

b

a - b

AddSub

4

I2

3

R2

2

I1

1

R1

Complex Addition Complex subtraction


166

Figure 18. Multiple_1 Module of IFFT Figure 19. Stgae_2 Module of

IFFT

Figure 20. Multiple_2 Module of IFFT Figure 21. Stgae_3 Module of IFFT

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

Real_in

imag_in

Real_out

Imag_out

CMULT3

Real_in

imag_in

Real_out

Imag_out

CMULT2

Real_in

imag_in

Real_out

Imag_out

CMULT1

Real_in

imag_in

Real_out

Imag_out

CMULT

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

2

Imag_out

1

Real_out

a

ba b

Mult

-1

Constant

2

imag_in

1

Real_in

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

Real_in

imag_in

Real_out

Imag_out

CMULT3

Real_in

imag_in

Real_out

Imag_out

CMULT2

Real_in

imag_in

Real_out

Imag_out

CMULT1

Real_in

imag_in

Real_out

Imag_out

CMULT

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

2

Imag_out

1

Real_out

a

ba b

Mult

-1

Constant

2

imag_in

1

Real_in

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

Real_in

imag_in

Real_out

Imag_out

CMULT3

Real_in

imag_in

Real_out

Imag_out

CMULT2

Real_in

imag_in

Real_out

Imag_out

CMULT1

Real_in

imag_in

Real_out

Imag_out

CMULT

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

2

Imag_out

1

Real_out

a

ba b

Mult

-1

Constant

2

imag_in

1

Real_in

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

R1

I1

R2

I2

R3

I3

R4

I4

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

Real

Imag

Complex subtraction2

R1

I1

R2

I2

Real

Imag

Complex subtraction1

R1

I1

R2

I2

Real

Imag

Complex Addition1

R1

I1

R2

I2

Real

Imag

Comp;ex Addition2

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

4×4 butterfly

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

0

Constant9

1

Constant8

0.7071075439453125

Constant7

-0.7071075439453125

Constant6

1

Constant5

0

Constant4

0.7071075439453125

Constant3

0.7071075439453125

Constant2

0.7071075439453125

Constant15

-0.7071075439453125

Constant14

1

Constant13

0

Constant12

0.7071075439453125

Constant11

0.7071075439453125

Constant10

0

Constant1

1

Constant

R1

I1

R2

I2

Real

Imag

C MULT8

R1

I1

R2

I2

Real

Imag

C MULT7

R1

I1

R2

I2

Real

Imag

C MULT6

R1

I1

R2

I2

Real

Imag

C MULT5

R1

I1

R2

I2

Real

Imag

C MULT4

R1

I1

R2

I2

Real

Imag

C MULT3

R1

I1

R2

I2

Real

Imag

C MULT2

R1

I1

R2

I2

Real

Imag

C MULT1

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

8*8 butterfly

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

R1

I1

R2

I2

R3

I3

R4

I4

R5

I5

R6

I6

R7

I7

R8

I8

OR1

OI1

OR2

OI2

OR3

OI3

OR4

OI4

OR5

OI5

OR6

OI6

OR7

OI7

OR8

OI8

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

Real

Imag

CompADD3

R1

I1

R2

I2

Real

Imag

CompADD2

R1

I1

R2

I2

Real

Imag

CompADD1

R1

I1

R2

I2

Real

Imag

CompADD

R1

I1

R2

I2

Real

Imag

ComSUB3

R1

I1

R2

I2

Real

Imag

ComSUB2

R1

I1

R2

I2

Real

Imag

ComSUB1

R1

I1

R2

I2

Real

Imag

ComSUB

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1


167

Figure 22. Multiple_3 Module of IFFT Figure 23. Stgae_4 Module of IFFT

The 16 parallel OFDM signal is then converted to serial symbols again using parallel to

serial converter. It is required two converters for each OFDM signal one for real and the

other for imaginary part. Fig. 24 shows XSG block diagram for one of parallel to serial

converter. These two serial complex OFDM signals are spatially multiplexed over

MIMO channel.

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

1

Constant9

0

Constant8

0.3827056884765625

Constant7

0.7071075439453125

Constant6

0.7071075439453125

Constant5

0.3827056884765625

Constant4

0.9239044189453125

Constant3

0

Constant2

0.9239044189453125

Constant16

0.3827056884765625

Constant15

-0.9239044189453125

Constant14

0.7071075439453125

Constant13

-0.7071075439453125

Constant12

0.9239044189453125

Constant11

-0.3827056884765625

Constant10

1

Constant1

R1

I1

R2

I2

Real

Imag

C MULT8

R1

I1

R2

I2

Real

Imag

C MULT7

R1

I1

R2

I2

Real

Imag

C MULT6

R1

I1

R2

I2

Real

Imag

C MULT5

R1

I1

R2

I2

Real

Imag

C MULT4

R1

I1

R2

I2

Real

Imag

C MULT3

R1

I1

R2

I2

Real

Imag

C MULT2

R1

I1

R2

I2

Real

Imag

C MULT1

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1

32

OI16

31

OR16

30

OI15

29

OR15

28

OI14

27

OR14

26

OI13

25

OR13

24

OI12

23

OR12

22

OI11

21

OR11

20

OI10

19

OR10

18

OI9

17

OR9

16

OI8

15

OR8

14

OI7

13

OR7

12

OI6

11

OR6

10

OI5

9

OR5

8

OI4

7

OR4

6

OI3

5

OR3

4

OI2

3

OR2

2

OI1

1

OR1

R1

I1

R2

I2

Real

Imag

Complex Subtraction8

R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag


R1

I1

R2

I2

Real

Imag

Complex Addition8

R1

I1

R2

I2

Real

Imag

Complex Addition7

R1

I1

R2

I2

Real

Imag

Complex Addition6

R1

I1

R2

I2

Real

Imag

Complex Addition5

R1

I1

R2

I2

Real

Imag

Complex Addition4

R1

I1

R2

I2

Real

Imag

Complex Addition3

R1

I1

R2

I2

Real

Imag

Complex Addition2

R1

I1

R2

I2

Real

Imag

Complex Addition1

32

I16

31

R16

30

I15

29

R15

28

I14

27

R14

26

I13

25

R13

24

I12

23

R12

22

I11

21

R11

20

I10

19

R10

18

I9

17

R9

16

I8

15

R8

14

I7

13

R7

12

I6

11

R6

10

I5

9

R5

8

I4

7

R4

6

I3

5

R3

4

I2

3

R2

2

I1

1

R1


168

Figure 24. XSG block diagram of parallel to serial converter

4.1.8 MIMO Channel

Fig. 25 shows XSG block diagram of 2×2 MIMO flat fading with AWGN channel.

Each element in H matrix {h11,h12,h21 and h22} is implemented using white Gaussian

noise generator blockset in communication Xilinx reference blockset.

Figure 25. XSG MIMO block diagram of flat fading with AWGN channel.

h11_r

h11_i

h12_r

h12_i

n1_r

n1_i

complex Addition2

6

h12_i

5

h12_r

4

h11_i

3

h11_r

2

Out2

1

Out1

resetnoise

White Gaussian

Noise Generator5

reset noise

White Gaussian

Noise Generator4

reset noise

White Gaussian

Noise Generator3

reset noise

White Gaussian

Noise Generator2

reset noise

White Gaussian

Noise Generator1

resetnoise

White Gaussian

Noise Generator

a

ba b

Mult5

a

ba b

Mult1

0

Constant8

0.01019287109375

Constant7

0.01019287109375

Constant6

0

Constant5

0

Constant4

0

Constant3

0

Constant2

0

Constant1

R1

I1

R2

I2

Real

Imag

Complex Addition

R1

I1

R2

I2

Real

Imag

CMULT1

R1

I1

R2

I2

Real

Imag

CMULT

R1

I1

R2

I2

Real

Imag

4

In4

3

In3

2

In2

1

In1

12

h22_i

11

h22_r

10

h21_i

9

h21_r

8

h12_i

7

h12_r

6

h11_i

5

h11_r

4

Rx2_I

3

Rx2_R

2

Rx1_I

1

Rx1_RIn1

In2

In3

In4

Out1Out2

h11_rh11_ih12_rh12_i

antennas 1

In1

In2

In3

In4

Out1Out2

h21_rh21_ih22_rh22_i

antenaas 2

4

ant2_I

3

ant2_R

2

ant1_I

1

ant1_R

AW

GN

1

an

t1_

rea

l

1

en

ab

le1

den

qz

-1

Re

giste

r9

den

qz

-1

Re

giste

r8

den

qz

-1

Re

giste

r7

den

qz

-1

Re

giste

r6

den

qz

-1

Re

giste

r5

den

qz

-1

Re

giste

r4

den

qz

-1

Re

giste

r3

den

qz

-1

Re

giste

r2

den

qz

-1

Re

giste

r15

den

qz

-1

Re

giste

r14

den

qz

-1

Re

giste

r13

den

qz

-1

Re

giste

r12

den

qz

-1

Re

giste

r11

den

qz

-1

Re

giste

r10

den

qz

-1

Re

giste

r1

den

qz

-1

Re

giste

r

sel

d0

d1

d2

d3

d4

d5

d6

d7

d8

d9

d1

0

d1

1

d1

2

d1

3

d1

4

d1

5

en

z-1

Mu

x

ab a

b

Mu

lt

do

ut

LF

SR

1

en++

Co

un

ter

ca

stz

-20

Co

nve

rt1ca

stz

-31

Co

nve

rt

0.0

62

5

Co

nsta

nt

16

In1

6

15

IN1

5

14

IN1

4 13

IN1

3

12

IN1

2

11

IN1

1

10

IN1

0

9

IN9

8

IN8

7

IN7

6

IN6

5

IN5

4

IN4

3

IN3

2

IN2

1

IN1


169

4.2 Receiver Section

4.2.1 Fast Fourier Transform (FFT)

In the first, the received two complex signals are converted into 16 parallel samples.

It is required two converters for each received signal one for real and the other for

imaginary part. The total 4 serial to 16 parallel converters required. Secondly, the

parallel samples are entered into FFT to recover the original modulating signal and after

that re-back to serial sample. Fig. 26 shows XSG block diagram of FFT. XSG block of

FFT is identical to IFFT block only difference the twiddle factor becomes conjugate.

Also serial to parallel and parallel to serial is identical to Figs. 15 and 25 respectively

only difference is setting times.

Figure 26. XSG block diagram of FFT.

4.2.2 MMSE Signal Detection

Fig. 27 shows the XSG block diagram of MMSE 2×2 MIMO detection. We assume

here the channel matrix is perfect estimated, therefore the coefficients of H matrix is

directly entered into the MIMO detection.

Figure 27. XSG block diagram of MMSE detector.

4

rx2_imag

3

rx2_real

2

rx1_imag

1

rx1_real

In1Out1

sqrt

a11_r

a11_i

a12_r

a12_i

a21_r

a21_i

a22_r

a22_i

b11_r

b11_i

b12_r

b12_i

b21_r

b21_i

b22_r

b22_i

z11_r

z11_i

z12_r

z12_i

z21_r

z21_i

z22_r

z22_i

matrix multiplication

In1In2In3In4In5In6In7In8

Out1

Out2

determinant

a11_r

a11_i

a12_r

a12_i

a21_r

a21_i

a22_r

a22_i

z11_r

z11_i

z12_r

z12_i

z21_r

z21_i

z22_r

z22_i

adjoint matrix

a op

Reciprocal

a

ba b

Mult5

a

ba b

Mult4

a

ba b

Mult3

a

ba b

Mult2

a

ba b

Mult1

a

ba b

Mult

a11_r

a11_i

a12_r

a12_i

a21_r

a21_i

a22_r

a22_i

z11_r

z11_i

z12_r

z12_i

z21_r

z21_i

z22_r

z22_i

Hermitian

ca

st

Convert1

98.039199829101563

Constant5

98.039199829101563

R1I1R2I2

Real

Imag

Complex addition2

R1I1R2I2

Real

Imag

Complex addition

R1I1R2I2

Real

Imag

CMULT3

R1I1R2I2

Real

Imag

CMULT2

R1I1R2I2

Real

Imag

CMULT1

R1I1R2I2

Real

Imag

CMULT

a

ba + b

AddSub3

a

ba + b

AddSub2

a

ba + b

AddSub1

a11_ra11_ia12_ra12_ia21_ra21_ia22_ra22_ib11_rb11_ib12_rb12_ib21_rb21_ib22_rb22_i

w11_r

w11_i

w12_r

w12_i

w21_r

w21_i

w22_r

w22_i

A*B1

12

Rx2_i

11

Rx2_r

10

Rx1_i

9

Rx1_r

8

h22_i

7

h22_r

6

h21_i

5

h21_r

4

h12_i

3

h12_r

2

h11_i

1

h11_r

HH

HHH HHH T=

Adjoint(HHH )HH

Ty

1/|determinant|

2

Out2

1

Out1

Din

I_dataI_data1I_data2I_data3I_data4I_data5I_data6I_data7I_data8I_data9I_data10I_data11I_data12I_data13I_data14I_data15

S2P5

Din

I_dataI_data1I_data2I_data3I_data4I_data5I_data6I_data7I_data8I_data9I_data10I_data11I_data12I_data13I_data14I_data15

S2P

IN1IN2IN3IN4IN5IN6IN7IN8IN9

IN10IN11IN12IN13IN14IN15In16

Imag1

P2S_3

IN1IN2IN3IN4IN5IN6IN7IN8IN9

IN10IN11IN12IN13IN14IN15In16

real1

P2S_2

R1R2R3R4R5R6R7R8R9

R10R11R12R13R14R15R16

I1I2I3I4I5I6I7I8I9

I10I11I12I13I14I15I16

r1r2r3r4r5r6r7r8r9r10r11r12r13r14r15r16i1i2i3i4i5i6i7i8i9i10i11i12i13i14i15i16

FFT1

2

In2

1

In1


170

4.2.3 16-ADQAM Demodulator

XSG block diagram of 16-ADQAM demodulation is shown in Fig. 28. This system

is implemented according to (7-10). Fig. 29 shows XSG block of bit detection that is

implemented according to (9) and (10). The precision format of are 20 fixed

points with 16 fractional bits. Cast blockset needs to convert 20 fixed points precision to

6 fixed points with 0 fractional bits.

Figure 28. XSG block diagram of 16-ADQAM demodulation.

a) Bit Detection (b0 b1) b) Bit Detection (b2 b3)

Figure 29. XSG block diagram of bit detection module.

4.2.4 Block Deinterleaver

The same block interleaver can be used to deinterleaver and recover the original

stream bits and its addressing.

Cp_Imag

Dp_Real

Dp_Imag

Cp_Real

Cp_Imag

Cp(n-1)

1

y

1

enable1

M1_R

M1_Im

b2

b1

bits detection1

M2_R

M2_Im

b0

b1

bits detectionsgn

Threshold3

sgn

Threshold2

sgn

Threshold1

sgn

Threshold

d

enqz

-1

Register8

d

enqz

-1

Register7

d

enqz

-1

Register6

d

enqz

-1

Register5

d qz-1

Register4

d qz-1

Register3

d qz-1

Register2

d qz-1

Register1

p s

Parallel to Serial

a

ba b

Mult5

a

ba b

Mult4

a

ba b

Mult3

a

ba b

Mult2a

ba b

Mult1

a

ba b

Mult

castz

-15

Convert4

cast

Convert3

cast

Convert2

cast

Convert1

cast

Convert

-1

Constant3

-1

Constant2

1.4141998291015625

Constant1

2.828399658203125

Constant

hi

lo

}

Concat

r1

i1

r2

i2

real

imag

C multi. 20 fix2

r1

i1

r2

i2

real

imag

C multi. 20 fix1a

b

a - b

AddSub1

a

b

a - b

AddSub2

rec_I

1

rec_R

R1

R2

2

b1

1

b2

[a:b]

Slice1

[a:b]

Slice

a

b

a = b

Relational7

a

b

a = b

Relational6

a

b

a = b

Relational5

a

b

a = b

Relational4

a

b

a = b

Relational3

a

b

a = b

Relational2

a

b

a = b

Relational1

a

b

a = b

Relational

sel

d0

d1

Mux2

sel

d0

d1

Mux1

sel

d0

d1

Mux

nor

Logical4

and

Logical3

nand

Logical2

nand

Logical1

and

Logical

3

Constant9

0

Constant8

-16

Constant7

1

Constant6

0

Constant5

16

Constant4

0

Constant3

16

Constant2

0

Constant12

0

Constant11

2

Constant10

0

Constant1

2

M1_Im

1

M1_R

2

b1

1

b0

[a:b]

Slice1

[a:b]

Slice

a

b

a = b

Relational7

a

b

a = b

Relational6

a

b

a = b

Relational5

a

b

a = b

Relational4

a

b

a = b

Relational3

a

b

a = b

Relational2

a

b

a = b

Relational1

a

b

a = b

Relational

sel

d0

d1

Mux2

sel

d0

d1

Mux1

sel

d0

d1

Mux

nor

Logical4

and

Logical3

nand

Logical2

nand

Logical1

and

Logical

3

Constant9

0

Constant8

-4

Constant7

1

Constant6

0

Constant5

4

Constant4

0

Constant3

4

Constant2

0

Constant12

0

Constant11

2

Constant10

0

Constant1

2

M2_Im

1

M2_R


171

4.2.5 Viterbi Decoder

Fig. 30 shows XSG block diagram of Viterbi decoder. In the first the serial bits it is

converted to parallel 2 bits and then using Viterbi decoder version 7.01 Xilinx blockset

to decode the signal. The parameters of the block are constrain length=7, hard coding,

output rate=2 and code generator [133 171] in octal form.

1

Output

1

enable4

1

enable3

1

enable2

data_in0

data_in1

rst

en

data_out

Viterbi Decoder 7.0 1

[a:b]

Slice1

[a:b]

Slice

s

rstp z

-1

Serial to Parallel

d

en

q z-1

Register1

d

en

q z-1

Register

castz

-255

Convert5

castz

-158

Convert4

castz

-313

Convert3

2

reset

1

input

Figure 30. XSG block diagram of Viterbi decoder.

4.2.6 Descrambling Using Chaos

The block diagram of deciphering is identical to that at transmitter the only different

is the pseudo random bit generator followed by delay components. This delay

component must be found by time synchronization between the transmitter and the

receiver. This work does not exist here.

5. Matlab Simulation Results

The MIMO-OFDM system is simulated using Matlab 7.12 with the following

parameters: 16 subcarrier numbers, convolutional code (7 constraint length, ½ code rate

and [133 171]octal generator polynomial) and 2×2 MMSE MIMO detection. Fig. 31

shows the performance comparison of MIMO-OFDM under flat fading channel with

and without channel coding. We assume in this simulation the channel is perfect

estimated. It is seen that from this figure at BER=10-3

, there is 7 dB gain can be added

by using convolutional code.

Figure 31. Performance of MIMO-OFDM system over flat fading channel.

0 5 10 15 20 2510

-4

10-3

10-2

10-1

100

SNR (dB)

BER

MIMO-OFDM MMSE

MIMO-OFDM MMSE with convolutional code


172

6. Xsg Simulation Results

The Resulting waveforms that explain the outputs of each component in MMSE

MIMO-OFDM system that are implemented using XSG are plotted using MATLAB

program. Fig. 32 shows XSG simulation waveforms of ciphering system. Xn and Yn are

chaos signals used to generate the key signal, PRBG where is adding mod 2 with

original data source to produce ciphered message. The bit rate is remaining the same.

Time(s)

Figure 32. XSG simulation waveforms of the ciphering system.

Fig. 33 shows XSG simulation waveforms of convolutional code. It can be seen from

this figure the rate is increased by two to become 200 Mbps. Fig. 34 Shows

Experimental signals of Matrix Interleaver for 4×4 matrix. The control signal is used to

start loading the signals to registers to become serial at the output of multiplexer. This

signal becomes on every 16 bits cycle.

The output rate remains the same. Fig. 35 shows XSG simulation waveforms of 16-

ADQAM modulation. As can be seen from this figure the rate at the output of serial to

parallel converter is 50 M samples/sec (20 ns).

The 16-ADQAM signal is parsing into two signals one for each channels to become

the rate 100 M samples/sec (40 ns). Fig. 36 shows the OFDM transmitted complex

signals the received complex signal and the MMSE detection complex signal of the first

channel. Fig. 37 shows the comparison results between transmitted and received signals.

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Xn Choas Signal

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Yn Choas Signal

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Key Stream PRBG using Chaos

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Original Data Message

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Ciphered Message


173

Time(s)

Figure 33. XSG simulation waveforms of convolutional code.

Time(s)

Figure 34. XSG simulation waveforms of Matrix Interleaver for 4×4 matrix.

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Input Data into Interleaver

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Control Signal

0 5 10 15 20 25 30 35 40 45 500

0.5

1

output of Interleaver

0 10 20 30 40 50 600

1020

Serial to Parallel (4 bits)

0 10 20 30 40 50 60-4-2024

16-ADQAM Real signal

0 10 20 30 40 50 60-4-2024

16-ADQAM Imaginary Signal

0 10 20 30 40 50 60-4-2024

16-ADQAM Real Signal of Antenna 1

0 10 20 30 40 50 60-4-2024

16-ADQAM Real Signal of Antenna 2

0 10 20 30 40 50 60-4-2024

16-ADQAM Imag.Signal of Antenna 1

0 10 20 30 40 50 60-4-2024

16-ADQAM Imag. Signal of Antenna 2

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Input Data

0 5 10 15 20 25 30 35 40 45 500

1

2

3

Output Convolutional Code

0 5 10 15 20 25 30 35 40 45 500

0.5

1

Output of Parallel to Serial

Figure 35. XSG simulation waveforms of 16-ADQAM modulation.

Time(s)


174

Figure 36. XSG simulation waveforms of OFDM and MMSE detection.

Figure 37. Comparing transmitted and received data.

7. Synthesis Report

After completing system design and simulation results, VHDL Code or Bitstream

file is generated using select device which is virtex 4. Fig. 38 shows the parameters of

80 100 120 140 160 180 200

-1

0

1

OFDM Real Signal of channel 1

80 100 120 140 160 180 200

-1

0

1

OFDM Imag. Signal of channel 1

80 100 120 140 160 180 200-1

0

1

Received Real Signal of Channel1

50 100 150 200 250 300-0.5

0

0.5Received Imag. Signal of Channel 1

120 140 160 180 200 220 240 260 280 300-5

0

5MMSE detection Real Signal of Channel 1

120 140 160 180 200 220 240 260 280 300-5

0

5

Time (sec)

MMSE detection Imag. Signal of Channel 1

0 10 20 30 40 50 60 70 80 90 100-0.5

0

0.5

1

1.5Transmitted Signal

250 260 270 280 290 300 310 320 330 340 350-0.5

0

0.5

1

1.5

Time (sec)

Received Signal


175

system generator. Resources used for the system are found by using ISE 14.1 program

as shown in Table 3.

Figure 38. System generator parameters.

Table 3. Development system resources

8. Conclusions

In this paper, 2×2 MMSE MIMO-OFDM system is implemented using Xilinx

system generator with the following adding features: increasing security of the system

using chaos stream ciphering, using 16-ADQAM modulation to solve the ambiguity problem

and implement FFT in pipelining way. The results show that the signal is recovered in correctly

at the receiver side and the VHDL code file can be generated in successful when Xilinx Virtex-4

device is used.


176

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