Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs
Formation of Sub-10 nm width InGaAs finFETs of 200 nm Height by Atomic Layer Epitaxy
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Formation of Sub-10 nm width InGaAs finFETs of 200 nm Height by Atomic Layer Epitaxy*D. Cohen-Elias1, J.J.M. Law1, H.W. Chiang1, A. Sivananthan1, C. Zhang1, B. J. Thibeault1, W.J. Mitchell1, S. Lee1, A.D. Carter1, C.-Y. Huang1, V. Chobpattana2, S. Stemmer2, S. Keller1, M. J.W. Rodwell1
IEEE Device Research Conference, June 24-27 2013, Notre Dame
1ECE and 2Materials DepartmentsUniversity of California, Santa Barbara, CA
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Goal: FinFET with 2-4 nm Body ThicknessIntel Lg=60nm III-V FinFET (IEDM 2011)
30 nm fin: too thick at 60 nm gate length
For good electrostatics,need fin thickness ~ (gate length/2)S. H. Park et al., NNIN Symposium Feb 2012.
8nm gate length → need <4 nm thick fin
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Goal: Tall Fins for High Drive Current
Goal: fin height >> fin pitch (spacing)
Goal: large on-current from small transistor footprint.
pitch finheight finJ
width transistorcurrent
surface
Heig
ht
Pitch
S
D
Transistor Width
J surfJ su
rfJ surfJ su
rf
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Goal: Fins with Integrated N+ Source/Drain
regrowth→ small S/D pitch → High Integration Density
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Why Not Dry-Etch a 2nm Fin ?
serious process challenges
Goal: 2-4 nm thickness, 100+ nm height
*metallization-induced damage increases Dit: Burek et al, JVST B. 29,4, Jul/Aug 2011;Dry-etching may well do similar surface damage
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FinFETs by Atomic Layer Epitaxy
Fin thickness defined by Atomic layer epitaxy (ALE)
thin, tall fins → few-nm Lg , high currents
Fin~8nm
HfO2→ nm thickness control
→ 200 nm high fins
Fin height defined by sidewall growth
TiN
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ALE-Defined finFET: Process Flow
Fin Template Channel ALE Dummy Gate
S/D RegrowthRelease Fins
Gate DielectricGate MetalS/D Metal
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Fin Template
(011)
SiN hard mask: Ridges oriented along [011]
H3PO4 : HCL etch: facet-selective, material-selective forms vertical (011) sidewalls stops on InGaAs etch-stop
InGaAs etch-stop: defines template height→ defines fin height
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Channel Growth by Atomic Layer Epitaxy
Using UCSB MOCVD :1.7 Monolayer of InGaAs / Cycle(Not true ALE mode)
1 monolayer growth per cycle.
30 31 32 33100
102
104
106
Angle
Inte
nsity
100 cycles of 10sec pulse InGaAs growth @ 450C Thickness~50nm
TBA flow H2 flow TMI+ TMGa flow
H2 flow→ → →
InGaAs monolayer ~ 2.9A
→S.P. DenBaars, P.D. Dapkus Journal of Crystal Growth, 98 (1989)
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Channel Growth by Atomic Layer Epitaxy
Growth: lattice-matched InGaAs 20 ALE cycles → <10 nm channel
Details: one ALE cycle = 10 sec TMGa/TMI, 10 sec H2 , 10 sec TBAs, 10 sec H2
450 C growth
Masked growth: no InGaAs growth on top of template
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Dummy Gate: Patterns Source and Drain
HSQ
Mask HSQ* : E-beam definable SiO2
ALD Al2O3 mask sub-layer: adhesion
*HSQ: Hydrogen silsesquioxane
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Source Drain Regrowth
Sour
ceD
rain
HSQ
MOCVD Regrowth 600C lattice-matched N+ InGaAs, 5*1019/cm3 doping
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S/D Regrowth: Filling vs. Sidewall Regrowth
Present process: S/D regrowth partly fills spaces between fins
Target process: S/D sidewall regrowth by ALE → large contact area → low access resistance
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Source Drain Regrowth
Sour
ceD
rain
HSQ
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Fin Release
fin release: H3PO4:HCl selective wet-etch etches InP stops on InGaAs
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Fin Release
fin with N+ regrowth
fin without N+ regrowth
N+
N+
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Why Not Release Fins Before S/D Regrowth ?
Images of released ~10 nm fins:
S/D regrowth provides mechanical support
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ALD Gate Dielectric, ALD Gate Metal
HfO2 and TiN ALD gate Stack
Source
Drain
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Source and Drain Metal
Source Metal
Drain Metal
Gate
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TEM Images
Fin~8nm
HfO2
TiN
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Where is the DC Data ?
Present finFETs: very high leakage
Planar FET: thermal Ni gatefinFET: ALD TiN gate
interface damage ?
Planar FET: 100 interfacefinFET: 011 interfaces
ALD surface preparation ?-0.2 0.0 0.2 0.4 0.6
0.00.20.40.60.81.01.21.41.61.8
Gm
(mS/m
)
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8 40 nm 70 nm 90 nm
VDS = 0.5 V
Planar InAs/InGaAs MOSFETLee et al, 2013 VLSI symposium
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3-D Transistors to Extend Moore's LawLundstrom: high S/D tunneling @ 4-7 nm Lg
→ increase m* as Lg decreases
Implication: FETs won’t improve with scaling increased m* → decreased vinj
→ decreased Ion , increased CV/I
Alternative: 3-D integration
If we scale only to increase the IC packing density, why reduce Lg ?
height>> pitch
...or other geometries...
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FinFETs by Atomic Layer EpitaxyALE-defined fin → few-nm thick channels → scaling to 8nm gate length
S
D
pitchfin heightfin J
widthtransistorcurrent
surface
J surfJ su
rfJ surfJ su
rf
Fin~8nm
HfO2
TiN
200 nm fin height →enhance drive current
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Thank You
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