Formal Verification for ASIC & System-On-Chip Designs

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Formal Verification Formal Verification for ASIC & System-On-Chip Designs Verplex Systems, Inc. & 丸紅ソリューション株式会社 1999年7月

Transcript of Formal Verification for ASIC & System-On-Chip Designs

Page 1: Formal Verification for ASIC & System-On-Chip Designs

Formal VerificationFormal Verificationfor ASIC & System-On-Chip

Designs

Verplex Systems, Inc.&

丸紅ソリューション株式会社1999年7月

Page 2: Formal Verification for ASIC & System-On-Chip Designs

従来の動的検証 : シミュレーション静的検証 : 論理等価性比較チェック

a b x0 00 11 01 1

0110 a

bx

a´

b´b

ax

シミュレーションは、テストパターンにより回路の動作が決まる

ab

x

a´

b´b

ax

数学的に回路等価を証明

多大な時間が必要多大な時間が必要

僅かな時間僅かな時間

Page 3: Formal Verification for ASIC & System-On-Chip Designs

フォーマルベリフィケーションの有効性

•• フォーマルベリフィケーションの種類フォーマルベリフィケーションの種類– 論理的等価性チェック

– プロパティチェック

•• フォーマルベリフィケーションのメリットフォーマルベリフィケーションのメリット– シミュレーション用パターン不要

– 比較用にシミュレーションを複数回実行するより遥かに短時間で結果を入手 ( x 数十 ～ over x 500 )

– ２つの回路を比較し、論理的な等価性を完全チェック

– カウンターサンプルや動作の判っている順序回路との比較による動作検証 (デザインプロパティチェック )

Page 4: Formal Verification for ASIC & System-On-Chip Designs

フォーマルベリフィケーションの活用フロー(等価性チェック)

RTLRTLDesignDesign

Gate-LevelGate-Level Design Design

Synthesis ECO, DFT P & R

Gate-LevelGate-Level Design Design

Gate-LevelGate-Level Design Design

Switch-LevelSwitch-Level Design Design

Tuxedo

RTLRTLDesignDesign

Tuxedo Tuxedo

Page 5: Formal Verification for ASIC & System-On-Chip Designs

Verplex社 製品ファミリー :TuxedoTuxedoシリーズ

• 等価性チェッカー

– Tuxedo-LEC ( Logic Equivalence Checker )GUIツール / ダイアグノシス＆デバッグ

• <Tuxedo-LDD> ( Logic Diagnosis/Debugging )

• トランジスタファンクション機能抽出とゲートへのリ･プレゼンテーション

– Tuxedo-LTX ( Logic Transistor Extraction )

• モデルチェッカー ( Logic Modeling Checker )– NEXT Release

Page 6: Formal Verification for ASIC & System-On-Chip Designs

Tuxedo-LEC 作業フロー1

Golden Revised

Design andLibrary Input

ConstraintsSpecification

Circuit flatteningand

key-point mapping

Library

SETUPmode

Page 7: Formal Verification for ASIC & System-On-Chip Designs

Tuxedo-LEC 作業フロー2

FunctionalComparison

ComparedReports

Diagnosis &Debugging

LECmode

Page 8: Formal Verification for ASIC & System-On-Chip Designs

Tuxedo-LEC- 入力 & コンパイル

• ソースレベル : RTL, Gate, Transistor レベル

• 入力ソース: Verilog, VHDL，NDL and Spice

• 入力ライブラリ: Verilog ( UDPを含む )

VHDL

• RTL 比較での “Don’t-cares” 抽出･対応

• Directive ( Full_case, Parallel_case,Translate_on/off )

• 4 値サポート( 0, 1, x, z )

• 言語混在可能

Page 9: Formal Verification for ASIC & System-On-Chip Designs

LDD 機能 - デバッグ/ダイアグノシス

• ダイアグノシス＆デバッギング– Gate to Gate

• エラー候補箇所の自動認識

• 論理コーン内の不一致点を回路図ビューワーで表示

– RTL to Gate• RTLソースを回路図ビューワーで表示

• ソースレベルでエラー候補箇所を自動認識

– エラー候補箇所の自動ハイライト表示

– 回路図上にエラーパターンを表示

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LDD (GUI)

Page 11: Formal Verification for ASIC & System-On-Chip Designs

Tuxedo-LTXについて

• 自動的にトランジスターのファンクションネットリストを抽出

• 各ノードにブーリアンをアサイン

• Verilogのファンクションモデルとして出力

Page 12: Formal Verification for ASIC & System-On-Chip Designs

Tuxedo-LTX利用例

• SPICEに比べて桁違いのスピード

• switch-level Verilogの高速シミュレーション

• accelerators, emulators, cycle-based simulator等の高速化も可能

Tuxedo-LTXTuxedo-LTX

TransistorNetlist

PhysicalLayout

Simulator/Accelerator/Emulator/

Cycle-based

PhysicalExtraction

Vectors ExtractedVerilogModel

Page 13: Formal Verification for ASIC & System-On-Chip Designs

RTL-Gate :Benchmark Example 1RTL-Gate :Benchmark Example 1

• Hewlett-Packard• Hewlett-Packard

Platform: HP with 500MB RAM

階層階層 RTL to RTL to フラットフラット gate / dongate / don’’t carest cares無し無しSize Runtime Memory700K gates 40min. 700MB

Note:don’t caresの有り無しは、パフォーマンスに大きく影響

Page 14: Formal Verification for ASIC & System-On-Chip Designs

Gate-Gate :Benchmark Examples 1

• Application: Manual engineering changes

• Circuit: Graphics chip module

• Size: 350K gates

• Runtime: 4 minutes 51 seconds (UltraSparc 10)

• Memory: 187 MB

• Application: Clock tree synthesis

• Circuit: Video phone (whole chip)

• Size: 500K gates

• Runtime: 7 minutes 30 seconds (UltraSparc 10)

• Memory: 215 MB

Page 15: Formal Verification for ASIC & System-On-Chip Designs

お問い合わせ

丸紅ソリューション株式会社

産業システム事業部

事業一部 EDA営業二課

東京 : (03) 5778ｰ8551

大阪 : (06) 6395ｰ5502


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