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3 SPACE VECTOR MODULATION FOR FOUR-LEG VOLTAGE
SOURCE INVERTERS
3.1 FOUR-LEG VOLTAGE SOURCE INVERTER
The schematic diagram of a four-leg inverter is shown in Fig. 3.1. This topology is
known to produce balanced output voltages even under unbalanced load conditions[10].
Due to the additional leg, a four-leg inverter can assume sixteen topologies which is twice
the number of topologies a conventional three-leg inverter can assume[11]. These
topologies are shown in Fig. 3.2. The topologies are similar to the three-leg inverter with
the fourth leg being connected either to the negative rail (Fig. 3.2(a)) or to the positive rail
(Fig. 3.2(b)). Each of these topologies is referred to as a switching state. Thus a four-leg
inverter can produce sixteen switching states.
p
n
ab
c
Ia
fVg
La
Lf
Fig. 3.1. Topology of a four-leg voltage source inverter.
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ab
cf
pnnn
ab
cf
ppnn
ab
cf
nppn
ab
cf
nppn
ab
cf
nnpn
ab
cf
pnpn
ab
cf
pppn
ab
cf
nnnn
p p p
ppp
p p
n n n
nnn
n n
Fig. 3.2(a). Topologies of a four-leg voltage source inverter.
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ab
cf
pnnp
ab
cf
ppnp
ab
cf
npnp
ab
cf
nppp
ab
cf
nnpp
ab
cf
pnpp
a b cf
pppp
a b cf
nnnp
pp
p
p p p
pp
n n
nnn
n n n
Fig. 3.2(b). Topologies of a four-leg voltage source inverter.
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3.2 VOLTAGE SPACE VECTORS
Space vector modulation for a four-leg voltage source inverter is based on the
representation of the phase voltage space vectors in the , , plane. Considering for
example the first topology of Fig. 3.2(a) which is repeated in Fig. 3.3 for the sake of
convenience, we see that the phase voltages Vaf, Vbf, Vcfare given by
0
0
=V
=V
= VV
cf
bf
gaf
.. (3.1)
f
p
ab
c
n
Vg
(a) (b)
Fig. 3.3(a) Topology 1 (pnnn) of a four-leg voltage source inverter.
(b)Representation of topology 1 in , , space.
The transformed voltages in the , , space can be obtained using the transformation
=
2
1
2
1
2
1
2
3
2
30
2
1
2
1
1
3
2
-
--
, T =
V
V
V
T
V
V
V
cf
bf
af
.. (3.2)
VV
V
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Thus, topology of Fig. 3.3 could be represented by the vector pnnn as shown in
Fig. 3.3(b) and in Fig 3.4(a). A similar procedure could be adopted for all the topologies of
Fig. 3.2. This would generate sixteen vectors. These are known as switching state vectors
(SSVs). These SSVs are shown in Fig. 3.4. in the space of transformed phase voltages
{Vaf, Vbf, Vcf}, where , plane is the plane in which Vaf + Vbf + Vcf = 0, and is the
axis of the zero sequence component. The tips of these vectors when projected onto the
, plane would form a regular hexagon as shown in Fig. 3.4(b).
pnnn
ppnn
npnn
nppn
nnpn
pnpn
pppn
pnnp
nnpp
npnp pnpp
ppnp
nppp
nnnp
V= Vg
ppppnnnn
V= 2 Vg/3
V= -2 Vg/3
V= -Vg
V= Vg/3
V= -Vg/3
V= 0
Fig. 3.4(a). Switching state vectors of a four-leg inverter.
1
2
3
4
5
6
V1(pnnx)
V2(ppnx)V3(npnx)
V4(nppx)
V5(nnpx) V6(pnpx)
pppx
nnnx
2Vg/3
x (p,n)
Fig. 3.4(b). Projection of the sixteen vector into , plane.
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3.3 SPACE VECTOR MODULATION
The required phase voltages at the output of the inverter could be represented by an
equivalent vector, rotating in a 3-D vector space (unlike the three-leg VSI where the
required output line voltages are represented by a vector rotating in the 2-D space). Space
vector modulation for four-leg inverter, as in a three-leg inverter involves identification of
adjacent switching state vectors, calculation of their duty-cycles and sequencing of these
vectors. The first two steps are described in detail in [10,13] are reviewed here for the
sake of completeness.
3.3.1 IDENTIFICATION OF ADJACENT VECTORS
Identification of adjacent vectors is a two step process. At first, the vector space of
Fig. 3.4(a) is divided into six triangular prisms (P1-P6). At any given instant the required
output voltage vector is present in one of these six prisms as can be seen in Fig. 3.5, where
the reference vector happens to be in prism1. The flowchart used to determine the prism
information at any given instant is shown in Fig. 3.6, where V , V are obtained from
(3.2), and is essentially the same as sector identification for the three-leg inverter.
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p n n n
p n n p
p p n p
p p n n
p p p n
n n n p
n n n n
p p p p
V r e f
Fig. 3.5. Reference vector in prism1.
V V
V V+
-+
+- -
| V 3 | V | |
Prism1 Prism2 Prism5Prism4 Prism3 Prism2 Prism6 Prism5
y y yy n n nn
| V 3 | V | | | V 3 | V | | | V 3 | V | |
Fig. 3.6. Flowchart used to determine prism information.
Once the prism information is determined the next step is to identify the
tetrahedron in which the reference vector is present. To do this each prism is further
subdivided into four tetrahedrons - thus leading to a total of 24 tetrahedrons. Each
tetrahedron is formed by three non-zero switching state vectors [11,13] as shown in Fig.
3.7 for prism1(P1). Table 3.1 shows how these tetrahedrons could be identified based on
the sign of required phase voltages at the output of the inverter. Thus the three adjacent
active vectors are determined.
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Table 3.1: Identification of tetrahedrons
Prism Tetrahedron Active Vectors Condition
T1 ppnp, pnnp, pnnn Va>0, Vb0, Vc0, Vb>0, Vc0, Vb
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pnnn
pnnp
ppnp
ppnn
[ + 0 0 ]
[ 0 - - ]
[ 0 0 - ]
[ + + 0 ]
[ - - - ]
nnnp
pppn
[ + + + ]
ppppnnnn
Vref
ppnp
pnnn
pnnp
V0X
Vref
Vref
(a) (b)
Fig.3.7(a) Prism (P1) consisting of four tetrahedrons (T1,T2,T13,T14)(b) Reference vector in tetrahedron1(T1).
3.3.2 Duty Cycle Calculation
Once the active vectors are determined, their duty-cycles are calculated based on
projections. This is illustrated for the case when the reference vector is in tetrahedron1(T1)
in Fig. 3.8, where the duty-cycles d1, d2, d3 for the active vectors ppnp, pnnp, pnnn
are obtained based on projections and the duty-cycle for the zero vector is obtained from
d0 = 1-d1-d2-d3 .. (3.3)
ppnp
pnnn
pnnp
V 0X
V ref
d3
d2
d1
Fig.3.8. Duty cycles for the active vectors.
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Under balanced load conditions the reference vector takes up a circular trajectory
in the , plane with the component being equal to zero. Under this condition the
reference vector traverses only twelve tetrahedrons (T1-T12) and the time it spends in each
tetrahedron is equal. This is indicated by the stair-case waveform in Fig. 3.9(a) where the
length of all the stairs is equal, indicating that the time spent by the reference vector in
each tetrahedron is the same. Fig. 3.9(b) shows the time spent by the reference vector in
each prism. It can be noted that since the reference vector traverses through two
tetrahedrons of a given prism consecutively; the sum of two consecutive stairs in Fig.
3.9(a) would give rise to one stair in Fig. 3.9(b).
Under small unbalance, the trajectory of the reference vector becomes elliptic, with
a varying component [10]. Under this condition the time spent by the reference vector ineach of these twelve tetrahedrons is not a constant as can be seen from Fig. 3.10(a). Fig.
3.10(b) shows the traversal of prisms under this condition.
Under balanced or small unbalanced operating conditions the reference vector
remains in only twelve tetrahedrons(T1-T12). However, during transients or during
extreme unbalance the reference vector could traverse tetrahedrons beyond twelve ( T13-
T24).
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Tetrahedrons
T1
T12
Time
Time
Prisms
P1
P6
Fig. 3.9. Traversal of tetrahedrons and prisms for a balanced load.
Time
(b)
Prisms
Time
(a)
Tetrah
edrons
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Tetrahedrons
T1
T12
Time
P
risms
P1
P6
Time
Fig.3.10. Traversal of tetrahedrons and prisms for an unbalanced load.
Time
(b)
Time
(a)
Tetrahedrons
Prisms
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3.3.3 Sequencing of Vectors
Once the active vectors are determined and the duty cycles calculated, the degrees
of freedom we have in the choice of a given modulation algorithm are
(1) The choice of the zero vector -
whether we would like to use nnnn or pppp or both,
(2) Sequencing of the vectors,
(3) Splitting of the duty cycles of the vectors without introducing additional
commutations.
Three such SVM algorithms are considered, namely:
1) The symmetric sequence - Scheme1
2) The highest current not switched sequence - Scheme2
3) The alternating zero vector sequence - Scheme3
The schemes analyzed here are similar to the ones found in literature for a three-
leg inverter operating under balanced load conditions as described in the previous chapter.
Scheme1 corresponding to SVM2, scheme2 corresponding to symmetric SVM4, and
scheme3 corresponding to SVM3. The scheme corresponding to SVM1 is not analyzed
here because it did not have any advantage under hard-switched conditions when
campared to the other schemes.
Each of these modulation schemes has been analyzed and its relative performance
with respect to switching loss and THD of the voltage at the output of the inverter is
assessed. The analysis is performed over the entire range of modulation index and for
both balanced and unbalanced load.
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3.4 MODULATION SCHEMES
3.4.1 Symmetric sequence: Scheme1
The sequence of vectors applied in this scheme is shown in Fig. 3.11 for the case
when the reference vector is in tetrahedron 1. This scheme is expected to have low THD,
as in three-leg voltage source inverter, because of the symmetry in the waveforms. The
number of commutations in one sampling period is eight.
T s
a
b
c
f
p
p
p
p
p
p
n
p
p
n
n
p
p
n
n
n
n
n
n
n
p
n
n
n
p
n
n
p
p
p
n
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
n
p
p
p
n
p
n
n
n
n
p
n
n
n
p
n
n
n
p
n
n
p
p
n
n
p
T s
d 0 d 1
2
d 2
2
d 3 d 0
2
d 3
2
d 2
2
d 1
2
d 0
4 2 4
d 0 d 1
2
d 2
2
d 3 d 0
2
d 3
2
d 2
2
d 1
2
d 0
4 2 4
p
np
n
p
n
p
n
Fig. 3.11. Phase gating signals in scheme1.
3.4.2 Highest Current Not-Switched Sequence: Scheme2
This scheme is based on the fact that the switching losses are approximately
proportional to the magnitude of the current being switched and hence it would be
advantageous to avoid switching the inverter leg with the highest instantaneous current.
This is possible in most cases, because all adjacent SSVs in a given tetrahedron differ in
the state of switches in only one leg. Hence, by using only one zero vector, nnnn or pppp
within a given tetrahedron, one of the legs does not have to be switched at all, as shown in
Fig. 3.12.
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However, since the choice of the non-zero SSVs is made based on the desired
output voltage vector and the phase and magnitude of the current is determined by the
load, it is not always possible to avoid switching the phase carrying the highest current. In
such a case the phase carrying the second highest current is not switched but the switching
loss savings are reduced. The splitting of active vectors about the zero vector as shown
below results in a significant reduction in the THD. The number of commutations in one
cycle is six.
Ts
a
b
c
f
pp
p
p
pp
n
p
p
n
n
p
p
n
n
n
p
n
n
p
pp
n
p
pp
p
p
pp
p
p
pp
p
p
pp
n
p
pp
n
p
pn
n
n
pn
n
p
pn
n
p
Ts
d d2
d2
d d2
d2
d4 4
d d2
d2
dd 22
d2
d4 4
p
n
p
n
p
n
p
n
Fig. 3.12. Phase gating signals in scheme 2.
3.4.3 Alternating Zero Vector Sequence : Scheme3
In this scheme the zero vectors (pppp, nnnn) are used alternatively in adjacent
switching cycles so that the effective switching frequency is halved, as shown in Fig. 3.13.
However, the sampling period is still Ts, same as in the other schemes. The number of
commutations in one Ts is four and hence the switching losses are expected to reduce.
Current THD is significantly higher due to the existence of the harmonics at half the
sampling frequency.
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a
b
c
f
pnnn pnnp ppnp pppp ppnp pnnp pnnn nnnn
Ts Ts
d3 d2 d1 d0 d1 d2 d3 d0
p
n
p
np
n
p
n
Fig. 3.13. Phase gating signals in scheme3.
3. 5 ANALYSIS
3.5.1 Performance Comparison for Balanced Loads:
3.5.1.1 Total Harmonic Distortion:
The modulation schemes are analyzed for their harmonic performance using the
algorithm developed in the previous chapter for a three-leg inverter where the Fourier
components of the output voltage are calculated by summing up the Fourier components of
the individual pulses. The harmonics of the line currents are calculated by using the load
impedance information. This procedure is illustrated here for scheme1.
The neutral point potential (Vf) can be 0 or Vg, depending on the SSVs. Hence the
phase voltages (Vaf, Vbf, Vcf - voltages between the inverter output and the neutral point)
can be accurately calculated as shown in Table 3.2 for tetrahedron 1.
Decomposition of the phase voltage switching waveform for scheme1 into sum of
pulses with period To as explained in chapter 2 is shown in Fig. 3.14 where a typical phase
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voltage is decomposed in the kth switching interval from beginning of the phase voltage
period, where
10 -f
fk
o
s .(3.4)
Comparing each of the component pulses with Fig. 2.13 one can find that for the
pulse in Fig. 3.14(b)
(3.5)
for the pulse in Fig. 3.14(c)
..(3.6)
d3/2
Vg
(k-1)Ts kTs
0d3/2
Vg
(k-1)Ts kTs
0d3/2
d3/2
Vg
(k-1)TskTs
00.5+d0/4
d0/4+d1/2+d2/2
(a) (b) (c)
Fig. 3.14. Phase voltage decomposition in one sampling period.
The duty cycles d1, d2, d3 and d0 are calculated as explained in section 3.2 and the
Fourier components of these pulses are obtained from equations (2.7) and (2.8).
Table 3.2. Output voltage pulse in tetrahedron1: Scheme1
SSVs pppp ppnp pnnp pnnn nnnn pnnn pnnp ppnp pppp
Duty cycle d0/4 d1/2 d2/2 d3/2 d0/2 d3/2 d2/2 d1/2 d0/4
Va V V V V 0 V V V V
Vf V V V 0 0 0 V V V
Vaf 0 0 0 V 0 V 0 0 0
gmsmm VVTddd
kTd
d =
+++== ,.
2241,
2
2103
gmsmm VVTd
kTd
d =
++== ,.42
11,
2
03
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Fig. 3.15 shows the variation of THD (of phase voltage and phase current) with
modulation index for all the schemes. The results are similar to the three-leg inverter.
0 0.866Modulation index
(a)
0 Modulation index 0.866
(b)
Fig. 3.15. Total harmonic distortion of (a) Phase voltage ,( b) phase current (fs/fo = 36).
3.5.1.2 Switching loss
The switching losses are assumed to be proportional to the product of the voltage
across the switch and the current through the switch at the instant of switching. Since the
voltage across the switch is the bus voltage, it is considered to be a constant. Thus the
losses are proportional to the current during switching.
Modulation index
Modulation index
THD
ofphasevoltage
THD
ofphasecurrent
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Under balanced load conditions the neutral leg carries only the high frequency
ripple as shown in Fig. 3.21(a). Hence the switching losses are expected to be similar to
the three leg inverters. Losses for schemes 1 and 3 are independent of the load whereas
for scheme 2 the losses depend on the load power factor and its loss performance has
been optimized as described in section 3.5.2
Fig. 3.16 shows the relative variation of switching losses with load power factor
for the three schemes.
Load pow er factor
Relativeswitching
loss
Fig.3.16. Relative switching losses as a function of load power factor angle.
3.5.2 Performance Comparison for Unbalanced Load
3.5.2.1 Total Harmonic Distortion
Depending on the load and load power factor angle (lpf) there are several cases of
unbalance that could be studied. Two cases are presented here.
(1) Load power factor angle unbalance: Here each of the three phases are assumed
to be carrying full load current, however the lpf of phase a is assumed to vary from
90
to 90 . Fig. 3.17 shows the variation of THD of phase a voltage when the lpf is leading
and lagging. The curves are not smooth because the THD was calculated at discrete points.
Relativeswitching
loss
Load power factor angle
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(a)
(b)
Fig. 3.17 Variation of THD of phase voltage with load power factor
(a)leading, b) lagging(2) Load power unbalance : In this case the lpf is assumed to be unity, however the
load power taken by phase a is assumed to vary from 100 % to 10 %. Fig. 3.18 shows the
variation of THD of phase a voltage with load power. It can be observed from the figure
that the THD increases with decrease in load power but variation is very small.
Load power factor angle
Load power factor angle0 90o
90o
0
THD
ofphasevo
ltage
THD
ofphasevoltage
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Load power
Fig. 3.18 Variation of THD of phase voltage with load power
3.5.2.2 Switching Losses
Load power factor angle unbalance: Here though the load currents are all of the same
magnitude, the currents through the filter inductors and hence the switches are dependent
on the load power factor. Fig. 3.19 shows the variation of total switching losses, of all the
switches, with load power factor. This shows that with increasing load power factor angle
unbalance the switching losses invariably tend to increase. The extent to which they
increase, however, is dependent on the exact power factor angle and also whether it is
leading or lagging.
Load power factor angle
(a)
THDo
fphasevoltage
10%100%
Relativeswitchingloss
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Load power factor angle
(b)
Fig. 3.19 Relative switching loss for
(a)Leading load power factors(b)Lagging load power factors
3.6 SIMULATION AND EXPERIMENTAL RESULTS
A 150 kW inverter was simulated for both balanced and unbalanced load
conditions. The parameters used wereLa = 1.25 mH, Lf = 0, C = 210 uF, Vg = 850 V, fo =
60 Hz, fs = 2160 Hz. The phase current waveform and its spectrum for each of the schemes
for balanced load conditions are shown in Fig. 3.20
The simulated phase currents, output voltages and the current through the neutral
leg for balanced and unbalanced load conditions are shown in Fig. 3.21. Scheme 1 was
used for Fig. 3.21. The load was assumed to be 255 A peak for the balanced case. For the
unbalanced case the load currents were assumed to be 60127.5,0255 A A, and
075.63 A for the three phases a, b, and c respectively.
Based on the analysis and simulation, scheme2 was implemented on a prototypeinverter and the results are as shown in Fig. 3.22.
Relative
switchingloss
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(a) (b)
Fig. 3.20 a) Phase currents and b) Spectrum of phase currents for the three space vector
modulation schemes.
Fig. 3.21. Line currents, output voltages and current through neutral leg for
a) Balanced load, b) Unbalanced Load.
Line Currents
Output Voltages
Neutral Current
Scheme1
Scheme2
Scheme3
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(b)
(a)
fs
20V/div
20db/div
Fig.
3.22.Experimental output voltage and spectrum of output voltage for scheme 2.
( Vg = 75V, fs/fo = 40)
20dB/div
20V/div
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3.7 PERFORMANCE SUMMARY
This chapter analyzed the most important modulation schemes for both balanced
and unbalanced load conditions for a four-leg inverter. The analysis was performed over
the entire range of modulation index and over the entire range of load power factor for the
balanced load conditions. Two typical unbalance conditions - load power factor angle and
load magnitude, were studied for harmonic distortion and switching losses. Table 3.3
summarizes the results of the analysis. The analysis clearly brings out the trade offs to be
observed between the THD and switching losses i.e., a scheme with low THD usually has
high losses. The study of unbalanced load conditions reveals that both THD and losses
increase. Overall scheme 1 should be used at low switching frequencies where the
switching loss is small. At high switching frequencies scheme 2 is recommended
Table 3.3. Relative performance of various modulation schemes (four-leg)
Modulation Schemes Scheme-1
Symmetric
Scheme-2. Highest
Current not Switched
Scheme-3. Alternating
Zero Vector
No. of commutations in Ts 8 6 4
No. of switching states in Ts* 10 7 4
Dominant Harmonic f s fs fs/2
Balanced LoadRelative Losses 1 0.5-0.63
**0.5
THD at low mod. Index Least
THD at high mod. Index Least Highest
Unbalanced LoadRelative Losses-lpf
(leading 00-90
0)
1-1.41 0.5-0.95 0.5-0.7
Relative Losses-lpf
(lagging 00-90
0)
1-1.58 0.5-0.95 0.5-0.79
THD at leading lpf***
Least HighestTHD at lagging lpf
***Least Highest
THD at varying loads***
Least Highest* Important in the design of digital modulator.
** Depending on load power factor.
*** Exact values are dependent on modulation index