8/16/2019 Floorplanning Tips

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Floorplanning Tips:

What is Floorplan?

Die Size Estimation

 pin/pad locationhard macro placement

 placement and routing blockage

location and area of the soft macros and its pin locations

number of power pads and its location.

 Note! For block le"el Die size and #in placement comes from $%#

Fl&line anal&sis is re'uired before placing the macros

While fi(ing the location of the pin or pad alwa&s consider the surrounding en"ironment with

which the block or chip is interacting.

$his a"oids routing congestion and also benefits in effecti"e circuit timing

#ro"ide sufficient number of power/ground pads on each side of the chip for effecti"e power

distribution.

)n deciding the number of power/ground pads* #ower report and )+!drop in the design should

also be considered

%rientation of these macros forms an important part of floorplanning

,reate standard cell placement blockage -ard lockage0 at the corner of the macro because this

 part is more sensiti"e to routing congestion.

using the proper aspect ratio -Width /eight0 of the chip

For placing block!le"el pins*

First determine the correct la&er for the pins

Spread out the pins to reduce congestion.

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1"oid placing pins in corners where routing access is limited

2se multiple pin la&ers for less congestion

 Ne"er place cells within the perimeter of hard macros.

$o keep from blocking access to signal pins* a"oid placing cells under power straps unless the

straps are on metal la&ers higher than metal3

2se densit& constraints or placement!blockage arra&s to reduce congestion

1"oid creating an& blockage that increases congestion.

1. Place macros around chip periphery.

)f &ou don4t ha"e reasonable rationale to place the macro inside the core area* then place macros

around the chip peripher&. #lacing a macro inside the core can in"ite serious conse'uence during

routing due to a lot of detour routing* because macros are e'ual to a large obstacle for routing.

1nother ad"antage to placing the hard macros around the core peripher& is it5s easier to suppl&

 power to them* and reduces the change of )+ drop problems to macros consuming high amounts

of power.

2. Consider connections to fixed cells when placing macros.

When &ou decide macro position* &ou ha"e to pa& attention to connections to fi(ed elements

such as )/% and perplaced macros. #lace macros near their associate fi(ed element. ,heck

connections b& displa&ing flight lines in the 62).

3. Orient macros to minimize distance between pins.

When &ou decide the orientation of macros* &ou also ha"e to take account of pins positions and

their connections.

4. eser!e enough room around macros.For regular net routing and power grid* &ou ha"e to reser"e enough routing space around macros.

)n this case estimating routing resources with precision is "er& important. 2se the congestion

map from trial+oute to identif& hot spots between macros and ad7ust their placement as needed.

". educe open fields as much as possible.

E(cept for reser"ed routing resources* remo"e dead space to increase the area for random logic.

,hoosing different aspect ratio -if that option is a"ailable0 can eliminate open fields.

#. eser!e space for power grid.

$he number of power routes re'uired can change based on power consumption. 8ou ha"e to

estimate the power consumption and reser"e enough room for the power grid. )f &ou

underestimate the space re'uired for power routing* &ou can encounter routing problems