Synchronous Sequential Logic

Flip-Flops

Chapter 5, Digital Design, Mano & Ciletti

Outline

● Flip-Flops, Latches● Latch● Set-Reset Latch (SR Latch)● SR Latch: NOR vs. NAND● SR NAND Latch with Enable● D-Latch

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

D

FF-

Latch-Q

Terms: Trigger, Transition

● Trigger: A change in the output of a latch/FF as a result of a change in the input– FF is triggered at the positive edge of the clock

– D-latch is triggered every time the En is at logic-1 level.

●

Terms: Trigger, Transition

● Trigger: A change in the output of a latch/FF as a result of a change in the input– FF is triggered at the positive edge of the clock

– D-latch is triggered every time the En is at logic-1 level.

● Transition– Clock pulse goes through two transitions: from 0 to 1

and the return from 1 to 0.

– FF is triggered at the 0 to 1 (low-to-high) transition of the clock

Level triggered to Edge-Triggered

D

FF-Latch-Q

Requirement: Output must be stable for a full clock cycle

Requirement: Output must be stable for a full clock cycle

Level triggered to Edge-Triggered

D

FF-Latch-Q

Requirement: Output must be stable for a full clock cycle

Requirement: Output must be stable for a full clock cycle

Observe: Output is already stable in the negative cycleObserve: Output is already stable in the negative cycle

Level triggered to Edge-Triggered

D

FF-Latch-Q

Requirement: Output must be stable for a full clock cycle

Requirement: Output must be stable for a full clock cycle

FF- Q

Level triggered to Edge-Triggered

D

FF-Latch-Q

Requirement: Output must be stable for a full clock cycle

Requirement: Output must be stable for a full clock cycle

FF- Q

Negative Edge

Triggered

Negative Edge

Triggered

Level triggered to Edge-Triggered

D

FF-Latch-Q

Capture last stable value before rising edge; Keep it

stable for another half cycle

Capture last stable value before rising edge; Keep it

stable for another half cycle

FF- Q

Level triggered to Edge-Triggered

D

FF-Latch-Q

Capture last stable value before rising edge; Keep it

stable for another half cycle

Capture last stable value before rising edge; Keep it

stable for another half cycle

FF-Q

LatchLatch

Level triggered to Edge-Triggered

D

FF-Latch1 – Q

FF-Latch2 – Q

Level triggered to Edge-Triggered

D

FF-Latch1 – Q

FF-Latch2 – Q

Output of Latch1 is input to Latch 2.

Output of Latch1 is input to Latch 2.

Level triggered to Edge-Triggered

D

FF-Latch1 – Q1

FF-Latch2 – Q2

Latch2 is triggered when C=0. But Q1 is stable during this period.

Latch2 is triggered when C=0. But Q1 is stable during this period.

Output of Latch1 is input to Latch 2.

Output of Latch1 is input to Latch 2.

Negative Edge-Triggered D-FF

Negative Edge-Triggered D-FF

D

Negative Edge-Triggered D-FF

D

Y

Negative Edge-Triggered D-FF

D

Y

Q

Negative Edge-Triggered D-FF

D

Y

Q Slave is transparent atClk Low. Input is constant.

Slave is transparent atClk Low. Input is constant.

Negative Edge-Triggered D-FF

D

Y

Q

Negative Edge-Triggered D-FF

D

Y

QSlave is Opaque at Clk HighSlave is Opaque at Clk High

Negative Edge-Triggered D-FF

D

Y

Q

Negative Edge-Triggered D-FF

D

Y

Q

Negative Edge-Triggered D-FF

D

Y

Q

How to make a positve-edge triggered D-FF?

How to make a positve-edge triggered D-FF?

FF Construction Summary

● Employ two latches (with opposite trigger behaviour)

FF Construction Summary

● Employ two latches (with opposite trigger behaviour)– Latch 1 is transparent when Latch 2 is opaque and

vice-versa

FF Construction Summary

● Employ two latches (with opposite trigger behaviour)– Latch 1 is transparent when Latch 2 is opaque and

vice-versa

– Latch 1 output is fed to Latch 2

FF Construction Summary

● Employ two latches (with opposite trigger behaviour)– Latch 1 is transparent when Latch 2 is opaque and

vice-versa

– Latch 1 output is fed to Latch 2

– When Latch 1 is opaque, its output is constant. Feed it to Latch 2. Output of FF will be constant.

3 SR Latch – D-FF

Positive Edge-Triggered

Positive Edge-Triggered

3 SR Latch – D-FF

0

3 SR Latch – D-FF

0

1

1

3 SR Latch – D-FF

0

1

1

Maintains previous state

Maintains previous state

3 SR Latch – D-FF

1

1

0

D has to be setup before Clk = 1

D has to be setup before Clk = 1

3 SR Latch – D-FF

1

1

0

0

Case 1. D=0.Case 1. D=0.

3 SR Latch – D-FF

1

1

0

0

1

3 SR Latch – D-FF

1

1

0

0

1

1

1

1

3 SR Latch – D-FF

1

1

0

0

1

1

1

10

0

3 SR Latch – D-FF

1

1

0

0

1

1

1

10

0 1

No change in QNo change in Q

3 SR Latch – D-FF

1

1

0

0

1

1

1

10

0 1

Positive edge triggers

Positive edge triggers

3 SR Latch – D-FF

1

1

0

1

1

1

1

10

0 1

3 SR Latch – D-FF

1

0

0

1

1

1

1

10

0 1

3 SR Latch – D-FF

1

0

0

1

1

1

1

10

0 1

1

1

3 SR Latch – D-FF

1

0

0

1

1

1

1

10

0 1

1

1

0

3 SR Latch – D-FF

1

0

0

1

1

1

1

10

0 1

1

1

0

Q follows DQ follows D

3 SR Latch – D-FF

1

1

1

0

Case 2. D=1Case 2. D=1

3 SR Latch – D-FF

1

1

1

0

01

3 SR Latch – D-FF

1

1

1

0

0

0 1

3 SR Latch – D-FF

1

1

1

0

0

0 1

Positive edge triggers

Positive edge triggers

3 SR Latch – D-FF

1

1

1

1

0

0 1

1

3 SR Latch – D-FF

0

1

1

1

0

0 1

3 SR Latch – D-FF

0

1

1

1

0

0 1

1

3 SR Latch – D-FF

0

1

1

1

0

0 1

1

0

1

Q follows DQ follows D

3 SR Latch – D-FF

0

1

1

1

0

0 1

1

0

1

Q is stable after Clk transition

Q is stable after Clk transition

3 SR Latch – D-FF

0

1

0

1

0

0 1

1

0

3 SR Latch – D-FF

0

1

0

1

1

1

1

0

1

3 SR Latch – D-FF

0

1

0

1

1

1

1

0

0

10

Q does not varyQ does not vary

3 SR Latch – D-FF

0

1

0

1

1

1

1

0

0

10

Transition Clk to 0Transition Clk to 0

D-Flip Flop

D-Flip Flop

● Timing of input input data w.r.t clock is important

●

D-Flip Flop

● Timing of input input data w.r.t clock is important

● Minimum time before clock transition for D input to be stable: Setup time

D-Flip Flop

● Timing of input input data w.r.t clock is important

● Minimum time before clock transition for D input to be stable: Setup time

● Minimum time during which the D input must not change after clock transition: Hold time

D-Flip Flop

● Propagation delay of the FF: interval between the trigger edge and the stabilization of the output to a new state.– Clock-to-Q delay

Flip-Flop Operations

● Three operations on a FF: Set it to 1, Reset it to 0, or Complement output

Flip-Flop Operations

● Three operations on a FF: Set it to 1, Reset it to 0, or Complement output

● D-FF can set or reset output

Flip-Flop Operations

● Three operations on a FF: Set it to 1, Reset it to 0, or Complement output

● D-FF can set or reset output● 2-input JK flip-flop can do all three

Flip-Flop Operations

● Three operations on a FF: Set it to 1, Reset it to 0, or Complement output

● D-FF can set or reset output● 2-input JK flip-flop can do all three● J =1: Set; K=1: Reset; J=K=1, Q is

complemented

Flip-Flop Operations

● Three operations on a FF: Set it to 1, Reset it to 0, or Complement output

● D-FF can set or reset output● 2-input JK flip-flop can do all three● J =1: Set; K=1: Reset; J=K=1, Q is

complemented● Circuit applied to the D input:

JK FF

Summary

● Flip-Flops vs. Latches● Latch● Set-Reset Latch (SR Latch)● SR Latch: NOR vs. NAND● SR NAND Latch with Enable● D-Latch