FlexRay Electrical Physical Layer Application Notes V3.0.1

8/10/2019 FlexRay Electrical Physical Layer Application Notes V3.0.1

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FlexRay Communications System

Electrical Physical LayerApplication Notes

Version 3.0.1


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FlexRay Electr ical Physic al Layer App lication Notes Table of con tents

Version 3.0.1 October-2010 Page 2 of 69

DISCLAIMER

This specification and the material contained in it, as released by the FlexRay Consortium, is for the purpose ofinformation only. The FlexRay Consortium and the companies that have contributed to it shall not be liable for

any use of the specification.

The material contained in this specification is protected by copyright and other types of Intellectual PropertyRights. The commercial exploitation of the material contained in this specification requires a license to suchIntellectual Property Rights.

This specification may be utilized or reproduced without any modification, in any form or by any means, forinformational purposes only.For any other purpose, no part of the specification may be utilized or reproduced, in any form or by any means,without permission in writing from the publisher.

Important Information

1. The FlexRay specifications V2.1 and V3.0.1 and the corresponding FlexRayConformance Test specifications (hereinafter together FlexRay specifications) havebeen developed for automotive applications only. They have neither been developednor tested for non-automotive applications.

2. The FlexRay specifications areretrievable on the website www.flexray.com forinformation purposes only and without obligation.

3. The technical expertise provided in the FlexRay specifications is subject tocontinuous further development. The FlexRay specifications serve exclusively as an

information source to enable to manufacture and test products which comply with theFlexRay specifications (FlexRay compliant products). Observation of theFlexRay specifications does neither guarantee the operability and safety of theFlexRay compliant products, nor does it guarantee the safe cooperation of multipleFlexRay compliant products with each other or with other products. Therefore, themembers of the former FlexRay Consortium are not able to assume liability for theoperability and safety of such products and the safe cooperation of multiple FlexRaycompliant products with each other or with other products.

4. The FlexRay specifications V3.0.1 were submitted to ISO in order to be published asa standard for road vehicles.

The word FlexRay and the FlexRay logo are registered trademarks.

Copyright 2006 2010. All rights reserved.

The Core Partners of the FlexRay Consortium are Adam Opel GmbH, Bayerische Motoren Werke AG, DaimlerAG, Freescale Halbleiter Deutschland GmbH, NXP B.V., Robert Bosch GmbH and Volkswagen AG.
http://www.flexray.com/http://www.flexray.com/


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Table of contents

CHAPTER 1 INTRODUCTION ...................................................................................................................... 5

1.1 Objective ............................................................................................................................................... 5

1.2 References ............................................................................................................................................ 5

1.3 Revision history ..................................................................................................................................... 5

1.4 Terms and definitions ............................................................................................................................ 6

1.5 List of abbreviations .............................................................................................................................. 6

1.6 Notational conventions .......................................................................................................................... 61.6.1 Parameter prefix conventions .......................................................................................................... 61.6.2 Parameter color conventions ........................................................................................................... 7

CHAPTER 2 APPLICATION NOTES ........................................................................................................... 8

2.1 Application hint: Cable impedance ........................................................................................................ 8

2.2 Application hint: Connectors ................................................................................................................. 9

2.3 Application hint: Split termination ........................................................................................................10

2.4 Application hint: Common mode chokes.............................................................................................11

2.5 Application hint: Exemplary cable shield connection ..........................................................................12

2.6 Application hint: Network topology layout ...........................................................................................13

2.7 Application hint: Termination concepts ...............................................................................................13

2.7.1 Termination concept for point to point connections .......................................................................132.7.2 Termination concept for passive star topologies ...........................................................................132.7.3 Termination concept for passive linear bus topologies .................................................................132.7.4 Termination in hybrid topologies ...................................................................................................13

2.8 Application hint: Passive star - impedance adjustment ......................................................................14

2.9 Application hint: AC busload test ........................................................................................................16

2.10 Application hint: Increased ESD protection.......................................................................................17

2.11 Application hint: Operation at low voltage on VBAT ............................................................................18

2.12 Application hint: Protocol relevant parameters / Propagation delay .................................................18

2.13 Application hint: Protocol relevant parameters / TSS and Symbol length change ...........................19

2.14 Application hint: Protocol relevant parameters / EMC jitter ..............................................................222.14.1 Introduction ..................................................................................................................................222.14.2 EMC jitter on data edges .............................................................................................................222.14.3 EMC jitter on TSS length .............................................................................................................222.14.4 EMC jitter on Symbol length change ...........................................................................................22

2.15 Application hint: Protocol relevant parameters / Echoes ..................................................................23

2.16 Application hint: Protocol relevant parameters / Ringing ..................................................................25

2.17 Application hint: Active star / Wakeup reaction .................................................................................29

2.18 Application hint: Active star / branch recovery ..................................................................................30

2.19 Application hint: Eye-diagram ...........................................................................................................31

2.19.1 Objective ......................................................................................................................................312.19.2 Eye-diagrams for different data rates ..........................................................................................312.19.3 Capturing method ........................................................................................................................33


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2.20 Signal integrity voting ........................................................................................................................342.20.1 Low pass filter (LPF)....................................................................................................................352.20.2 Schmitt trigger bit timing detection (STBTD) ...............................................................................352.20.3 Signal voting calculation ..............................................................................................................372.20.4 Variables ......................................................................................................................................38

2.21 Application hint: Generic transmitter model ......................................................................................39

2.22 Implementation hint: Receiver asymmetry ........................................................................................40

2.23 Application hint: EMC performance of bus drivercommunication controller interface ..................46

2.24 Application hint: PCB track impedance and track delay ...................................................................46

2.25 Application hint: Bus driverbus guardian interface ........................................................................46

2.26 Application hint: Wakeup state machine ...........................................................................................47

CHAPTER 3 SYSTEM TIMING CONSTRAINTS ........................................................................................48

3.1 Objective .............................................................................................................................................48

3.2 Description of asymmetry portions ......................................................................................................493.2.1 Overview ........................................................................................................................................493.2.2 Bus driver ......................................................................................................................................503.2.3 Communication controller ..............................................................................................................513.2.4 ECU ...............................................................................................................................................523.2.5 Passive networks ...........................................................................................................................543.2.6 Electro-magnetic-interferences EMI ..............................................................................................55

3.3 Description of asymmetric acceptance ranges ...................................................................................583.3.1 Asymmetric acceptance range of the decoder ..............................................................................583.3.2 Minimum bit duration of the transceiver ........................................................................................61

3.4 System calculation with asymmetric delays ........................................................................................62

3.4.1 Overview ........................................................................................................................................623.4.2 Considered topologies ...................................................................................................................623.4.3 Example calculation without EMI ...................................................................................................63

3.5 Conclusion with respect to topologies .................................................................................................643.5.1 Statistical asymmetry calculation ..................................................................................................69


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FlexRay Electr ical Physic al Layer App lication Notes Chapter 1: Introdu ction


Chapter 1Introduction

1.1 Objective

The objective of this document is to collect valuable information that shall help to implement FlexRay systems.The content of this document is informative and not normative.

1.2 References

[EPL10] FlexRay Communications System - Electrical Physical Layer Specification, Version 3.0.1,FlexRay Consortium, October 2010

[PS10] FlexRay Communications System - Protocol Specification, Version 3.0.1,FlexRay Consortium, October 2010

[EMC10] FlexRay Communication SystemElectrical Physical Layer EMC measurement specification,Version 3.0.1, FlexRay Consortium, October 2010

1.3 Revision history

With respect to Version 2.1 Revision B of this Application Notes the following changes were applied.

Chapter 2Several Application hints clarified and reworked due to changed parameters in [EPL10]

Application hint: Termination concepts adaptedApplication hint: Host software / ECU control deletedApplication hint: Protocol relevant parameters / Propagation delay introducedApplication hint: Protocol relevant parameters / TSS and Symbol length change introducedApplication hint: Protocol relevant parameters / EMC jitter introduced

Application hint: Protocol relevant parameters / Echoes introducedApplication hint: Protocol relevant parameters / Ringing introducedApplication hint: Active Star / Wakeup reaction introducedApplication hint: Active Star / branch recovery introducedApplication hint: Eye-diagram introducedApplication hint: Signal integrity voting introducedApplication hint: Generic transmitter model introducedApplication hint: Receiver asymmetry introducedApplication hint: EMC performance of bus drivercommunication controller interface introducedApplication hint: PCB track impedance and track delay introducedApplication hint: Bus driverbus guardian interface introducedApplication hint: Wakeup state machine introduced

Chapter 3Complete chapter adapted to new values and definitions


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1.4 Terms and definitions

FlexRay specific terms and definitions are listed in [PS10].

1.5 List of abbreviations

See Glossary in [EPL10]

1.6 Notational conventions

1.6.1 Parameter prefix conventions

::= Name

::= a | c | v | g | p | z

::= d | l | n | s | u

NamingConvention

Information Type Description

a AuxiliaryParameter

Auxiliary parameter used in the definition or derivation of otherparameters or in the derivation of constraints.

c Protocol Constant Values used to define characteristics or limits of the protocol.These values are fixed for the protocol and cannot be changed.

v Node Variable Values that vary depending on time, events, etc.

g Cluster Parameter Parameter that must have the same value in all nodes in a cluster,is initialized in the POC:default configstate, and can only bechanged while in the POC:configstate.

p Node Parameter Parameter that may have different values in different nodes in thecluster, is initialized in the POC:default configstate, and can onlybe changed while in the POC:configstate.

z Local SDLProcess Variable

Variables used in SDL processes to facilitate accuraterepresentation of the necessary algorithmic behavior. Their scopeis local to the process where they are declared and their existencein any particular implementation is not mandated by the protocol.

- - prefix_1can be omitted for physical layer parameters.

This table is mirrored from [PS10], where the binding definitions are made!

Table 1-1: Prefix 1.


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NamingConvention

Information Type Description

d Time Duration Value (variable, parameter, etc.) describing a time duration, thetime between two points in time.

l Length Physical length of e.g. a cable

n Amount Number of e.g. stubs

s Set Set of values (variables, parameters, etc.).

u Voltage Differential voltage between two conducting materials (e.g. copperwires)

The prefixes l, n and u are defined in [EPL10]. For all other prefixes refer to [PS10].

Table 1-2: Prefix 2.

1.6.2 Parameter color conventions

Throughout the text several types of items are highlighted through the use of an italicized color font.

ColorConvention

Example Description

blue dBDRxAsym Parameters, constants and variables

green BD_Normal SDL states (see [PS10]) and operation modes

brown Data_0 Enum value (e.g. different bus states)

Table 1-3: Color conventions.


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FlexRay Electr ical Physic al Layer App lication Notes Chapter 2: App lication Notes


Chapter 2Application Notes

2.1 Application hint: Cable impedance

With a differential mode impedance in the range of [80 .. 110] an optimum matching with the defined DC busload (see [EPL10]) can be achieved. Mismatches between DC bus load and cable impedance may beintentionally applied, but need to be checked application specific.

The figure below shows the equivalent input circuit of a symmetric two-wire transmission line applicable toshielded and unshielded twisted pair lines.

The differential input impedance calculates to Z0= (2 Z) || Z12

ground

Z Z

Z12

Z

Z12

Z

Figure 2-1: Cable impedance


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2.2 Application hint: Connectors

This application hint note does not prescribe certain connectors for FlexRay systems.

However, some recommendations are given:

Name Description Typ Unit

lContactDistanceBP-BM Contact distance (*) 4.5 mm

lContactMetal Distance between outer metal parts andcenter of contact

2 mm

lECUCoupling Length of connector to control unit (**) 75 mm

(*) adjacent chambers shall be used

(**) to be measured from end of the twisted area in cable to PCB housing

Table 2-1: Connector parameters.

See also the section about connectors in [EPL10].


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2.3 Application hint: Split termination

In order to achieve a better EMC performance, it is recommended to make use of a so-called split termination inall ECUs, where the Termination resistance RTis split into two equal parts RTAand RTB.

BD

BP

BM

ECU

R1C1 RTB

RTA

Figure 2-2: ECU with split termination.

The serial RC combination (R1;C1) at the center tap of the split termination provides a termination to GND forcommon mode signals. R1is preferably omitted. Typical values are given in the following table:


R1 Resistor < 10

C1 Capacitor 4700 pF

2 |RTA-RTB| / (RTA+RTB) Matching of termination resistors 2 %

Table 2-2: Termination parameters.

For RTAand RTBthe use of 1% tolerated resistors leads to a matching of 2%; see table above.

The better the matching of the split termination resistors RTAand RTB, the lower the electromagnetic emission.


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2.4 Application hint: Common mode chokes

To improve the emission and immunity performance, a common mode choke may be used. The function of thecommon mode choke is to force the current in both signal wires to be of the same strength, but oppositedirection. Therefore, the choke represents high impedance for common mode signals. The parasitic strayinductance should be as low as possible in order to keep oscillations on the bus low. The common mode chokeshall be placed between transceiver and split termination. The following figure shows how to integrate thecommon mode choke in presence of a split termination.

BD

BP

BM

ECU

R1C1 RTB

RTA

Figure 2-3: ECU with split termination and common mode choke.

The following table lists the recommended characteristics of common mode chokes in FlexRay networks:


RCMC Resistance per line 1.5

LCMC Main inductance 100 H

L Stray inductance < 1 H

Table 2-3: Common mode choke characteristics.

Mind that in case the stray inductance exceeds a certain application specific limit, a node sees activity on thebus temporarily immediately after stopping its own transmission. I.e. when last transmitted bit was Data_1, thena Data_0can be read and vice versa. For further information see section 2.15.


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The maximum mechanical overall dimensions should not exceed the limits listed below:

Name Description Min Max Unit

H Height 5.2 mm

W Width 6.0 mm

L Length 10.0 mm

Table 2-4: Maximum mechanical dimensions.

2.5 Application hint: Exemplary cable shield connection

The following figure shows an exemplary cable shield connection. It is also assumed that the connectors areshielded, thus the shielding is not interrupted between two ECU housings.

Node n Node m

Termination

network

Figure 2-4: Exemplary cable shield connection.

The short-circuited shield could cause resonances. Additional circuits to damp these resonances are up to theapplication.


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2.6 Application hint: Network topology layout

Recommendations that are listed here should be followed when topologies are planned in order to increase thechance to find a reasonable termination concept, so that signal voting according to section 2.20 can result in apass at each node as receiver in combination with all possible sending nodes.

Avoid "stubs on stubs". A splice shouldn't be connected to more than two other splices.

Keep the cumulative cable length as short as possible. Avoid lStubi+ lSpliceDistancei,j > 24m.

Connect ECUs that are optional to a separate branch of an active star in order to avoid un-terminatedcable ends.

Apply a split termination to each ECU by taking the DC-load range into account.

2.7 Application hint: Termination concepts

2.7.1 Termination concept for point to point connections

Both cable ends are terminated with a resistor (RTA+ RTB) that has a resistance equal to the nominal cableimpedance. Limitations of cable impedance and DC busload are given in [EPL10].

2.7.2 Termination concept for passive star topologies

At those two nodes that have the maximum electrical distance over the passive star, the cable ends areterminated with a resistance equal or slightly higher to the nominal cable impedance. At all other nodes a high

ohmic split termination (e.g. 2x 1300+ 4.7nF) should terminate the cable. Limitations of cable impedance and

DC busload are given in [EPL10].

2.7.3 Termination concept for passive linear bus topologies

At those two nodes that have the maximum electrical distance on the bus, the cable ends are terminated with aresistance equal or slightly higher to the nominal cable impedance. At all other nodes a high ohmic split

termination (e.g. 2x 1300+ 4.7nF) should terminate the cable. Limitations of cable impedance and DC busloadare given in [EPL10].

2.7.4 Termination in hybrid topologies

To each sub-section, the termination concept is chosen as outlined in the sections above.


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2.8 Application hint: Passive star - impedance adjustment

Passive star topologies tend to reflections at their low resistive center. To avoid this, ferrite cores can be used forincreasing the impedance for high frequencies. Their selection is specific to the application.

BP

BM

BP

BM

BP

BM

Ferrite cores

Optimized

RF impedance

Figure 2-5: Ferrite cores on each wire at a passive star.

This impedance adjustment might be also achieved by discrete components:

1st branch of the passive staroptimized RF

impedance

last branch of the passive staroptimized RF

impedance

BP

BM

R1

L1

R1

L1

R1

L1

R1

L1

BP

BM

Figure 2-6: Discrete elements for impedance adjustment at a passive star (no cable shield).


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or, in case a cable shield is used in the system:

1st branch of the passive staroptimized RF

impedance

optimized RF

impedance

BP

BM

C1

L1

R1

L2

R2

R

3

L1

R1

last branch of the passive star

L1

R1

L2

R2

L1

R1

Shield

Shield

BP

BM

Figure 2-7: Discrete elements for impedance adjustment at a passive star (with cable shield).


R1 Series resistance at signal wire 22

L1 Series inductance at signal wire 220 nH

R2 Resistance at cable shield 100

L2 Inductance at cable shield 220 nH

R3 Resistance at shield to system ground 1 M

C1 Capacitance to system ground 100 nF

Table 2-5: Typical component values for impedance adjustment.


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2.9 Application hint: AC busload test

The figure 2-8 shows a load dummy that can be connected to TP2 for AC busload investigations. The SI votingat TP2 (see chapter 2.20) needs to result in PASS.

BD under test

inclusive

termination

network

Stimuli on TxD

0001000"

1110111"

(100ns/bit)

Transmission line

Z = 90

Ltg

= 9ns

DC

> -0.015dB

30MHz

> -0.5dB

100MHz

> -1.4dB

200MHz

> -2.7dB

58

1 H 330 nH

1 H 1 H

100 pF 330 pF

S1

1 2

Switch S1 is in default position 1, when the BD under test has a termination resistor; otherwise S1 is in position 2

TP2

18

58 58

Figure 2-8: AC busload dummy.


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2.10 Application hint: Increased ESD protection

ESD protection elements typically represent a certain capacitive load on the bus lines BP and BM.

EMC investigations have shown that in case such capacitances on BP and BM do not match, the emission isincreased and the RF immunity is decreased.

Therefore it is strongly recommended to strictly limit the mismatch in the entire capacitive load caused by ESDprotection diodes, PCB layout, connectors and further termination circuits.

A mismatch of more than 2% seems not to be acceptable.

BD

BP

BM

ECU

C1RTB

RTA CESD

CESD

Figure 2-9: ESD protection diodes in an ECU.


CESD Capacitance of ESD protection element - 20 pF

Table 2-6: Capacitance of ESD protection elements.


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2.11 Application hint: Operation at low voltage on VBAT

In case communication is required during crank then sufficient bypass capacitance is expected to be existent atBDs supply voltage pins. This applies specially to conditions as specified in ISO7637 part 1 Test pulse 4maximum severity level. Mind that the BD may enter a low power mode, when uVECUbecomes less than 6.5V,since a further voltage drop between uVECUand uVBATat the transceiver pin has to be considered due toprotection diodes.

2.12 Application hint: Protocol relevant parameters / Propagation delay

The maximum propagation delay of a transmitting BD is given by dBDTx1075ns, for a receiving BD by

dBDRX1075ns and for an active star dStarDelay10150ns. Furthermore a limitation for the specific line

(cable) delay is given in chapter 4 of [EPL10] T010ns/m.

Under the arbitrary chosen assumption that all cable segments have lengths up to 24m, the following valueshave been calculated:


dPLPropagationDelay0ASM,N (*) Propagation delay on a path without activestars from node module M to node moduleN

- 390 ns

dPLPropagationDelay1ASM,N (*) Propagation delay on a path with oneactive star from node module M to nodemodule N

- 780 ns

dPLPropagationDelay 2ASM,N (*) Propagation delay on a path with two activestars from node module M to node moduleN

- 1170 ns

(*) The path from TP1_BD to TP4_CC is covered, the CC-portions are not included.

Table 2-7: Exemplary propagation delay.

The actual propagation delay influences the performance of the FlexRay system. An estimate of this influencecan be made by using the equations given in [PS10].

The following rules of thumb can be derived:

Minimize max { dPropagationDelayM,N} in order to achieve an optimum efficiency of the dynamic partand short interslot gaps.

Minimize the difference [max { dPropagationDelayM,N} - min { dPropagationDelayM,N}] in order toachieve an optimum precision of clock synchronization.


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2.13 Application hint: Protocol relevant parameters / TSS and Symbol

length changeFor calculating several protocol parameters the knowledge about the frame TSS length change and symbollength change is necessary. Relevant values are given in the tables below.


dFrameTSSLengthChange0ASM,N(*)

Frame TSS length change on a pathwithout active stars from node module M tonode module N

-400 50 ns


Frame TSS length change on a path withone active star from node module M to

node module N

-850 50 ns


Frame TSS length change on a path withtwo active stars from node module M tonode module N

-1300 50 ns


Table 2-8: Frame TSS length change.


dSymbolLengthChange0ASM,N (*) Change of length of a symbol on a path

without active stars from node module M tonode module N

-325 225 ns

dSymbolLengthChange1ASM,N (*) Change of length of a symbol on a pathwith one active star from node module M tonode module N

-625 675 ns

dSymbolLengthChange2ASM,N (*) Change of length of a symbol on a pathwith two active stars from node module Mto node module N

-925 1125 ns


A negative value means that the symbol is shortened, a positive value means the symbol is elongated.

Table 2-9: Symbol length change.

Mind that the minimum and maximum values in both tables do not take jitter caused by EMC effects intoaccount. More information about EMC jitter is given in the following section in this document.


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FlexRay Electr ical Physica l Layer Appl icat ion Notes Chapter 2: Appl icat ion Notes


uBus

RxD

Activity shorter than

dActivityDetection

Activity reaction time

dBDRxiadBDRx01 Idle shorter than

dIdleDetection

Idle reaction time

dBDRxaidBDRx10

TxEN

dBDTxia dBDTxai

dBDTx01 dBDTx10

dBDTxai dBDTxia

TxD

Figure 2-10: Receiver timings.


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FlexRay Electr ical Physica l Layer Appl icat ion Notes Chapter 2: Appl icat ion Notes


Here it comes clear that the Frame TSS length change at the receiver is caused mainly by the activity reaction time.

dFrameTSSLengthChangeReceiver= dBDRx01dBDRxia.

With dBDRxia= [100 .. 325] and dBDRx01= [0 .. 75] follows dFrameTSSLengthChangeReceiver= [-325 .. -25].

At the transmitter the length of the TSS may also face a lengthening or shortening:

dFrameTSSLengthChangeTransmitter= dBDTx01dBDTxia.

With dBDTxia= [0 .. 75] and dBDTx01= [0 .. 75] follows dFrameTSSLenghtChangeTransmitter= [-75 .. 75].

The two portions mentioned above lead to the resulting value for a signal path without active stars: dFrameTSSLengthChange0ASM,N= [-400 .. 50].

Considering the parameter dStarTSSLengthChange: = [-450 .. 0] it follows that:

Resulting value for a signal path with one active star: dFrameTSSLengthChange1ASM,N= [-850 .. 50].

Resulting value for a signal path with two active stars: dFrameTSSLengthChange2ASM,N= dFrameTSSLengthChangeM,N= [-1300 .. 50].

Symbol length change at the transmitter is determined as dSymbolLengthChangeTransmitter= | dBDTxia- dBDTxai= dBDTxDM| 50ns.

Symbol length change at the receiver is determined as dSymbolLengthChangeReceiver= dBDRxai- dBDRxia.

With dBDRxia= [100 .. 325] and dBDRxai= [50 .. 275 ] follows dSymbolLengthChangeReceiver= [ -275 .. 175].

The two portions mentioned above lead to the resulting value for a signal path without active stars: dSymbolLengthChange0ASM,N= [-325 .. 225].

Considering the parameter dStarSymbolLengthChange: = [-300 .. 450] it follows that:

Resulting value for a signal path with one star: dSymbolLengthChange1ASM,N= [-625 .. 675].

Resulting value for a signal path with two active stars: dSymbolLengthChange2ASM,N= dSymbolLengthChangeM,N= [-925 .. 1125].


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2.14 Application hint: Protocol relevant parameters / EMC jitter

2.14.1 Introduction

Injection of RF fields results in a certain jitter portions seen in the RxD signal at receiving nodes. These differentportions have been investigated and the results are documented in the following subsection.

2.14.2 EMC jitter on data edges

Jitter on edges in the RxD signal, which are different from first transition from HIGH to LOW (start of frame) andthe last transition from LOW to HIGH (the end of a frame), shall be considered in the course of systemevaluation. This is discussed in detail in the following chapter in this document.

2.14.3 EMC jitter on TSS length

Jitter on the TSS length might lengthen or shorten the TSS additionally to the length change as described insection 2.13. The empirical upper bound of this effect is given in the following table:


dFrameTSSEMIInfluence0ASM,N Change of length of a TSS due toEMC effects in systems withoutactive stars

-25 25 ns

dFrameTSSEMIInfluence1ASM,N Change of length of a TSS due toEMC effects in systems one activestar per channel

-50 50 ns

dFrameTSSEMIInfluence2ASM,N

Change of length of a TSS due toEMC effects in systems two activestars per channel

-75 75 ns

A negative value means that the TSS is shortened, a positive value means the symbol is elongated.

Table 2-10: EMC jitter on Frame TSS length change.

2.14.4 EMC jitter on Symbol length change

The summation of jitter on the idle to active and active to idle edges of symbols might lead to deviations of thesymbol length change as described in section 2.13. The empirical upper bound of this effect is given in thefollowing table:


dSymbolEMIInfluence0ASM,N Change of length of a symbol due to EMCeffects in systems without active stars

-100 200 ns

dSymbolEMIInfluence1ASM,N Change of length of a symbol due to EMCeffects in systems with one active star perchannel

-200 400 ns

dSymbolEMIInfluence2ASM,N Change of length of a symbol due to EMCeffects in systems with two active stars perchannel

-300 600 ns

A negative value means that the symbol is shortened, a positive value means the symbol is elongated.

Table 2-11: EMC jitter on Symbol length change.


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2.15 Application hint: Protocol relevant parameters / Echoes

A transmitting node may see a kind of echo after the end of transmission, which means that its RxD pin mightsignal additional edges after disabling the transmitter. In most cases, where echoes occur, the stray inductanceof common mode chokes is too high and the network can be seen as defective.

Beside echoes also ringing (see chapter 2.16) might affect the transmitting node. Both effects will overlay andthe effect of multiple RxD switching can be combined to a time span of RxD uncertainty ( dRxUncertainty).

Nevertheless such a time span of multiple RxD switching can be accepted by the protocol mechanisms and canbe considered in the protocol configuration constraints.

In case ferrite cores or other inductive elements are used for impedance matching (e.g. at passive stars),dRxUncertaintymay be even greater than 250ns.

Examples of the effects of dRxUncertaintyare given in Figure 2-11 and Figure 2-12. In case a communication

controller is connected to an active starcommunication controller interface (see section 9.8) the parameterdStarTxRxaishall be used instead of dBDTxRxai.


dRxUncertainty Time following the end of a transmissionwhere instability may occur on RxD as aresult of echoes and/or ringing. During thistime the RxD output may change statesseveral times and may not reflect the actualcondition of the bus.

0 250 ns

Table 2-12: Duration of RxD instability after transmission

idle

dRxUncertainty + dBDTxRxai

RxD either on high or lowRxD may switchseveral times between

high and low

dRxUncertainty

TxEN

idle

RxDwithout echo/ringing

dBDTxRxai

RxDwith echo/ringing

RxD on high

Figure 2-11: RxD uncertainty after frame end.


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idle

dRxUncertainty + dBDTxRxai

RxD either on high or lowRxD may switch

several times between

high and low

dRxUncertainty

TxEN

idle

RxDwithout echo/ringing

dBDTxRxai

RxDwith echo/ringing

RxD on high

Figure 2-12: RxD uncertainty after symbol end.


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2.16 Application hint: Protocol relevant parameters / Ringing

A receiving node or active star may see a kind of ringing at the end of a received signal.

In the description below, ringing is described as a period of instability following the end of the FES high bit, i.e.,

the description assumes that transmission is turned off after the FES high bit, as it would be for a frame

transmission in the static segment. Note, however, that ringing with similar characteristics could also occur at the

end of all other types of transmission, for example at the end of the DTS for frame transmissions in the dynamic

segment or at the end of the active low phase in a WUS transmission.

Such ringing can be accepted by the protocol mechanisms and can be considered in calculating protocolconfiguration parameters. The ringing takes different effect depending on the location of the receiver in thenetwork.

Receiving

BD

Trans-

mitting BD

RxD0

Active

Star 1

Active

Star 2

RxDAS1 RxDAS2

RxD1 RxD2

TxDTxEN

Receiving

BD

Receiving

BD

ReceivingBD

ReceivingBD

Figure 2-13: Different positions of RxD signals in a FlexRay network.


dRingRxD0 Time following the FES1 where instabilitymay occur on RxD without pass throughactive stars

0 525 ns

dRingRxDAS1 Time following the FES1 where instability

may occur on RxD at the first receivingactive star in a network

0 800 ns

dRingRxD1 Time following the FES1 where instabilitymay occur on RxD when signal passedthrough one active star

0 1225 ns

dRingRxDAS2 Time following the FES1 where instabilitymay occur on RxD at the second receivingactive star in a network

0 1250 ns

dRingRxD2 Time following the FES1 where instabilitymay occur on RxD when signal passedthrough two active stars

0 1675 ns

Table 2-13: Ringing period in different network types.


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When ringing occurs the RxD signal may switch multiple times and ends either on logical high or logical low,which cannot be predicted. From the perspective of a receiving node the worst case occurs when the ringingperiod ends with a logical low RxD signal. In this case the idle detection after transmission of a frame is delayedby the duration of ringing plus the idle reaction time. The idle detection time after transmission of a symbol isdelayed by the duration of the ringing.

The figure 2-14 on next page shows the receivers behavior with the maximum timings. The hatched areasindicate the time span in which ringing at the bus may occur and the RxD signal may switch multiple times. Thewhite rectangles indicate time spans in which the RxD signal is stable; either on low or on high. When thereceiver is in idle the RxD signal is on logical high.

Table 2-13 above shows the worst case values (i.e. for ringing that ends on active low) for different topologiesand for nodes which are located a various positions within these topologies. These values are calculated underthe assumption that the duration of ringing (dRing)does not exceed 250ns. This value is also the basis for thederivation of parameter ranges in [PS10].

In case ferrite cores or other inductive elements are used for impedance matching (e.g. at passive stars), ringing

periods may get even longer than 250ns.


dRing Educated guess for the ringing period 0 250 ns

Table 2-14: Educated guess of ringing period.

The effect of ringing with respect to the resulting RxD signal is depending whether the transmission ends with anactive high bit or with an active low bit. In three cases the transmission ends with an active high bit:

- FES high bit after the transmission of a static frame (see Figure 3-2 in [PS10])

- DTS high bit after the transmission of a dynamic frame (see Figure 3-3 in [PS10])

- Additional high bit after the transmission of a WUDOP (see Figure 3-7 in [PS10])

The transmission of a symbol (WUS, CAS, MTS) ends on an active low bit.

Figure 2-15 gives an example for the resulting RxD2signal for different scenarios (frame vs. symbol) with andwithout ringing.


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275ns

550ns

idle

idle

idle

uBus (behind transmitting BD)

RxDAS1- Receiving active star

(no active star on path to sender)

uBus(behind first active star)

RxDAS2- Receiving active star

(no ringing at 2nd active star

since this a p2p connection)

RxD2- Receiving node

(two active stars on path to sender)

250ns

250ns 450ns

idle


(no active star on path to sender)

250ns

dRingRxD0

dBDRxaidRing

dRingRxDAS1

dStarRxaidRing

dStarFES1LengthChangedRing

idle

250ns 450ns

dRingRxDAS2

dStarFES1LengthChangedRing

550ns

dStarRxai

250ns 450ns

2 x dStarFES1LengthChangedRing

450ns

uBus(behind second active star)

275ns

idle


(one active star on path to sender)

250ns

dRingRxD1

dBDRxaidRing dStarFES1LengthChange

450ns 250ns

dRing

idle

250ns 450ns


450ns 275ns

idle

250ns

dRingRxD2

dBDRxaidRing

TxEN (of transmitting BD)

*)

*)

*) Received ringing is actively forwarded by the active star

Figure 2-14: Ringing after transmission end.


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250ns 450ns


450ns

uBus(behind second active star) idle

250ns 450ns


450ns 275ns

idle

250ns

dRingRxD2

dBDRxaidRing

*)


450ns

2 x dStarFES1LengthChange

450ns


450ns

2 x dStarFES1LengthChange

450ns 275ns

idle

dRxD2

dBDRxai



FES

FES

FES

FES



250ns 450ns


450ns


250ns 450ns


450ns 275ns

idle

250ns

dRingRxD2

dBDRxaidRing

*)


450ns

2 x dStarSymbolEndLengthChange

450ns


450ns

2 x dStarSymbolEndLengthChange

450ns 275ns

idle

dRxD2

dBDRxai



Symbol

Symbol

Symbol

Symbol

FrameorWUDO

P

Symbol

w

ithringing

withoutringing

withringing

withoutringing

**)

**)

**)

**)

**) FES or DTS or additional high bit after WUDOP (see [PS09])

Figure 2-15: Example for transmission end with and without ringing


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2.17 Application hint: Active star / Wakeup reaction

In case of non-monolithic implementations, only the active star device with the branch that receives the wakeupevent has to initiate the transition toAS_Normalon this remote wakeup. Other active star devices used in the

same non-monolithic active star shall initiate the transition toAS_Normallatest on the next activity that issignaled on the intra star interface between the different active star devices.

The system designer shall ensure that a stabilized voltage supply is available latest dStarMainSupplyafter theremote wakeup event was detected; i.e. the AS has re-enteredAS_Normalafter dStarMainSupplyafter wakeup,in case the capacitor could not bridge the voltage regulator ramp up.

The AS needs to forward a minimum number of wakeup pattern after its wakeup to ensure a proper wakeup ofthe network. Figure 2-16 depicts the exemplary situation with 2 active stars, with timings ensuring a sufficientwakeup pattern at the branches of the 2

ndAS. In case the AS is supplied solely out of a capacitor after wakeup,

this capacitor, which is charged out of VBAT, shall be able to sufficiently supply the AS for at leastdStarAuxSupply.

AS1TP14

AS1TP11

Wake-up detected

70s

dWU

dWUIdleDet (4s)

Idle Data_0

Idle

174s

AS2TP11

70s

50s

Wake-up detected

20s 34s

124s

20s 30s

t

uBus

AS2TP14

nodeTP4

TP4 50s

20s 30s

node

uBus

uBus

t

t

Figure 2-16: Wakeup timing


dStarAuxSupply1AS(*) Time during the AS is supplied from anauxiliary supply (e.g. storage capacitor)when a network with 1 active stars is used

50 - s

dStarAuxSupply2AS(*) Time during the AS is supplied from anauxiliary supply (e.g. storage capacitor)when a network with 2 active stars is used

174 - s

dStarMainSupply(*) Time after that the AS gets stabilizedvoltage supply

- 100 ms

(*) Parameter on system level

Note: For the calculation of the timings it is expected that during the wakeup reaction time (max. 70s) the active star is supplied out of VBAT.If not, this extra time needs to be considered for the dimensioning of a capacitor.

Table 2-15: Active star wakeup reaction time.


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2.18 Application hint: Active star / branch recovery

An active star will deactivate branches upon detection of error conditions. See [EPL10].

Unless the host steps in to prevent it branch recovery could occur at any time, and this recovery might havetemporary implications on the operation of the protocol.

See [PS10] for mechanisms by which the slot counters can become desynchronized, the implications andlimitations on the scope of the damage.


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2.19 Application hint: Eye-diagram

2.19.1 Objective

The eye diagram is an easy to use tool to estimate jitter and signal quality in serial data systems. In FlexRaysystems it is a fast and helpful tool to obtain an overview about jitter, noise, reflections, amplitude differencebetween various nodes, and possibly errant edge timing problems in the system. Nevertheless for the physicallayer testing it is insufficient to be used as a signal integrity compliance test alone because reflections andglitches could fail the eye diagram even though the communication controller works faultless. The main reasonfor this is the low-pass filter characteristic of the FlexRay bus driver as well as the FlexRay glitch filter and signalvoting in the communication controller, which could eliminate the negative effect of short glitches and reflections.

The SI voting as described in the following section 2.20 makes another assessment of the signal quality.

To see all effects of signal variation in the eye diagram, including jitter, the eye must be created from

consecutive bits from one or more FlexRay frames. The more frames are used to create the eye diagram, themore confidence it gives in the signal integrity performance of the FlexRay under test. Therefore the eye-diagram must be created using an oscilloscope with special software that extracts/recovers the clock from thedata signal. The FlexRay receivers clock recovery hardware has to be emulated. The capturing method for theeye diagram is described in section 2.19.3.

2.19.2 Eye-diagrams for different data rates

2.19.2.1 Eye-diagram for 10Mbit/s

The eye diagram timing for 10Mbit/s is based on the decoder requirement of 62.5ns (=5/8 x gdBit) plus 11nsasymmetry on the path from TP4 to TP5. An implemented eye diagram procedure is assumed to be

synchronized every 10 Bits (falling BSS edges, see section 2.19.3).

0mV

26.5ns

Minimum aperture uBus @ 10Mbit/s

0mV

73.5ns

300mV

62.25ns

300mV

37.75ns

400mV

50ns

-300mV

37.75ns

-400mV

50ns

- 300mV

62.25ns

100ns

Figure 2-17: FlexRay eye-diagram @ 10Mbit/s.


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2.19.2.2 Eye-diagram for 5Mbit/s

The eye diagram timing for 5Mbit/s is based on the decoder requirement of 125ns (=5/8 x gdBit) plus 11.5ns

asymmetry on the path from TP4 to TP5. An implemented eye diagram procedure is assumed to besynchronized every 10 Bits (falling BSS edges, see section 2.19.3).

0mV

63.5ns

Minimum aperture uBus @ 5Mbit/s

0mV

136.5ns

300mV

125.25ns

300mV

74.75ns

400mV

114ns

200ns

400mV

86ns

-300mV

74.75ns

-400mV

114ns

-400mV

86ns

-300mV

125.25ns

Figure 2-18: FlexRay eye-diagram @ 5Mbit/s.

2.19.2.3 Eye-diagram for 2.5Mbit/s

The eye diagram timing for 2.5Mbit/s is based on the decoder requirement of 250ns (=5/8 x gdBit) plus 12.5nsasymmetry on the path from TP4 to TP5. An implemented eye diagram procedure is assumed to besynchronized every 10 Bits (falling BSS edges, see section 2.19.3).

0mV

137.5ns

Minimum aperture uBus @ 2.5Mbit/s

0mV

262.5ns

300mV

251.25ns

300mV

148.75ns

400mV

240ns

400ns

400mV

160ns

-300mV

148.75ns

-400mV

240ns

-400mV

160ns

-300mV

251.25ns

Figure 2-19: FlexRay eye-diagram @ 2.5Mbit/s.


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2.19.3 Capturing method

To recover the receivers clockthe oscilloscope has to find the first BSS event (=falling edge in the BSS) afterthe TSS and looks for the next BSS events to occur within 10 bit fields after the prior BSS event. With eachBSS event, the oscilloscope generates ideal clocks synchronized to this BSS event. This process of generatingideal clocks synchronized to each BSS event continues until the oscilloscope detects the frame-end-sequence

(FES). If the oscilloscope fails to find a BSS event within 10 bits fields after the prior BSS event, the clockrecovery shall be aborted until detection of the next TSS event.

After generating the ideal clocks synchronized to each BSS event for the entire acquisition, the scope slices theacquired waveform into single bit field segments based on the timing of the recovered clocks. These slices, areoverlaid on top of each another to create the real-time FlexRay eye-diagram.

Figure 2-20: Generation of FlexRay eye-diagrams.

Advantageously the oscilloscope allows using all captured frames as well as using only selected frames; e.g.those which are sent by one selected node, to generate the eye-diagram.


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2.20 Signal integrity voting

An eye diagram test applied to any passive network is going to fail in case of reflections even if thecommunication works faultlessly. Reflections appear in e.g. passive stars. The signal integrity voting is aprocedure following the example given by the BD properties and its robustness against disturbances.

The procedure detects whether a FlexRay topology is operable or not in principle. Differential bus signal shapesmeasured at any position are taken into account. The signal integrity voting is a mathematical calculationprocedure. Any block of identical bits in a row (consecutive edges) can be used. To keep the description simple,a single bit is assumed.

Passive network TPx

Parameter

cut-off frequency

Schmitt-Trigger thresholds uData0and uData1

requirements

1. minimal level reached2. asymmetric delay limited

3. minimal bit-duration reached

4. idle not detected

Sq

single bit (or bit-block) by any node or

passed by an active star

x00010x (or x00011...110x)

x11101x (or x11100...001x)x:= dont care

Signal Voting

uBusTPx

uBusTPx

dBitLong

dBitShort

dEdgeMax

LPF

Low Pass Filter

Schmitt-Trigger

Bit Timing Detection

STBTD

SV

Figure 2-21: Single bit signal integrity model

In the 1ststep the measured differential signal uBusTPxpasses a mathematically perfect low-pass filter. The

resulting signal uBusTPxshould meet minimal level requirements (level test). In the 2nd

step the signal uBusTPx

passes a Schmitt-Trigger with the threshold variations according to table 2-18a. The resulting bit-timing has tomeet the specified requirement (bit-timing test). The voting result Sqsummarizes the results of the level test andthe bit-timing tests.


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2.20.1 Low pass filter (LPF)

IN uBusTPx Measured differential voltage at any test planeOUT uBusTPx Filtered differential voltage signal

PARAMETER fSIVotingcutoff The 3dB cut off frequency is 14MHz

BEHAVIOR 1storder low pass filter, infinite input impedance

Table 2-16: Low pass filter characteristics.

Standard oscilloscopes offer to limit the measuring bandwidth down to 20MHz. Using this feature allows to getan impression of the signal integrity easily.

2.20.2 Schmitt trigger bit timing detection (STBTD)

According to table 8-22 the data detection thresholds uData0und uData1have to match. The tolerance rangehas to be sampled with a 30mV resolution.

uData1

150mV

uData1min

300mV

uData1max

uData0

-150mV

-300mV

30mV

used

threshold

combination

uData0max

uData0min

Figure 2-22: Threshold tolerances and their test coverage

IN uBusTPx Filtered differential voltage signal

OUT dBitLong Longest detectable duration of one bit (*)

dBitShort Shortest detectable duration of one bit (*)

dEdgeMax Duration slowest edge

PARAMETER uData1 Data_1threshold (see behavior)

uData0 Data_0threshold (see behavior)

(*) determined by applying all threshold combinations shown in Figure 7-6

Table 2-17: Signal voting parameter list.


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BEHAVIORbit-length

Single target bit x00010x

dBitM/N

uData1

uData0

uBus TPx

Single target bit x11101x

uData1

uData0

dBitM/N

u B u s TPx

Duration of one singleData_0or Data_1bitmeasured at differentthresholds.3 inverted bits before and one inverted bit after the monitored bit are required at least

uData1 uData0 uData0 uData1

300mV -300mV -300mV 300mV dBit300/-300

300mV -270mV -270mV 300mV dBit300/-270

270mV -300mV -300mV 270mV dBit270/-300

270mV -240mV -240mV 270mV dBit270/-240

240mV -270mV -270mV 240mV dBit240/-270

240mV -210mV -210mV 240mV dBit240/-210

210mV -240mV -240mV 210mV dBit210/-240

210mV -180mV -180mV 210mV dBit210/-180

180mV -210mV -210mV 180mV dBit180/-210

180mV -150mV -150mV 180mV dBit180/-150

150mV -180mV -180mV 150mV dBit150/-180

150mV -150mV -150mV 150mV dBit150/-150

180mV -180mV -180mV 180mV dBit180/-180

210mV -210mV -210mV 210mV dBit210/-210

240mV -240mV -240mV 240mV dBit240/-240

270mV -270mV -270mV 270mV dBit270/-270

Table 2-18a: Signal voting bit length measurements.

BEHAVIOR

bit-length Calculations

Longest bit duration dBitLong = MAX(dBitM/N)

Shortest bit duration dBitShort= MIN(dBitM/N)

Asymmetry of themeasured bit

dBitLengthVariation= dBitLongdBitShort

Table 2-18b: Signal voting bit length determination.


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BEHAVIOURedge-duration

dEdge10

uData1max

uData0min

u B u s TPx

dEdge01

uData1max

uData0min

uBus TPx

Determination of edgedurations

uData1Max= 300mV uData1Max= 300mV

uData0Min= -300mV uData0Min= -300mV dEdge10 dEdge01

Table 2-19a: Signal voting - edge duration measurement.

BEHAVIOURedge-duration

Calculation Slowest edge dEdgeMax= MAX (dEdge01, dEdge10)

Table 2-19b: Signal voting - edge duration determination.

2.20.3 Signal voting calculation

Conditions to pass the test

the differential voltage level has to be high enough

the shortest detectable duration of one bit has to be long enough

the asymmetry of the measured bit has to be less than the limit

idle detection during the frame has to be avoided

IN uBusTPx Filtered differential voltage

dBitShort Shortest detectable duration of one bit

dBitLong Longest detectable duration of one bit

dEdgeMax Duration of the slowest edge

OUT Sq Voted signal quality

PARAMETER dBitLengthVariationMax Allowed maximal length variation 7ns

dBitMin required minimum duration of the shortest bit at TP4_BDi:

70.95ns @ 10Mbit/s (*)

134.40ns @ 5.0Mbit/s (**)

261.30ns @ 2.5Mbit/s (***)

uData0Top required level (top): -330mV

uData1Top required level (top): 330mV

dIdleDetectionMin minimal timeout to detect Idle: 50ns

(*) (100ns36.6ns) + 7.55ns for the path from TP5 to TP4_BDi according to fig 6-4 and tab 6-6 in [EPL10] (@10Mbit/s for one single bit)

(**) (200ns73.2ns) + 7.60ns for the path from TP5 to TP4_BDi according to figure 6-4 in [EPL10] (@5Mbit/s for one single bit)

(***) (400ns146.4ns) + 7.70ns for the path from TP5 to TP4_BDi according to figure 6-4 in [EPL10] (@2.5Mbit/s for one single bit)

Table 2-20: Signal voting

parameter list.


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BEHAVIOR IF dBitLengthVariation dBitLengthVariationMax

AND uBusTPxuData1Top

AND dBitShortdBitMinAND dEdgeMaxdIdleDetectionMinTHEN Sq= passELSE Sq= fail

IF dBitLengthVariation dBitLengthVariationMax

AND uBusTPxuData0Top

AND dBitShortdBitMinAND dEdgeMaxdIdleDetectionMinTHEN Sq= passELSE Sq= fail

Table 2-21: Signal voting procedure calculation method.

The result is coded in the value Sq:

pass the differential signal meets the minimal signal shape requirements (level and delay)

fail the differential signal does not meet the minimal signal shape requirements (level or delay)

2.20.4 Variables

dBitLengthVariation detected length variation

dBitLengthVariationMax allowed maximal length variation

dBitMin allowed shortest bit at TP4_BDi (e.g. limited by the properties of the CC)

dBitLong shortest detectable duration of one bit

dBitShort longest detectable duration of one bit

uBusTPx differential voltage at any test plane

uBusTPx filtered differential voltage uBusTPx.

uData0Top required voltage uBusTPxto detect Data_0

uData1Top required voltage uBusTPxto detect Data_1

dIdleDetectionMin minimal timeout to detect Idle

dEdgeMax detected duration of the slowest edge

Sq voted signal quality: pass or fail

Fail: the signal shape does not meet the specified requirements

Pass: the signal shape meets the specified requirements

system specific individual additional voting states like e.g. warning are notdefined

Table 2-22: Signal voting variables.


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2.21 Application hint: Generic transmitter model

The following figure shows a generic FlexRay BD and AS transmitter model.

Transmitter

BP

BM=

RBDTransmitter

RBDTransmitter

Figure 2-23: Generic transmitter model.

The figure shows the transmitter when transmitting a Data_0on the bus.

The resistors drawn with dashed lines are assumed to have infinite resistance. The resistors drawn with solidlines have a resistance value of RBDTransmitter, a value which is given in the product datasheet.

The dashed and solid resistorshave to exchange their places, when transmitting Data_1.


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2.22 Implementation hint: Receiver asymmetry

In section 8.9 in [EPL10] a receiver input signal is defined, which is the definition for receiver delay and receiverasymmetry measurements. Here six further receiver test signals are given. These shall be used as guidanceduring silicon design about the expected system behavior of a bus driver and can be optionally used to assessthe quality of a receiver circuit. For each test signal a logical high pulse of a certain given length on RxD isexpected.

uBus

800mV

- 800mV

-1000ns 0ns 30ns 70ns 100ns t

Figure 2-24: Receiver test pulse 1.


dBitTestpulse1 Width of expected logical high pulse onRxD (*)

66 74 ns

(*) Measured at 50% of VDIG

Table 2-23: Expected timing for test pulse 1.


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t

uBus

-1000ns 0ns 200ns100ns

400mV

- 400mV



dBitTestpulse2 Width of expected logical high pulse on

RxD (*)

93 107 ns




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uBus

-1000ns 0ns 140ns70ns

500mV

- 500mV

t




RxD (*)

65 75 ns




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uBus

-1000ns

500mV

- 600mV

0ns 140ns

70ns

t

225mV

- 225mV

52.5ns

116.14ns

225mV is the mean value of the specified minimum and maximum receiver thresholds



dBitTestpulse4 Width of expected logical high pulse onRxD (*)

51 76 ns




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uBus

600mV

- 600mV

1000mV

- 1000mV

-1000ns 0ns 110ns30ns t

40ns

70ns

100ns




RxD (*)

66 74 ns




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uBus

120ns

600mV

- 600mV

30ns

1000mV

- 1000mV

50ns

60ns

200mV

- 200mV

100ns t0ns 70ns 130ns-1000ns




RxD (*)

66 74 ns

(*) Measured at 50% of VDIG6



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2.23 Application hint:

EMC performance of bus driver

communication controller interfaceThe TxD and RxD signals between the communication controller and the bus driver are driven by low ohmicoutputs in order to ensure sufficient driving capability even for large distances between these two components.

This leads to high currents and emission of RF energy, which can be reduced by series resistors as depicted inthe following figure.

BDCC

RxD

TxEN

TxD

Figure 2-30: Series resistors in RxD, TxD and TxEN line.

This measure may lead to additional asymmetry in the signal path. Therefore it needs to be checked carefully foreach individual application, whether additional asymmetry occurs, or not.

2.24 Application hint:PCB track impedance and track delay

For the PCB tracks (TxD, TxEN and RxD) between the communication controller and the bus driver it isrecommended to fulfill the values given in Table 2-29. All timing budget calculations are done with these values,therefore additional asymmetric delay mismatch may occur in case the recommended values are not met.

The given values representing a PCB track length of 15cm.


ZPCB PCB track impedance 50

dTrackDelayPCB PCB track delay 1 ns

Table 2-29: PCB track impedance and track delay.

2.25 Application hint: Bus driverbus guardian interface

The usage of a bus guardian interface (if the bus driver or active star includes the functional class Bus driver -bus guardian interface or Active star - bus guardian interface, as defined in [EPL10]) might help to fulfillSIL3 / ASIL D level requirements (see also IEC 61508 / ISO 26262).


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2.26 Application hint: Wakeup state machine

For the remote wakeup detector there is an event driven wakeup state machine defined in [EPL10]. Theoperating principal for typical wakeup recognition is depicted in Figure 2-31.

For details of the remote wakeup detector refer to chapter 8.11 of [EPL10].

Id le Id le IdleData_0 Data_0

Id le

detected

dW UIdleDetect dW U0Detect dW U0DetectdW UIdleDetect

id le

detected

Data_0

detected

id le

detected

dW UIdleDetect

Wakeup!

dW UTi me o u t

dW U

Data_0

detected

Wait I Initial state Wait S Start state Wait A Wait state A Wait B Wait state B Wait C Wait state C

Bus-signal

Wakeup

timings

Wakeup

state

machine

Idle

edge

on bus

Data_0

edge

on bus

Idle

edge

on bus

Data_0

edge

on bus

Idle

edge

on bus

Figure 2-31: Typical wakeup recognition.


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FlexRay Electr ical Physical Layer Appl icat ion Notes Chapter 3: System Timing Constra ints


Chapter 3System Timing Constraints

3.1 Objective

TopologyClock

sourceBDCC

Connection

network

transmitting ECU

TP0

Clocksource

BD CC

receiving ECU

TP4TP5

Connection

network

total asymmetry from transmitter to decoder: 37.5 ns max.

total asymmetry from transmitter to busdriver input: 30.0 ns max.

Topology = combination of: point-to-point linear passive bus passive star active star

Figure 3-1: Overview.

This chapter describes the system timing of a FlexRay network, the behavior of networks and influences on asystem, which should be considered during the design phase.

The impacts of asymmetric delays in the complete signal chain of a FlexRay network are considered.Asymmetric delays result in real measurable bit times, which can be shorter or longer than the specified nominalbit time gdBit.

There are two major kinds of asymmetric delay contributions: static and stochastic.

Static contributions do not vary at fixed operating conditions, but will always appear in a FlexRay network. Theyare defined by maximum values in [EPL10].

The stochastic contributions occurrence cannot be anticipated. It results mainly from external contributions, likeelectro-magnetic effects, thermal noise and similar stochastic effects.


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A general topology consists of a transmitting and a receiving ECU (see figure 3-1). The signal chain starts in thetransmitting communication controller, continues its way over the bus driver, common mode choke and bustermination. The signal passes the topology and ends in the receiving ECU also with bus termination, common

mode choke to the receiving bus driver. Finally, the transmitted signal can be decoded in the receivingcommunication controller.

The sum of asymmetric delay must not exceed 37.5ns for 10Mbit/s through the complete signal chain of theapplied FlexRay topology. Moreover, requirements on the bit duration at the receivers input (TP4) have to befulfilled. With 500ppm crystal tolerance the asymmetric delay robustness is 36.5ns (see chapter 3.2.3.1).

The relevant conditions are:

Decoders asymmetric delay robustness for 10Mbit/s: 37.5ns (table 6-6 in [EPL10])

Bus drivers minimum bit duration: 70.0ns (table 8-30 in [EPL10])

3.2 Description of asymmetry portions

3.2.1 Overview

Figure 3-1 represents the signal flow, depending on the FlexRay network topology. Such a network includes

the transmitting ECU,

a passive network (passive bus or passive star),

an active star network and

the receiving ECU

The following table 3-1 lists relevant components for the asymmetric delay examination. These components are

discussed in detail within this chapter. The third column shows whether the component is mandatory or optionaldepending upon the chosen topology.

Component Sub component / design Mandatory / Optional

Transmitting ECU ECU Layout

Clock

Communication controller

Bus driver

Bus Termination

Mandatory

Mandatory

Mandatory

Mandatory

Optional

Network Active star

Bus Termination

Wiring

Optional

Optional

Mandatory

Receiving ECU ECU Layout

Clock

Communication controller

Bus driver

Bus Termination

Mandatory

Mandatory

Mandatory

Mandatory

Optional

Table 3-1: Contributions to asymmetric delays.


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3.2.3 Communication controller

3.2.3.1 Oscillator tolerance

The sample clocks used by transmitting and receiving communication controller to generate and sample the bitstream are derived from oscillators local to the node. Due to oscillator tolerances, the sample clock oscillator ofthe transmitter may run at a different frequency than the sample clock oscillator of the receiver. This ratedifference will result in a systematic error in the perception of the incoming sample stream, and this errorcontributes to the overall asymmetry of the system.

A fast oscillator in a transmitter will make edges appear to arrive earlier than expected with respect to the fallingedge of the BSS. A slow oscillator in the transmitter will make the edges arrive later than expected. The situationis basically opposite in the receiversa fast oscillator makes the edges appear to arrive late, and slow oscillatorwill make the edges appear to arrive early.

The worst case for early edges is when the transmitter oscillator is at its tolerance limit on the fast side, and the

receiver oscillator is at its tolerance limit on the slow side. The worst case for late edges is when the transmitteroscillator is at its tolerance limit on the slow side, and the receiver oscillator is at its tolerance limit on the fastside.

The magnitude of the effect is also a function of how far the edge occurs away from the resynchronization at thefalling edge of the BSS. The effect is larger for edges further away from the falling edge of the BSS.

In the current implementation of the communication controller [PS10], the worst case would be the rising edge ofthe FES or the falling edge in the subsequent BSS, as those represent the maximum time possible without bitclock alignment. The maximum time without clock alignment is 10 bits multiplied by the nominal bit time gdBit(1s).

The FlexRay protocol specification [PS10] specifies a maximum oscillator tolerance of 1500ppm (0.15%). Thetolerance of a FlexRay system to asymmetry improves when higher precision oscillators are employed. In thefollowing analysis an oscillator tolerance of 500ppm (i.e. 0.05%) is assumed. This tolerance should be feasiblewith the selection of high quality components.

With a maximum oscillator tolerance of 500ppm at the transmitting and the receiving node the decodersasymmetric delay robustness decreases to 37.5ns2 x 10 x gdBitx 500ppm = 37.5ns2 x 0.5ns = 36.5ns.

Remark:

The maximum time without clock synchronization is 10 bits and only reflects the requirement for the coding anddecoding process within the communication controller. Thus for the calculation of worst case timings, the clock-tree deviation for the communication controller on sending and receiving side differs with factor 10 from thecalculation for the bus driver and active star calculation.

3.2.3.2 Sampling clock accuracy

Clock accuracy with PLLA phase locked loop (PLL) can be used to provide the required sample clock based on a lowerfrequency. The PLL jitter influences both the transmitting and receiving communication controller.

Clock accuracy without PLLOne way to minimize signal asymmetries is the use of a clock source, which is 16 times the bitfrequency. The usage of a clock source, 8 times the bit frequency, by using rising and falling edgesgenerates also the recommended clock, but may introduce additional asymmetry because of a non-idealduty cycle. The amount of asymmetry depends on the duty cycle directly but increases the staticasymmetry only at the receiving side.


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3.2.3.3 Generic digital component contribution

Setup & hold times

The setup and the hold times are not considered separately because these values are included in worstcase considerations of time discretization of the sampling process. The considered time discretization isgreater than any setup time. If there is any hold time in semiconductor process, it will be present both atsynchronizing the sampling clock and at sampling point. Both hold times neutralize each other.

I/O bufferComplementary transistors of I/O buffers never match perfectly. Thus, a propagation delay mismatchmight occur. These asymmetries will vary with temperature and supply voltage variations, but areassumed to be constant during the reception of one frame.

Pin padThe pin pads of the communication controllers within the semiconductor device may be a source ofstatic asymmetric delay because of different locations of different pin pads on the chip and because of

production tolerances. The pin pad will not insert a stochastic asymmetry.The output pins of a communication controller will typically have slew rate controlled pin pads in order tolimit the electromagnetic emission. Slew rate for rising and falling edges might not match. In fact apositive asymmetric delay can be assumed since it is expected that the pull-down transistor is fasterthan the pull-up transistor.

3.2.4 ECU

The keyword ECU summarizes production specific amounts to the asymmetric delay caused by:

asymmetric load to ground, e. g. by an asymmetric geometry inside the differential signal chain

briefly reduced slew-rate, e. g. by additional parasitic capacities, inductivities and resistors due to PCBwires and layout behaviors

inside the area between the BD pins and the ECU pins.

Topic Examples: Asymmetry Examples: Parasitic

Layout of the bus-signal lines Routing of the signal BP

Routing of the signal BM

Capacities and inductivities of vias

Common mode choke Windings

Terminal pairs

Stray inductivity

Termination filters Matching of the split termination Capacities of the resistors to ground

Connectors Geometry path BP geometry path BM Capacities and inductivities of thecontacts

Printed circuit board Width path BP

Width path BM

Etching of the lines and pads

Soldering of the pins

Dielectricity of the PCB

Ringing

Impedance matching Mismatch of output impedance and

characteristic impedance of PCB

Table 3-2: ECU Parameter influencing asymmetric delays.


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3.2.4.1 Interfaces

The signal path consists of several interfaces between devices. Figure 3-2 gives an overview of all possible

types of interfaces in a topology with two active stars.Combination of input thresholds and rise and fall times of connected devices leads to interface asymmetry.

BDCC

transmitting ECU

AS

active star 1

AS

active star 2

CCBD

receiving ECU

CC-BD IF BD-AS IF AS-AS IF AS-BD IF BD-CC IF

Figure 3-2: Interfaces in an active star topology.

3.2.4.1.1 Interface between communication controller and bus driver

The interface asymmetry of the transmitting path (CC-BD IF) is included in the bus driver while the interfaceasymmetry of the receiving path (BD-CC IF) is included in the total asymmetry of the receiving CC.

Effects of interconnections between semiconductor devices on a PCB can be described with a micro strip line.

FlexRay Electrical Physical Layer Application Notes V3.0.1

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