FPGA IMPLEMENTATION OF LOW POWER FIR FILTER

Mr.K Siva sankaran

Assistant Professor School of Electronics Engineering

VIT University

Suyog.C1, Neelabh C2 ,Adithyan R3,Ajith Krishna.R4 Balaji D.S5

M.Tech Student School of Electronics Engineering

VIT University

Abstract Abstract-In this paper low power and high performance design of digital fir filter has been proposed. In traditional design of FIR filter low power and high performance cannot be meet.In this paper we proposed FIR filter design that uses the low complexity and low power multiplication algorithm and carry skip adder. The proposed architecture has been implemented using FPGA which provides flexibility and reliability to the design. The proposed architecture gives 20% power saving and improved speed performance as compared to the traditional FIR filter design. Keywords- FIR, digital filter, FPGA.

I. INTRODUCTION

Digital filter plays crucial role in digital signal processing applications[1][9]. Digital filters are devided into two categories FIR and IIR filters.but,FIR filters are widely used in many signal processing applications because they are always stable and gives linear phase response. Traditional DSP based FIR filter are designed with the Multiply and accumulate (MAC)blocks and ripple carry adders[9][10] therefore these designs of FIR filters does not give high speed and low power performance in many applications, therefore it is essential to build the algorithm for FIR filter that gives low power and improve speed.In the proposed architecture MAC blocks and ripple carry adder have been replaced by the Booth multipliers and the carry skip adder thats results in the improved speed and power performance[9]. Nowdays, it is possible to use Field programmable gate array(FPGA) in all DSP applications.In modern FPGA there are certain blocks which are dedicated for DSP applications. FPGA based systems achieves improved speed

performance because of parallel structure flexibility and reliability of the design achieved due to the configurable logic blocks of FPGA[10]. In this paper we implement the Low power FIR filter to reduce the power consumption and improves the speed performance[9]. First we choose the design specifications and then the low power booth and Wallace tree multipliers for multiplication and carry skip adder for addition.The rest of the paper has been divided into three sections. In first section literature review has been discussed. In second section hardware architecture of low pass filter using proposed low power algorithms has been discussed and in third section we put experimental results and some conclusion marks.

II. LITERATURE REVIEW

Existing systems to implement the FIR filters uses MAC blocks for multiplication and addition purpose that does not gives speed and power performance[2][10]. There were many schemes of reducing power have been put forward. The reduction in the partial product terms to implement the multiplier is the one of the challenge to overcome this problem many algorithms of high complexity have been proposed in recent years.In this paper modified Booth algorithm for multiplication has been proposed which is low complexity and reduces sufficient amount of partial product terms fulfills low power requirement[9].

III.LOW POWER AND HIGH SPEED CONSIDERATIONS

A. Booth Multiplication Algorithm

Booths multiplication algorithm is essential to reduce the numbers of partial product terms in the multiplication which results in the low power[2][9]. There are many types of Booths algorithm like radix-2,radix-4 and radix-8 The principle of this algorithm is repeated addition of Predefined values X and Y to the product term P, then Arithmetic right shift on P will be performed[2].Let a and b be the multiplicand and multiplier respectively; and let p and q represent the number of bits in a and b. [4] 1. First define the values of the values of X and Y, and the initial value of P. All of these values must be equal length which is equal to (p + q + 1). (a) X: Fill MSB bits with the value of p and Fill the remaining (q + 1) bits with zeros. (b) Y: Fill the MSB with the value of (-a) in twos complement form and then fill the remaining (q + 1) bits with zeros. (c) P: Fill the most significant p bits with zeros. To the right of this, append the value of b. Fill LSB bit with a zero. 2. Determine the LSB bits(rightmost two digits) of product term P. (a) If they are 01, calculate the value of P +X. Discard if any overflow occurs. (b) If they are 10, find the value of P + Y. Discard if any overflow occurs. (c) If they are 00 or 11 No operation performed. In this case use P directly in the next step. 3. Arithmetic Right shift in the value obtained in the second step by 1. Let P now takes this new value. 4. Repeat steps 2 and 3 to q times.

B. Wallace tree algorithm

A Wallace tree is a efficient multiplication algorithm which is specially used in the multiplication of integers[4][6][7].The Wallace tree multiplier adds all the bits of the same weights in a Wallace tree rather than complete addition of the partial product pairs[6]. Partial product terms produced during the multiplication are arranged in the tree like structure and addition is performed by

using Half adder and full adder cells[7]. Consider the following example which shows how partial product terms in the multiplication of 4*4 are reduced using tree like structure this algorithm differs from others. In Normal multipliers

b3b2b1b0 a3a2a1a0 b3a0 b2a0 b1a0 b0a0

b3a1 b2a1 b1a1 b0a1 b3a2 b2a2 b1a2 b0a2

b3a3 b2a3 b1a3 b0a3 and we have to add all these terms to get the result. In Wallace tree multiplier, partial products are arranged in tree like structure,

b3b2b1b0 a3a2a1a0 b3a3 b3a2 b3a1 b3a0 b2a0 b1a0 b0a0

b2a3 b2a2 b2a1 b1a1 b0a1 b1a3 b1a2 b0a2

b0a3

Figure 1:Wallace tree multiplier

C. Carry skip adder

In the binary arithmetic there are only two possibilities of Carry 0 and 1.The presence of only two values provides facility to choose any one value between these two[5]..In carry skip adder we used the algorithm to select the carry or bypassing the carry through the several stages of calculation and add it in the final stage using multiplexer facilities the minimization of delay due the propagation of carry. This mechanism improves the speed performance of the design[5][9].

Figure 2.Carry Skip Adder

III. PROPOESED ARCHITECTURE

In this paper we have implemented 4 tap low and direct form low pass FIR filter which has cutoff frequency as 2.5KHz.In the first stage the coefficients of the filter has been calculated using the matlab program. As stop band attenuation is less than 50 dB Hamming window has used for calculating the coefficients and then filter is designed using the Modelsim and the implementation on DE1 FPGA board had done using the ALTERA QuartusII software. Here design has proposed using two low power algorithms: Booths and Wallace tree and carry skip adder has been used for improving the speed performance. The proposed architecture meets the low power and high speed requirements.

Figure3: FIR filter Architecture

V.EXPERIMENTAL RESULTS

In this paper we implemented low power FIR filter of cutoff frequency 2.5 KHz on FPGA. Architecture has been designed using Booths and Wallace tree algorithms indivisually. The proposed design has been implemented and functionality has been checked by applying different input combinations for each algorithm. This architecture saves 20% power as compared to traditional design of FIR filter also speed performance of the design has been considerably increased as compared to the

traditional device. The experimental results clearly indicates that filter design using the Wallace tree algorithm gives better performance as compared to the Booths algorithm

Figure4. Output for input Combination 00000011 using Booth

multiplication algorithm .

Figure5: Output for input Combination 000010 using Wallace tree algorithm

VI.CONCLUSION

In this paper we proposed a power and speed efficient design of low pass FIR filter using low power multiplication algorithms and carry skip adder When the implemented Architecture has been compared to other design of FIR filter it was found that the proposed architecture gives better speed and power performance Also, the proposed design is an area and cost efficient Hence the proposed design can be used efficiently in many DSP applications.

ACKNOWLEDGMENT We wish to extend our thanks to our project

guide to Mr.SivaSankaran.K for his timely guidance and encouragement to complete the project.

REFERENCES

[1] H. Lee. C. Lit1 and C. Jen. "A new hardware-efficient architecture for programmable FIR filters.".IEEE transcation on circuits and systems." vol. 43.pp. 637-644. Sept. 1996 [2] Li-Hsun Chen and Oscal T-C. Chen. A low-complexity and high-speed booth-algorithm fir architecture. International Journal of Advanced Technology & Engineering Research (IJATER) . [3] L.chen.W Lit and T.C.Chen Determination of radix numbers of the booth algorithm for th optimized programmable FIR architecture . Proc of IEEE international Symposium on circuits and systems, Geneva, Switzerland, May 2000 [4] C.S.Wallace A suggestion for fast multipliers IEEE transaction on electronic computer [5] Dimitris Bekiaris, Isidoros Sideris, George Economakos Power-efficient and low latency Implementation of Programmable of FIR filters using carry save arithmetic [6] Jagadeshwar Rao M and sanjay Dubey A high speed and area efficient booth recoded Wallace tree multiplier for fast arithmetic circuits Asia pacific conference on post Graduate research in microelectronics and Electronics , 2012 [7] N.Surekha An efficient high speed Wallace tree multipier , IEEE conference 2012 [8] Sarita Chouhan and yogesh kumar Low power designing of FIR filter International journalof advanced technology &engineering research (IJATER) [9] Neil H.Weste and Kamaran Eshraghian principles of CMOS VLSI Design A system perspective Pearson Edition pvt Ltd .3rd edition Pp:345-356 [10] M.kirthi and V.Midasala FPGA implementation of distributed arithmetic for FIR filter International journal of engineering research & technology (IJERT) vol 1 Issue 9, November 2012 ISSN: 2278-0181.

I. INTRODUCTION II. LITERATURE REVIEWIII.LOW POWER AND HIGH SPEED CONSIDERATIONSA. Booth Multiplication AlgorithmB. Wallace tree algorithmC. Carry skip adder

III. PROPOESED ARCHITECTURE V.EXPERIMENTAL RESULTS VI.CONCLUSION REFERENCES