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Finite State Machines

Great - Theory!Finally!

Some ENGINEERING!

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Dynamic Discipline:Discrete State, Time

Comb. Logic

Comb. Logic

IN OUT

NEXT STATE CURRENT

STATE

Clock

Clock

STATE

NEXT

Clock Period

1

Clock Period

2

Clock Period

3

Clock Period

4

Clock Period

5

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Today's Abstraction:Finite State Machine

A FINITE STATE MACHINE has

• m INPUTS I1 ... Im

• n OUTPUTS O 1 ... O n

• Output Rules Out(s) for each state s

• Transition Rules S'(s,i)for each state s and input i

• k STATES S 1 ... S k (one "initial")

Clocked FSM

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FSM Example:Lets build an ant.

SENSORS: antennae L and R, each 1 if in contact with something.

ACTUATORS: Forward Step F, one- degree turns TL and TR (left, right).

GOAL: Make our ant smart enough to get out of a maze like:

STRATEGY: "Right antenna to the wall" approach.

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Ant Psychology8 situations ants know how to deal withSituation A: Following wall on

right, Right antenna just touching. Turn left a little, getting to

Situation B: Following wall, antenna not quite touching. Turn right a little, look for wall (A) or possibly a break in the wall (C).Situation C: a

break in the wall. Turn right & step until we hit the perpendicular wall, as shown in

Situation D: Hit the new wall, back to A.

Situation E: frontal wall. Turn left until

Situation F, which we can treat like B.

LOST: Go forward until we hit something.

? G: turn left until we don't touch.

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Ant Brain Synthesis: FSM Notation

LOST

STATE L RNEW

STATE OUTPUTS

LOST0 10 0

EorGLOSTF

.... .... .... .... ....

A0 00 1

011 1

A

AA

BorC 0 00 1

BorCA

EorGEorG

CA

.... .... .... .... ....

TL,F

TR,F

TL,FTL,FTL,F

TR,FBorC

State Transition Diagram:

F

LOST

TR,F

F

A

TL,F

BorCTR,F

C

EorG

R

L+R

L+R

R

_R

LTL

_ _L R

_ _L R _ _

L R

_ L R

_R

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Stylized FSM Implementation(One) IMPLEMENTATION STRATEGY:

• ROMs for NEXT STATE, OUTPUT Logic.• ENCODE each state as unique value of

some set of STATE VARIABLES...• ARBITRARY encoding may work... BUT• Choice may effect COMPLEXITY, COST!

• Fill in truth tables from TRANSITION DIAGRAM and OUTPUT SPECIFICATION.

ROM ROM

ROMMAY COMBINE next

state and output logic into single ROM:

EncodesFSM’s _________________

FSM’s __________________

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Example FSM ImplementationROML,R

2

LOST

L R

OUTPUTS

0 10 0

EorG

F

.... .... .... ....

A

0 00 1

011 10 00 1

BorCA

EorGEorG

CA

.... .... .... ....

BorC

X,Y,ZX',Y',Z'

F, TR, TL

TR TLX,Y,Z X',Y',Z'0 0 00 0 0

....

0 0 0

INPUTS

LOSTEorG

ABorC

C

= 0 0 0= 0 0 1= 0 1 0= 0 1 1

= 1 0 0

State Assignment:assign unique binary codes

to states.

0 1 00 1 00 1 00 1 00 1 10 1 1....

11

111111

....

.... .... ....

11

.... ....

00

0000

111100

00

(These are called

“_______________________”)

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FSMs: Issues & VariationsOUTPUTS = State Variables: Nice when you can do it.

MOORE vs. MEALY machines:

MOORE Machines: Outputs depend ONLY on current state.

MEALY Machines: Outputs may depend on INPUTS as well as current state.

INITIAL STATE: 000 in our example. Direct CLEAR input to register?

ROM ROM ROM

MOORE MEALY

SYNCHRONY of INPUTs -- what assumptions?Nonsense states? Worse?

UNASSIGNED STATES: What about 101 in example?

BUG inhandout!

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Unreachable StatesWhat about those unused ROM locations

-- eg, for xyz = 101, etc?

Unreachable states• Can't be reached from starting state by any

input sequence• May waste nearly 50% of ROM• Might (depending on design) be entered on

startup, or for illegal inputs...... often its important to specify transitions

out (eg to starting state).

1 1 1

all What does Ant doif it gets into this state? _______________

1 0 11 1 0

R

L+R

L+R

R

_R

L

_ _L R

_ _L R _ _

L R

_ L R

_R

0 0 0

0 1 1

0 0 1 0 1 0

1 0 0

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FSM Party Games

ROM

k k

1. What can you say about

the number of states?

2. Same question:

3. ADVENTURE:Here's an FSM. Can you discover its rules?

FSM

0 1

m States

n States

x y z

“______________________”

“______________________”

(see, eg, http://www.dtek.chalmers.se/~d9dax/laby/lab_lbcdaa.html)

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FSM Party Games:Whats My Transition Diagram?

3. ADVENTURE:Here's an FSM. Can you discover its rules?

FSM

0 1

• If you know NOTHINGabout the FSM, you’re ____________________________!

• If you have a BOUND on the number of states, you can discover its _______________________________

k-state FSM: Every (reachable) statecan be reached in < k steps.

BUT ... states may be _______________________________!

1

01

01

01 1

0

1

0

1

00

vs.0=OFF,1=ON?

"1111" =Surprise!

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FSM Metaphysics

ARE THEY DIFFERENT?

1

01

01

01 1

0

1

0

1

00

vs.

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FSM Equivalence

ARE THEY DIFFERENT?

NOT in any practical sense!They are EXTERNALLY INDISTINGUISHABLE,

hence interchangeable.

FSMs EQUIVALENT iff everyinput sequence yields ______________________output sequences.

ENGINEERING GOAL:• HAVE an FSM which works...• WANT simplest equivalent FSM.

New notion:

1

01

01

01 1

0

1

0

1

00

vs.

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FSM SimplificationGOAL: Given FSM, find reduced-state equivalent FSM.

METHOD: Detect indistinguishable ("equivalent") states, merge into single state.

01

01

EXAMPLE:

DISCOVER that all of the "ON" states are EQUIVALENT, merge them to yield:

"________________________" algorithm: Iterative application of simplification rule until no further simplifications can be found.

01 1

0

1

0

1

001

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Equivalent State ReductionO BSERVAT IO N: S i ­ S j IF BO TH:

1. States have identical outputs; AND2. Every input → equivalent states.

Reduction Strategy:Find pairs of equivalent states, MERGE them.

Any candidate pairs in our Ant Brain?

LOST

TR,F

F

A

TL,F

BorCTR,F

C

EorG

R

L+R

L+R

R

_R

LTL

_ _L R

_ _L R _ _

L R

_ L R

_R

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Ant Brain Synthesis:an evolutionary step

LOST

TLF

A

TL,F

BorCTR,F

EorG

R

L+R

L+R

L

REDUCED (4-state) Equivalent FSM:

Behaves exactly as previous (5-state) FSM, but requires half the ROM in its implementation!

Merge equivalent states BorC and C into a single new, combined state.

_R

_ _L R

_ _L R _ _

L R

_ L R

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Ant Brain: Circuit Diagram

(Hmmm, looks a lot like the circuit ofthe Bldg 36 Elevator Controller...)

ROM Size (bits) = ________________________________

ROMs

ioINPUTS

OUTPUTS

STATE

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States vs. BitsMost REAL digital sequential systems are FSMs:

• Registers• Counters• RAM chips• Cash machines• Video games• Personal computers• Mainframe processors.

FSM view of system state identifies STATES ;

Alternative MEMORY view of system state identifies BITS.

NUMBER OF STATES can grow EXPONENTIALLY with hardware:

• Add 1 flip flop => DOUBLE number of states• k-bit memory has 2k states!

GENERALLY:

• FSM view useful for optimizing SIMPLEdevices;

• MEMORY view useful for designing large systems.

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What makes a Bee pig out?

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Consciousness Explained?Bee “awareness” of being on the road...

Is a bee conscious of its distance from home?What dictates the bee’s feeding behavior --

Social responsibility?Peer pressure?Level of hunger?

Apparent answer:One combinational input bit (“FOOD HERE”);

andOne state bit (“got here via air”).

Is this a single bit of consciousness?Insects: a few bits of consciousnessHow many bits for an ant? A guppy? An MIT

Prof?

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Finite State Machines:an important abstraction

• FORMAL MODEL: Substantial literature, theoretical results.

• PRACTICAL IMPACT: Major engineering tool...

... You'll see FSMs for the rest of your life!

Can you believe this guy?I'll never see an FSM!

No, not with that dumb hat.