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A MODIFIED TETROLET BASED IMAGE DE-NOISING FOR REAL TIME EDGE DETECTORS
AAiT, ECE 1
By: Eyob Teshome
Advisor :Prof. Bisrat Derebssa
Addis Ababa UniversityAddis Ababa Institute of Technology
Department of Electrical and Computer Engineering
Outline• Introduction
• Background
• Statement of the problem
• Objective
• Previous works
• Methodology
Tetrolet Image decomposition
Hardware realization
• Experiments and Results
• Conclusion
• Recommendation
AAiT, ECE 2
Introduction• Image de-noising algorithms:
Involves the manipulation of the image data to produce a high quality image.
• Tetrolet Transform image decomposition:
Based on the 2D-Haar wavelet transform, adapts the image characteristics automatically.
• Edge detection algorithm:
Used to finds the sharp intensity variation of an image.
• Edge detection is an initial step in object recognition.
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Background• Haar scaling(φ(t)) and main Wavelet functions(ψ(t)).
φ(t) . ψ(t) = 0 (i.e., Orthogonal)• Three major steps:
Figure 1: Basic steps in Wavelet based image de-noising algorithm
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Background(1)• In the Standard Tetrolet transform Image decomposition,
Images are sub-divided into 4x4 Pixels. Each 4x4 Pixels is partitioned using Tetrominoes.
The Haar transform is applied to generate 4 average coefficients and 12 detailed coefficients.
Figure 1: The five free tetrominoes. O-I-T-S-L-tetromino.
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Statement of the problem
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• [1],[2],[3] The standard tetrolet transform Selects 117 Tilings for covering of each 4 × 4 Pixels with four Tetrominoes. • [1],[2] Computationally costly and needs big Storage.
[1] After J levels: Store ) coeficient values. [1] For Complete decomposition (J = log2(N) − 1 ):
• The First order gradient based edge detection algorithms are susceptible to noise.
Objective• Improve the Tetrolet transform based image de-noising algorithm. • Use the improved image de-noising algorithm as a pre-processing step for other image processing algorithms.• To design and simulate a hardware realization of the Tetrolet based image de-noising algorithm using FPGA. • Compare the performance of the software as well as the hardware design with other benchmark techniques.• To compare the software and the FPGA implementation of the system via simulation.
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Previous Works• Tetrolet transform is first proposed by Jens Krommweh [1] for image compression.• In 2010, Singh [2] proposed a new approach to the de-noising problem based on the Tetrolet transform. • He achieves up to 2 dB better PSNR compared with other published Haar wavelet based methods.• Cai-lian Li [3] improves the Tetrolet based image de-noising algorithm using the Sure [5] thresholding method.• As a result, he achieved a better PSNR and visual quality.• For the software realization, this two methods takes a significant amount of computational time.
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Methodology
Figure 3: Overall system
• Linear Operation:
The addition or multiplication of the noise to the
image signal.
• An additive noise follows the rule:
w(x, y) = s(x, y) + n(x, y) ,
• While the multiplicative noise satisfies:
w(x, y) = s(x, y)× n(x, y) ,AAiT, ECE 9
• Tetrolet based de-noising involves three steps:
Tetrolet based image decomposition
Tetrolet Coefficient Thresholding
Tetrolet based image Reconstruction
Figure 4: Basic steps in Tetrolet based image de-noising algorithmAAiT, ECE 10
Tetrolet Based Image Decomposition
x x x … xx x x … x
… … .x x x . . . x
…
…
…
…
…
…
Note: averaging/differencingof detail coefficients shown
One level, vertical Haar decomposition:
detail
average
2D-Haar
Figure 5: 2D-Haar image decomposition
𝐿𝑜𝑤𝑝𝑎𝑠𝑠 : 𝑓 (𝑋 (𝑖 ) )=(𝑋 (𝑖 )+𝑋 (𝑖+1 ))√2
h𝐻𝑖𝑔 𝑝𝑎𝑠𝑠 :𝑔 (𝑋 (𝑖 ) )=(𝑋 (𝑖 )−𝑋 (𝑖+1 ))√2
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…
Tetrolet Based Image Decomposition(1)• The generalization of 2-D classical Haar wavelet transform.
Figure 6: The 5 free Tetrominoes: O - I - T - S - L.
Figure 7: The Tetrolet based image decomposition
x x x x … xx x x x … xx x x xx x x x
… … .x x x x . . . x
Tetrolet Partitions:…
…
…
…
…
… … .
…
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Tetrolet Based Image Decomposition(2)• 2D Haar DWT/DTT using filter banks(Analysis)
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Modify the Tetrolet Image de-composition• Only the 15 best Tilings are selected out of 117 Possible coverings.
Figure 8: The 15 selected Tetromino configurations.
Figure 9: The 22 fundamental forms tiling a 4 x 4 PixelsAAiT, ECE 14
Modify the Tetrolet Image de-composition(1)• An Improved Tetrolet based image de-noising algorithm flowchart.
15AAiT, ECE
Hardware Design• The whole design incorporates three stages.
Stage one is the Tetrolet based image decomposition with thresholding Stage two is the Tetrolet based image reconstruction The third stage is Sobel edge detection algorithm
• FDTT image decomposition is designed as a hierarchical scheme: Uses 1-D processing module twice to represent 2-D processing. The module can be used repeatedly on the same image for multilevel processing. Three of the first Tetrolet partitions are implemented. Figure 10: The first three Tetrolet partitions.
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Hardware Design(1)
• The proposed algorithm of the DFTT is divided into three phases:
Initializing phase, Horizontal Pixel phase and
Vertical Pixel phase.
Figure 11: Layout of the proposed architecture for the FDTT
• Memory: Modeled using non-synthesizable VHDL code for
simulation only.AAiT, ECE 17
Hardware Design(2)• The Low and High pass components for FTT image decomposition
[Low pass] [High pass]
• The original pixels values could be retrieved in IDTT process from the clean High and Low pas components.
• [7] The VHDL implementation of Sobel edge detection algorithm involves:
The convolution of the 3x3 masks with image pixels,
The gradient magnitude and the direction of the intensity variation,
The comparison of the magnitude value with the threshold value.
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Experimental Setup(Software)• The algorithms were tested in MATLAB (without C routines).
• Single level image decomposition.
• Performance Metrics: based on the execution time and the PSNR values.
[7]
Where x and y are the clean and estimated samples respectively.
• The Cameraman Test image, a size of 512x512,
• The Test image format used is the Gray Scale format.
• Processor: Intel Pentium Dual CPU T3400 @2.16GHz @2.17GHz
• Installed memory (RAM): 3.00GB
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20
Results
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5 10 15 20 25 30 35 40 450
5
10
15
20
25
30
35
40
De-noising Algorithms for Cameraman Image
TetroletMtetroletR.haarBayesThre.SoftThre.Noisy
Noise Standard Deviation(Sigma)
PSN
R in
dB
Image Noisy VisuHard
VisuSoft
Sure Bayes R-haar Tetrom Modified Tetrolet
Avg. Exec. Time(in sec)
- ≈0.32506
≈0.34547
≈0.34222
≈0.33863
≈0.94957
≈20min
≈7.3693
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Result(1)
Noisy Image
Hard Soft Sure Bayes R.Haar Tetrolet Mod. Tetrolet
0
5
10
15
20
25
σ=10σ=20σ=30
De-noising Methods with Sobel
PS
NR
in d
B
AAiT, ECE
Noisy Image
Hard Soft Sure Bayes R.Haar Tetrolet Mod. Tetrolet
0
5
10
15
20
25
σ=10σ=20σ=30
De-noising methods with Roberts
PS
NR
in
dB
Experimental Setup(Hardware)• The design is synthesized using Xilinx XST Synthesis tool
• Simulated using ModelSim SE Simulation Tool Environment.
• Hardware Platform:
Xilinx Virtex®-4 FPGA (XC4VSX Series).
• Input image:
White Gaussian noise corrupted 128x128 Cameraman
image.
• Picture data are 8-bit pixels.
• A Text file is used as input for test bench configurations for
simulation.
• Data Converter application accompanies this thesis:
Read an image in ‘jpg’ format and store its contents in
‘txt’ format, AAiT, ECE 22
Device utilization FDTT
Table 3: Device utilization FDTT for different Tetrolet Partitions
Device Utilization Summary
Logic Utilization
Available
2D-HAAR 2TETROLET. 3TETROLET15TETR.
Used
Utilization
Used
Utilization
Used
Utilization
Utilization
Number of Slices 10240 383 3% 522 5% 797 7% ≈ 31%
Number of Slice Flip Flops
20480 279 1% 365 1% 542 2% ≈ 15%
Number of 4 input LUTs 20480 716 3% 976 4% 145
4 7% ≈ 31%
Number of bonded IOBs 320 36 11% 36 11% 36 11% ≈ 11%
Number of GCLKs 32 1 3% 1 3% 1 3% ≈ 3%
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REAL-TIME PERFORMANCE
• FDTT has the maximum frequency (168.297MHz). No.
Table 4: Review of No. of clock cycle and Timing for FDTT and 2D Haar image decomposition
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Stage of
design
No. Tetrolet
partitions
Execution
time(ns)
No. of
Clock
cycles
Maximum
Frequency(M
Hz)
Time duration
of Clock
period (ns)
1D-Haar 6102625 122053 203.934 50
One (2D-
Haar)
9157075 183142 189.418 50
Two 1221152
5
244231 195.409 50
Three 2137487
5
427984 168.297 50
Fifteen ≈
9163350
0
≈
1832670
≈ 50
Conclusion• Tetrolet based de-noising is much more computationally intensive
while providing a better result.
• The modified image de-noising algorithm has comparably as equal
quality as the previous Tetrolet based image de-noising algorithm.
• The FPGA design of the Tetrolet image decomposition algorithm is
running at a maximum frequency of 168.297MHz targeting Virtex-4
FPGA.
• In addition, the entire VHDL utilized only 9% of the total logic
elements available on this FPGA.
• FPGA based implementation of Tetrolet based image de-noising results
in significant improvement in terms of speed over the Software
realization. AAiT, ECE 25
Recommendation• With Tetrolet transform, a good result can be brought for Poisson
noise and Speckle noise.
• For the software realization, if the vectoring of loops further
exploited, the execution time can be improved more.
• It is recommended to realize and check the performance of the full
Tetrolet transform based de-noising on FPGA.
• The Sobel edge detection is synthesized for only 64x64 image
sizes due to the fact that Xilinx ISE only support loops with 64
maximum iterations.
• This issue is not solved for this thesis. It is left as a future work.AAiT, ECE 26
Main References[1] J. Krommweh, ”Tetrolet transform: A new adaptive Haar wavelet algorithm for sparse image representation ”, Journal of Visual Communication and Image Representation, Vol. 21, no. 4, pp. 364–374, 2010.
[2] Singh, Manish Kumar, "de-noising of natural images using the wavelet transform" (2010). Master's Theses, Paper 3895.
[3] Cai-lian Li, Ji-xiang Sun and Yao-hong Kang, "A new algorithm for image denoising based on Tetrolet transform", International Conference on Image Processing and Pattern Recognition in Industrial Engineering, Volume 7820, pp. 78201L-78201L-7 (2010).
[4] M. Korn, Geometric and algebraic properties of polyomino tilings, PhD thesis, Massachusetts Institute of Technology (2004).
[5] David L. Donoho and Iain M. Johnstone. “Adapting to Unknown Smoothness via Wavelet Shrinkage.” Journal of the American Statistical Association, Vol. 90, No. 432, pp. 1200-1224, Dec. 1995.
[6] An improved Sobel edge detection, Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on 9-11 July 2010.
[7] CNRS, CEREMADE, University Paris-Dauphine.
Internet: http://www.ceremade.dauphine.fr/~peyre/
[8] VHDL Design Representation and Synthesis (2nd Edition), James R. Armstrong, F. Gail Gray . Prentice Hall, April 9, 2000.AAiT, ECE 27
THANK YOU!
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