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AIN SHAMS UNIVERSITY FACULTY OF ENGINEERING

Electronics and Communications Engineering Department

Design and Implementation of Radar Pulse Compression A Thesis

Submitted in partial fulfillment of the requirements of the degree ofMaster of Science in Electrical Engineering

Submitted by

Hossam Ahmed Said Mohamed Hanafy

B.Sc. of Electrical Engineering (Electronics and Communications Engineering) Alexandria University, 2003

Supervised By

Prof. Adel Ezzat El-Hennawy

Dr. Abd El-Lateef El-Kouny Cairo, 2014


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1. Introduction2. Basic Concepts3. Matched Filter

4. Types of pulse compression5. Mathematical Model of LFM PulseCompression

6. Design of LFM Pulse Compression7. Implementation of LFM Pulse

Compression8. Hardware Results9. Conclusion


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1 INTRODUCTION


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2

ct R


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2 BASIC CONCEPTS

a Definitions

b Range Resolution

c

Motivation of Pulse Compression

d Radar Block Diagram


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Target Range:

Inter pulse period (IPP) and Pulse repetition frequency:

Duty Cycle =

2t c R

IPP PRF /1

T dt /

dt P P t av


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An example, two targets with to small spacing:

And now the other example: the spacing is large enough


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1 Short pulses are used to increase range resolution.

2

Short pulses = decreased average power.

3

Decreased average power = Decreased detection

capability.

4

Pulse compression = Increased average power +Increased Range resolution.


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3 MATCHED FILTER

a Matched Filter Concepts

b Matched Filter Basics


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4 TYPES OF PULSE COMPRESSION

a Phase Coded

b

Linear Frequency Modulation(LFM)


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5

MATHEMATICAL MODEL OFLFM PULSE COMPRESSION

a Correlation Processing

b Stretch Processing

c Modeling of LFM Pulse Compression


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)(t S R c

RT

)(c

Rt S

)(.c

Rt S

)2

(.c R

t S


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M

i

iir

M

iiir

r

M

i ii

t S t S

t t S t S

t ht S t S

t t h

1

1

1

)()(

)(*)()(

)(*)()(

)()(


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)()( * t S t hr

)(*)(*)()(

)(*)()(S*

o

t ht S t S t S

t ht S t

o

r r

)()()(

)()()()(2

*

jw H jS jS

j H jS jS jS

o

o


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)()( jkH jS o

M

iiio

o

t k t S

t kht S

1

)()(

)()(


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)2

(2)( 2t K t f t c

Where B

K 2

Kt f t f t dt

d

t f c )(

)(2

1

)(


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)2

(2 2

)()(t

K t f j c

e

T

t rect t S


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)(*)()( t ht S t S o duut S uhduut huS t S o )()()()()(

due

T ut

rect eeT u

rect et S ut f jut K ju f j Ku jo cc )(2)(2 )()()(

22


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t f jo

ceT t

rect KTt

t T t K

T t S

2)

2(

1sin

)(

)2

()()(T t

rect Bt TSat S o


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6

DESIGN OF LFM PULSECOMPRESSION

a LFM-1

b LFM-2

c

LFM-3

d LFM-4

D i S f LFM P l C i


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Design Steps of LFM Pulse Compression


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LFM-1Phase Curve


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LFM-1

Frequency Curve

LFM-1Frequency Curve


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LFM-1Amplitude Curve


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LFM-1Resolving 1 Target


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LFM-1Resolving Multi Targets


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LFM-1Problem


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LFM-2Phase Curve


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2


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LFM-2LFM-2Over Clocking

LFM 2


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LFM-2Over Clocking

LFM 3


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LFM-3Phase Curve

LFM 3


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LFM 3


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LFM 3


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LFM 3


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LFM 3


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LFM 3


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LFM-3Over Clocking

LFM 3


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LFM-3Over Clocking

LFM 4


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LFM-4Phase Curve

LFM 4


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LFM 4


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LFM 4


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LFM 4


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LFM 4


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7

IMPLEMENTATION OF LFMPULSE COMPRESSION

a FPGA

b Generation of LFM waveform

c Processing of LFM Waveform


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8,256 Logic Elements 36 M4K RAM blocks 165,888 Total RAM bits 18 Embedded Multiplier 2 PPLs 182 maximum user I/O

pins

The Cyclone II FPGAdevelopment kit (Red Core)comes with ALTERA(EP2C8Q208C8N) chip


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1 Reduction of Hardware complicity, size and cost.

2 Availability for R & D future works.

3

High MTBF (Mean Time Between Failures).4

Low MTR (Mean Time to Repair).

5 Low power consumption.

6 Preventing errors due to backplanes, inner cables connections

using in classic hardware design.

7 Reduction of error due to high speed data rate (50 MHz).


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Phasor Concept 180 deg Phasor Concept 180 deg


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old old new Q I I 83

6459

Phasor Concept 22.5 deg


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8 PRACTICAL RESULTS

a Generation

b Processing


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9 CONCLUSION


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A software model was developed to simulate a practical LFM pulsecompression system

LFM-1 Achieved27dB SNRDC

coupling

Frequenciesaround

zero

LFM-2 Achieved15dB SNR Bad

resolutioncapability

Overclocking

complicityof thedesign

Enhancedthe

resolution

DecreaseSNR to13dB.

LFM-3 Achieved27dB SNRFull

suppression forfrequenciesaround zero

Pairedecho

Canceledusing

paired filter

Overclocking

Paired echolevel wasreduced

Decreasingthe SNR.

LFM-4 Achieved29dB SNRFull

suppression forfrequenciesaround zero

Withoutcomplicity

(over clocking)

Hardware was designed and implemented using FPGA kit(Red Core) with CYCLONE II (EP2C8Q208C8N) chip.

Phase Vector Rotation

HardwareResults SNR 29dB Pulse width 480 ns Resolution 72m


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