Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development
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Transcript of Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development
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Final FED 1 Testing Set Up
• Testing idea and current status• Preliminary results• Future development• Summary
M. Noy
29-01-2003
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M. Noy
29-01-2003
Some known (and relevant)
signal
FF1 (real)
FF1 emulator (SW)
SW comparison of processed
data
Analysis of functionality
(later pass/fail)Software Control
Data processing
Testing idea
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M. Noy
29-01-2003
System status
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M. Noy
29-01-2003
DAC Vocm
VME interface for PC control
digital sequencer 40MHz
12 bit DAC and fully differential op-amp with
common mode offset
analogue opto-tx
010
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M. Noy
29-01-2003
VME interface logic
Analogue section
Sequence control logic
Sequence storage
DACAmplification+cmAnalogue opto-tx
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M. Noy
29-01-2003
Software
I have developed software using XDAQ and the HAL
FedTesterObject: encapsulates functionality interface
FedTesterApplication: instantiates a (the) FedTesterObject(s); inherits from xdaqApplication and FedTesterSOAPCommandListener
Plus additional required SO class
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M. Noy
29-01-2003
Results from the system: preliminary
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M. Noy
29-01-2003
Analogue square wave, period 50ns.
(channel 0, bias setting 0x17, gain setting 1)
10% to 90% rise time:3.60.2 ns
90% to 10% fall time:3.40.2 ns
Settling time believed to be better than 17ns,
analogue noise believed to be less than 10mV, but not
characterised yet.
The optical output is fed into the first Optobahn opto-rx version, through 50 co-ax, into a 50
terminated scope.
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M. Noy
29-01-2003
Linearity looks sufficient, but no
detailed measurements
have been made yet.
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M. Noy
29-01-2003
Muxed pair of APV25 frames with
pedestals only.
pedestalsErrorbitsHeader
ticks
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M. Noy
29-01-2003
Muxed pair of APV25 frames with a 1 MIP (approx.) hit
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M. Noy
29-01-2003
HIP event: from the X5 beam test data.
R. Bainbridge,M. Takahashi
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M. Noy
29-01-2003
Development
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VME
Clock and trigger distribution (propagation matched lines)
Master trigger in
4x6U VME cardsActing master
M. Noy
29-01-2003
4 identical VME boards 6U in size
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M. Noy
29-01-2003
Single Board
1 back end module controlling synchronisation and 4 front end modules
Mas
ter
trig
gers
in
Sla
ve tr
igge
r an
d cl
ock
BE to FE bus
with clock
and L1A
VME
BEV2
Temp unit
Front End
Modules
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SRAM - optional add on, 512kB x 36 @80MHz
Front End Virtex 2
DAC x6Op-amp x6
3 channel analogue opto-tx
3 channel analogue opto-tx
I2C from BE
I2C from BE Serial connection from BE
Clock and Trigger from BE
Opt
ical
out
puts
To temp unit
M. Noy
29-01-2003
Single Front End Module
6 DAC 6 op-amp 2 analogue opto-tx-hybrid (current layout)
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M. Noy
29-01-2003
Summary
The optical test board works, and will be used to test the FF1.Have a 9U crate, VME64x backplane, and 3.3v psu at IC.
Software for the set up is functional, we can produce test vectors and sequence tests. Some work is required to make it more user-friendly.
The next optical test card is being developed to provide multiple individually configurable channels, stepping towards more automation ( production testing)