Final Code

Final Code--

-- VHDL Architecture Sushant_Mongia_Project1_lib.uart.rtl

--

-- Created:

-- by - SUSHANT MONGIA.UNKNOWN (SUSHANT)

-- at - 23:28:23 10/13/2013

--

-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)

--

-------------------------------------------------------

-- Design Name : uart

-- File Name : uart.vhd

-- Function : Simple UART

-- Coder : SUSHANT MONGIA

-------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity uart is

port (

reset :in std_logic;

txclk :in std_logic;

ld_tx_data :in std_logic;

tx_data :in std_logic_vector (7 downto 0);

tx_enable :in std_logic;

tx_out :out std_logic;

tx_empty :out std_logic;

rxclk :in std_logic;

uld_rx_data :in std_logic;

rx_data :out std_logic_vector (7 downto 0);

rx_enable :in std_logic;

rx_in :in std_logic;

rx_empty :out std_logic

);

end entity;

architecture rtl of uart is

-- Internal Variables

signal tx_reg :std_logic_vector (7 downto 0);

signal tx_over_run :std_logic;

signal tx_cnt :std_logic_vector (3 downto 0);

signal rx_reg :std_logic_vector (7 downto 0);

signal rx_sample_cnt :std_logic_vector (3 downto 0);

signal rx_cnt :std_logic_vector (3 downto 0);

signal rx_frame_err :std_logic;

signal rx_over_run :std_logic;

signal rx_d1 :std_logic;

signal rx_d2 :std_logic;

signal rx_busy :std_logic;

signal rx_is_empty :std_logic;

signal tx_is_empty :std_logic;

begin

-- UART RX Logic

process (rxclk, reset) begin

if (reset = '1') then

rx_reg '0');

rx_data '0');

rx_sample_cnt '0');

rx_cnt '0');

rx_frame_err