FIN FET TECHNOLOGY

INTRODUCTION Silicon CMOS has emerged as the predominant

technology in the semiconductor industry. The concept of device scaling has consistently

resulted in better device density and performance.

The industry roadmap for CMOS technology suggests that we may be reaching some physical limitations as well as practical technological barriers to continuous scaling.

We are expected to reach the limit value of 35nm for the gate length by 2010

CONTD……. As the downscale of CMOS technology

approaches physical limitations, the need arises for alternative device structures.

Many novel structures have been proposed for the nano scale regime.

One such structure is the Double-Gate Transistor, proposed in the 1980s.

Other possible solutions inclue SOI devices,strained-silicon FETs, carbon nanotube FETs Etc.

DOUBLE GATE FETS

BULK CMOS

DG –FET NON SI NANO DEVICE

Gap

Feature size 10 nm 32nm

DG-FETs can be used to fill this gapare extensions of CMOSManufacturing processes similar to CMOS

WHY DG FET??Reduction of short channel effects (SCE)– Increased Ioff– Decreased VT due to reduced channeldepletion chargeMaintaining good electrical

characteristics– High Ion/Ioff ratio– Sharp I-V slopeKeeping fabrication process simple– Addition of steps to existing processes

WHAT IS A DG-FET?Double gate MOSFETs (DG-FET) is

a MOSFET that has two gates to control the channel

TYPES Three possible realizations of DGFETs

TYPE 1 TYPE 2 TYPE 3

Types 1 and 2 suffer most from fabrication problems

it is hard to fabricate both gates of the same size and that too exactly aligned to each other.

Also, it is hard to align the source/drain regions exactly to the gate edges

Type 1 DG-FETs, it is hard to provide a low-resistance, area-efficient contact the bottom gate, since it is buried

Type 3 DG FET is commonly used.

WHAT IS A FINFET?Type 3 DG-FETs are called FinFETs.• Here the channel has been “turned

on its edge” and made to stand up

Si Fin

CONTD……….Because of the vertically thin channel

structure, it is referred to as a fin because it resembles a fish’s fin; hence the name FinFET.

Both the gates of a FinFET can be independently controlled

Back GateOxide insulation

CONTD……

Amongst the DG-FET types, the FinFET is the easiest one to

fabricate. A gate can also be fabricated at

the top of the fin, in which case it is a triple gate FET.

WHY FIN-FET?? Having excellent control of short

channel effects in submicron regime and making transistors still scalable.

Due to this reason, the small- length transistor can have a larger intrinsic gain compared to the bulk counterpart.

Lower off-state current compared to bulk counterpart.

CONTD……….Raised source/drain to reduce parasitic

resistance and improve currrent driveSymmetric gates yield great

performance Finfets are designed to use multiple

fins to achieve larger channel widths. As the number of fins is increased the

current through the device increases.Promising matching behavior.

FINFET FABRICATIONThe key challenges in FinFET

fabrication are the thin, uniform fin; and also in reducing the source-drain series resistance.

FinFET’s are fabricated in 2 ways:Gate-first process: Here the gate stack

is patterned/formed first, and then the source and drain regions are formed

Gate-last process: Here source and drain regions are formed first and then the gate is formed

CONTD………FinFET’s are usually fabricated on an

SOI substrate. It starts by patterning and etching

thin fins on the SOI wafer using a hard mask.

The hard mask is retained throughout the process to protect the fin.

The fin thickness is typically half or one third the gate length, so it is a very small dimension.

CONTD………In the gate-first process, fabrication

steps after the fin formation are similar to that in a conventional bulk MOSFET process.

In the gate-last process, the source/drain is formed immediately after fin patterning.

To protect the fin while forming the other regions, doped poly or poly SiGe or even doped amorphous Silicon is deposited on the fin.

APPLICATIONS Low power design in digital

circuit, such as RAM, because of its low off-state current.

Power amplifier or other application in analog area which requires good linearity.

High speed switching applications

CONCLUSION The introduction of FinFET

Technology has opened new chapters in Nano-technology.

Simulations show that FinFET structure could be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects.

It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability. 

REFERENCES EEs801 Seminar report FinFETS

Venkatnarayan Hariharan http://en.wikipedia.org/wiki/Multigate_device

#FinFETs

http://www.eeel.nist.gov/812/conference/2009_presentations/Vandervorst.pdf

www.rit.edu/~w-ue/ameccontent/3_Rahman.pdf

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