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2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND = V-) - ±18V Terminal Voltage Range (DGND = V- + 18V) Wide Operating Voltage: - Analog: 10V to 36V (specified performance) - Digital: 2.7V to 5.5V 1.8V to 5.5V (DGND V- + 0.9V) Single Resistor Network Potentiometer Configuration Options Resistor Network Resolution - 7-bit: 127 resistors (128 Taps) - 8-bit: 255 resistors (256 Taps) •R AB Resistance Options: - 5k 10 k - 50k 100 k High Terminal/Wiper Current (I W ) Support: - 25 mA (for 5 k) - 12.5 mA (for 10 k) - 6.5 mA (for 50 k and 100 k) Zero-Scale to Full-Scale Wiper Operation Low Wiper Resistance: 75 (Typical) Low Temperature Coefficient: - Absolute (Rheostat): 50 ppm typical (0°C to +70°C) - Ratiometric (Potentiometer): 15 ppm typical SPI Serial Interface (10 MHz, Modes 0,0 and 1,1) Resistor Network Terminal Disconnect Via: - Shutdown pin (SHDN ) - Terminal Control (TCON) register Write Latch (WLAT ) Pin to Control Update of Volatile Wiper Register (such as Zero Crossing) Power-on Reset/Brown-out Reset for Both: - Digital supply (V L /DGND); 1.5V typical - Analog supply (V+/V-); 3.5V typical Serial Interface Inactive Current (3 μA Typical) 500 kHz Typical Bandwidth (-3 dB) Operation (5.0 k Device) Extended Temperature Range (-40°C to +125°C) Package Types: TSSOP-14 and VQFN-20 (5x5) Package Types Description The MCP41HVX1 family of devices have dual power rails (analog and digital). The analog power rail allows high voltage on the resistor network terminal pins. The analog voltage range is determined by the V+ and V- voltages. The maximum analog voltage is +36V, while the operating analog output minimum specifications are specified from either 10V or 20V. As the analog supply voltage becomes smaller, the analog switch resistances increase, which affects certain performance specifica- tions. The system can be implemented as dual rail (±18V) relative to the digital logic ground (DGND). The device also has a Write Latch (WLAT ) function, which will inhibit the volatile wiper register from being updated (latched) with the received data until the WLAT pin is low. This allows the application to specify a con- dition where the volatile wiper register is updated (such as zero crossing). MCP41HVX1 Single Potentiometer 1 2 3 4 11 12 13 14 V- P0B DGND P0W 5 6 7 8 9 10 V+ NC (2) P0A SCK V L SHDN WLAT CS SDO SDI 1 2 3 4 14 15 17 18 NC (2) NC (2) 6 7 8 9 12 13 P0B P0W V- NC (2) NC (2) SHDN SDI V L CS SCK 19 20 WLAT NC (2) NC (2) P0A 5 SDO 10 NC (2) 11 DGND 16 V+ 21 EP (1) Note 1: Exposed Pad (EP) 2: NC = Not Internally Connected TSSOP (ST) 5 x 5 VQFN (MQ) 7/8-Bit Single, +36V (±18V) Digital POT with SPI Serial Interface and Volatile Memory

Transcript of file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1...

Page 1: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX178-Bit Single +36V (plusmn18V) Digital POT

with SPI Serial Interface and Volatile Memory

Featuresbull High-Voltage Analog Support

- +36V Terminal Voltage Range (DGND = V-)

- plusmn18V Terminal Voltage Range (DGND = V- + 18V)

bull Wide Operating Voltage

- Analog 10V to 36V (specified performance)

- Digital 27V to 55V 18V to 55V (DGND V- + 09V)

bull Single Resistor Network

bull Potentiometer Configuration Options

bull Resistor Network Resolution

- 7-bit 127 resistors (128 Taps)

- 8-bit 255 resistors (256 Taps)

bull RAB Resistance Options

- 5 k 10 k- 50 k 100 k

bull High TerminalWiper Current (IW) Support

- 25 mA (for 5 k)

- 125 mA (for 10 k)

- 65 mA (for 50 k and 100 k)

bull Zero-Scale to Full-Scale Wiper Operation

bull Low Wiper Resistance 75 (Typical)

bull Low Temperature Coefficient

- Absolute (Rheostat) 50 ppm typical(0degC to +70degC)

- Ratiometric (Potentiometer) 15 ppm typical

bull SPI Serial Interface (10 MHz Modes 00 and 11)

bull Resistor Network Terminal Disconnect Via

- Shutdown pin (SHDN)

- Terminal Control (TCON) register

bull Write Latch (WLAT) Pin to Control Update ofVolatile Wiper Register (such as Zero Crossing)

bull Power-on ResetBrown-out Reset for Both

- Digital supply (VLDGND) 15V typical

- Analog supply (V+V-) 35V typical

bull Serial Interface Inactive Current (3 microA Typical)

bull 500 kHz Typical Bandwidth (-3 dB) Operation (50 k Device)

bull Extended Temperature Range (-40degC to +125degC)

bull Package Types TSSOP-14 and VQFN-20 (5x5)

Package Types

DescriptionThe MCP41HVX1 family of devices have dual powerrails (analog and digital) The analog power rail allowshigh voltage on the resistor network terminal pins Theanalog voltage range is determined by the V+ and V-voltages The maximum analog voltage is +36V whilethe operating analog output minimum specifications arespecified from either 10V or 20V As the analog supplyvoltage becomes smaller the analog switch resistancesincrease which affects certain performance specifica-tions The system can be implemented as dual rail(plusmn18V) relative to the digital logic ground (DGND)

The device also has a Write Latch (WLAT) functionwhich will inhibit the volatile wiper register from beingupdated (latched) with the received data until the WLATpin is low This allows the application to specify a con-dition where the volatile wiper register is updated (suchas zero crossing)

MCP41HVX1 Single Potentiometer

1234 11

121314

V-P0B

DGND

P0W

567 8

910

V+

NC (2)

P0ASCKVL

SHDNWLAT

CS

SDOSDI

1

2

3

4

14

151718

NC

(2)

NC

(2)

6 7 8 9

12

13 P0B

P0W

V-

NC

(2)

NC

(2)

SH

DN

SDI

VL

CS

SCK

1920

WL

AT

NC

(2)

NC

(2)

P0A

5SDO

10

NC

(2)

11 DGND

16

V+

21 EP(1)

Note 1 Exposed Pad (EP) 2 NC = Not Internally Connected

TSSOP (ST)

5 x 5 VQFN (MQ)

2013-2015 Microchip Technology Inc DS20005207B-page 1

MCP41HVX1

Device Block Diagram

Device Features

Device

o

f P

OTs

Wiper Configuration

Co

ntr

ol

Inte

rfac

e

PO

R W

iper

S

etti

ng

Resistance (Typical)Number

of Specified Operating

Range

RAB Options (k)

Wiper - RW () R

S

Tap

s

VL(2) V+(3)

MCP41HV31 1 Potentiometer (1) SPI 3Fh50 100

500 100075 127 128

18V to 55V

10V(4) to 36V

MCP41HV51 1 Potentiometer (1) SPI 7Fh50 100

500 100075 255 256

18V to 55V

10V(4) to 36V

MCP45HV31(5) 1 Potentiometer(1) I2Ctrade 3Fh50 100

500 100075 127 128

18V to 55V

10V(4) to 36V

MCP45HV51(5) 1 Potentiometer (1) I2C 7Fh50 100

500 100075 255 256

18V to 55V

10V(4) to 36V

Note 1 Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor)

2 This is relative to the DGND signal There is a separate requirement for the V+V- voltages VL V- + 27V

3 Relative to V- the VL and DGND signals must be between (inclusive) V- and V+

4 Analog operation will continue while the V+ voltage is above the devicersquos analog Power-on Reset (POR)Brown-out Reset (BOR) voltage Operational characteristics may exceed specified limits while the V+ voltage is below the specified minimum voltage

5 For additional information on these devices refer to DS20005304

Power-upBrown-outControl

VL

DGND

SPI SerialInterfaceModule andControlLogic Resistor

Network 0(Pot 0)

Wiper 0 and TCONRegister

CS

SCK

SDI

SDO

SHDN

Memory (2x8)

Wiper0 (V)

TCON

P0A

P0W

P0B

V+ Vndash

WLAT

Power-upBrown-outControl(Analog)

(Digital)

DS20005207B-page 2 2013-2015 Microchip Technology Inc

MCP41HVX1

10 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings dagger

Voltage on V- with respect to DGND DGND + 06V to -400V

Voltage on V+ with respect to DGND DGND - 03V to 400V

Voltage on V+ with respect to V- DGND - 03V to 400V

Voltage on VL with respect to V+ -06V to -400V

Voltage on VL with respect to V- -06V to +400V

Voltage on VL with respect to DGND -06V to +70V

Voltage on CS SCK SDI WLAT and SHDN with respect to DGND -06V to VL + 06V

Voltage on all other pins (PxA PxW and PxB) with respect to V- -03V to V+ + 03V

Input clamp current IIK (VI lt 0 VI gt VL VI gt VPP on HV pins) plusmn20 mA

Output clamp current IOK (VO lt 0 or VO gt VL) plusmn20 mA

Maximum current out of DGND pin 100 mA

Maximum current into VL pin 100 mA

Maximum current out of V- pin 100 mA

Maximum current into V+ pin 100 mA

Maximum current into PXA PXW amp PXB pins (Continuous) RAB = 5 k plusmn25 mARAB = 10 k plusmn125 mARAB = 50 k plusmn65 mARAB = 100 k plusmn65 mA

Maximum current into PXA PXW amp PXB pins (Pulsed) FPULSE gt 10 kHz (Max IContinuous)(Duty Cycle)

FPULSE 10 kHz (Max IContinuous)(Duty Cycle)

Maximum output current sunk by any Output pin 25 mA

Maximum output current sourced by any Output pin 25 mA

Package Power Dissipation (TA = + 50degC TJ = +150degC) TSSOP-14 1000 mWVQFN-20 (5x5) 2800 mW

Soldering temperature of leads (10 seconds) +300degC

ESD protection on all pins Human Body Model (HBM) plusmn4 kVMachine Model (MM) plusmn400VCharged Device Model (CDM) for TSSOP-14 plusmn1 kV

Maximum Junction Temperature (TJ) 150degCStorage temperature -65degC to +150degCAmbient temperature with power applied -40degC to +125degC

dagger Notice Stresses above those listed under ldquoMaximum Ratingsrdquo may cause permanent damage to the device Thisis a stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operational listings of this specification is not implied Exposure to maximum rating conditions for extended periodsmay affect device reliability

2013-2015 Microchip Technology Inc DS20005207B-page 3

MCP41HVX1

ACDC CHARACTERISTICS

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Digital Positive Supply Voltage (VL)

VL 27 mdash 55 V With respect to DGND(4)

18 mdash 55 V DGND = V- + 09V (referenced to V-)(14)

mdash mdash 0 V With respect to V+

Analog Positive Supply Voltage (V+)

V+ VL(16) mdash 360 V With respect to V-(4)

Digital Ground Voltage (DGND)

VDGND V- mdash V+ - VL V With respect to V-(45)

Analog Negative Supply Voltage (V-)

V- -360 + VL mdash 0 V With respect to DGND and VL = 18V

Resistor Network Supply Voltage

VRN mdash mdash 36V V Delta voltage between V+ and V-(4)

VL Start Voltage to ensure Wiper Reset

VDPOR mdash mdash 18 V With respect to DGND V+ gt 60V RAM retention voltage (VRAM) lt VDBOR

V+ Voltage to ensure Wiper Reset

VAPOR mdash mdash 60 V With respect to V- VL = 0V RAM retention voltage (VRAM) lt VBOR

Digital to Analog Level Shifter Operational Voltage

VLS mdash mdash 23 V VL to V- voltage DGND = V-

Power Rail Voltages during Power-Up(1)

VLPOR mdash mdash 55 V Digital Powers (VLDGND) up 1st V+ and V- floating oras V+V- powers up(V+ must be to DGND)(18)

V+POR mdash mdash 36 V Analog Powers (V+V-) up 1st VL and DGND floatingoras VLDGND powers up (DGND must be between V- and V+)(18)

VL Rise Rate to ensure Power-on Reset

VLRR Note 6 Vms With respect to DGND

Note 1 This specification is by design

Note 4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digitallogic DGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

Note 5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for oper-ation equals 18V So 36V - 18V = 342V

Note 6 PORBOR is not rate dependent

Note 16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

Note 18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analogand Digital) should have a common reference to ensure that the driven DGND voltage is not at a higherpotential than the driven V+ voltage

DS20005207B-page 4 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Delay after device exits the reset state (VL gt VBOR)

TBORD mdash 10 20 micros

Supply Current(7) IDDD mdash 45 300 microA Serial Interface Active Write all 0rsquos to Volatile Wiper 0 (address 0h)VL = 55V CS = VIL FSCK = 5 MHz V- = DGND

mdash mdash 7 microA Serial Interface Inactive VL = 55V SCK = VIH CS = VIH Wiper = 0 V- = DGND

IDDA mdash mdash 5 microA Current V+ to V- PxA = PxB = PxW DGND = V- +(V+2)

Resistance(plusmn 20)(8)

RAB 40 5 60 k -502 devices V+V- = 10V to 36V

80 10 120 k -103 devices V+V- = 10V to 36V

400 50 600 k -503 devices V+V- = 10V to 36V

800 100 1200 k -104 devices V+V- = 10V to 36V

RAB Current IAB mdash mdash 900 mA -502 devices 36V RAB(MIN) V- = -18V V+ = +18V(9)

mdash mdash 450 mA -103 devices

mdash mdash 090 mA -503 devices

mdash mdash 045 mA -104 devices

Resolution N 256 Taps 8-bit No Missing Codes

128 Taps 7-bit No Missing Codes

Step Resistance(see Appendix B4)

RS mdash RAB(255) mdash 8-bit Note 1

mdash RAB(127) mdash 7-bit Note 1

Note 1 This specification is by design

Note 7 Supply current (IDDD and IDDA) is independent of current through the resistor network

Note 8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

Note 9 Guaranteed by the RAB specification and Ohms Law

2013-2015 Microchip Technology Inc DS20005207B-page 5

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 2: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

Device Block Diagram

Device Features

Device

o

f P

OTs

Wiper Configuration

Co

ntr

ol

Inte

rfac

e

PO

R W

iper

S

etti

ng

Resistance (Typical)Number

of Specified Operating

Range

RAB Options (k)

Wiper - RW () R

S

Tap

s

VL(2) V+(3)

MCP41HV31 1 Potentiometer (1) SPI 3Fh50 100

500 100075 127 128

18V to 55V

10V(4) to 36V

MCP41HV51 1 Potentiometer (1) SPI 7Fh50 100

500 100075 255 256

18V to 55V

10V(4) to 36V

MCP45HV31(5) 1 Potentiometer(1) I2Ctrade 3Fh50 100

500 100075 127 128

18V to 55V

10V(4) to 36V

MCP45HV51(5) 1 Potentiometer (1) I2C 7Fh50 100

500 100075 255 256

18V to 55V

10V(4) to 36V

Note 1 Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor)

2 This is relative to the DGND signal There is a separate requirement for the V+V- voltages VL V- + 27V

3 Relative to V- the VL and DGND signals must be between (inclusive) V- and V+

4 Analog operation will continue while the V+ voltage is above the devicersquos analog Power-on Reset (POR)Brown-out Reset (BOR) voltage Operational characteristics may exceed specified limits while the V+ voltage is below the specified minimum voltage

5 For additional information on these devices refer to DS20005304

Power-upBrown-outControl

VL

DGND

SPI SerialInterfaceModule andControlLogic Resistor

Network 0(Pot 0)

Wiper 0 and TCONRegister

CS

SCK

SDI

SDO

SHDN

Memory (2x8)

Wiper0 (V)

TCON

P0A

P0W

P0B

V+ Vndash

WLAT

Power-upBrown-outControl(Analog)

(Digital)

DS20005207B-page 2 2013-2015 Microchip Technology Inc

MCP41HVX1

10 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings dagger

Voltage on V- with respect to DGND DGND + 06V to -400V

Voltage on V+ with respect to DGND DGND - 03V to 400V

Voltage on V+ with respect to V- DGND - 03V to 400V

Voltage on VL with respect to V+ -06V to -400V

Voltage on VL with respect to V- -06V to +400V

Voltage on VL with respect to DGND -06V to +70V

Voltage on CS SCK SDI WLAT and SHDN with respect to DGND -06V to VL + 06V

Voltage on all other pins (PxA PxW and PxB) with respect to V- -03V to V+ + 03V

Input clamp current IIK (VI lt 0 VI gt VL VI gt VPP on HV pins) plusmn20 mA

Output clamp current IOK (VO lt 0 or VO gt VL) plusmn20 mA

Maximum current out of DGND pin 100 mA

Maximum current into VL pin 100 mA

Maximum current out of V- pin 100 mA

Maximum current into V+ pin 100 mA

Maximum current into PXA PXW amp PXB pins (Continuous) RAB = 5 k plusmn25 mARAB = 10 k plusmn125 mARAB = 50 k plusmn65 mARAB = 100 k plusmn65 mA

Maximum current into PXA PXW amp PXB pins (Pulsed) FPULSE gt 10 kHz (Max IContinuous)(Duty Cycle)

FPULSE 10 kHz (Max IContinuous)(Duty Cycle)

Maximum output current sunk by any Output pin 25 mA

Maximum output current sourced by any Output pin 25 mA

Package Power Dissipation (TA = + 50degC TJ = +150degC) TSSOP-14 1000 mWVQFN-20 (5x5) 2800 mW

Soldering temperature of leads (10 seconds) +300degC

ESD protection on all pins Human Body Model (HBM) plusmn4 kVMachine Model (MM) plusmn400VCharged Device Model (CDM) for TSSOP-14 plusmn1 kV

Maximum Junction Temperature (TJ) 150degCStorage temperature -65degC to +150degCAmbient temperature with power applied -40degC to +125degC

dagger Notice Stresses above those listed under ldquoMaximum Ratingsrdquo may cause permanent damage to the device Thisis a stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operational listings of this specification is not implied Exposure to maximum rating conditions for extended periodsmay affect device reliability

2013-2015 Microchip Technology Inc DS20005207B-page 3

MCP41HVX1

ACDC CHARACTERISTICS

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Digital Positive Supply Voltage (VL)

VL 27 mdash 55 V With respect to DGND(4)

18 mdash 55 V DGND = V- + 09V (referenced to V-)(14)

mdash mdash 0 V With respect to V+

Analog Positive Supply Voltage (V+)

V+ VL(16) mdash 360 V With respect to V-(4)

Digital Ground Voltage (DGND)

VDGND V- mdash V+ - VL V With respect to V-(45)

Analog Negative Supply Voltage (V-)

V- -360 + VL mdash 0 V With respect to DGND and VL = 18V

Resistor Network Supply Voltage

VRN mdash mdash 36V V Delta voltage between V+ and V-(4)

VL Start Voltage to ensure Wiper Reset

VDPOR mdash mdash 18 V With respect to DGND V+ gt 60V RAM retention voltage (VRAM) lt VDBOR

V+ Voltage to ensure Wiper Reset

VAPOR mdash mdash 60 V With respect to V- VL = 0V RAM retention voltage (VRAM) lt VBOR

Digital to Analog Level Shifter Operational Voltage

VLS mdash mdash 23 V VL to V- voltage DGND = V-

Power Rail Voltages during Power-Up(1)

VLPOR mdash mdash 55 V Digital Powers (VLDGND) up 1st V+ and V- floating oras V+V- powers up(V+ must be to DGND)(18)

V+POR mdash mdash 36 V Analog Powers (V+V-) up 1st VL and DGND floatingoras VLDGND powers up (DGND must be between V- and V+)(18)

VL Rise Rate to ensure Power-on Reset

VLRR Note 6 Vms With respect to DGND

Note 1 This specification is by design

Note 4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digitallogic DGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

Note 5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for oper-ation equals 18V So 36V - 18V = 342V

Note 6 PORBOR is not rate dependent

Note 16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

Note 18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analogand Digital) should have a common reference to ensure that the driven DGND voltage is not at a higherpotential than the driven V+ voltage

DS20005207B-page 4 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Delay after device exits the reset state (VL gt VBOR)

TBORD mdash 10 20 micros

Supply Current(7) IDDD mdash 45 300 microA Serial Interface Active Write all 0rsquos to Volatile Wiper 0 (address 0h)VL = 55V CS = VIL FSCK = 5 MHz V- = DGND

mdash mdash 7 microA Serial Interface Inactive VL = 55V SCK = VIH CS = VIH Wiper = 0 V- = DGND

IDDA mdash mdash 5 microA Current V+ to V- PxA = PxB = PxW DGND = V- +(V+2)

Resistance(plusmn 20)(8)

RAB 40 5 60 k -502 devices V+V- = 10V to 36V

80 10 120 k -103 devices V+V- = 10V to 36V

400 50 600 k -503 devices V+V- = 10V to 36V

800 100 1200 k -104 devices V+V- = 10V to 36V

RAB Current IAB mdash mdash 900 mA -502 devices 36V RAB(MIN) V- = -18V V+ = +18V(9)

mdash mdash 450 mA -103 devices

mdash mdash 090 mA -503 devices

mdash mdash 045 mA -104 devices

Resolution N 256 Taps 8-bit No Missing Codes

128 Taps 7-bit No Missing Codes

Step Resistance(see Appendix B4)

RS mdash RAB(255) mdash 8-bit Note 1

mdash RAB(127) mdash 7-bit Note 1

Note 1 This specification is by design

Note 7 Supply current (IDDD and IDDA) is independent of current through the resistor network

Note 8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

Note 9 Guaranteed by the RAB specification and Ohms Law

2013-2015 Microchip Technology Inc DS20005207B-page 5

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 3: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

10 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings dagger

Voltage on V- with respect to DGND DGND + 06V to -400V

Voltage on V+ with respect to DGND DGND - 03V to 400V

Voltage on V+ with respect to V- DGND - 03V to 400V

Voltage on VL with respect to V+ -06V to -400V

Voltage on VL with respect to V- -06V to +400V

Voltage on VL with respect to DGND -06V to +70V

Voltage on CS SCK SDI WLAT and SHDN with respect to DGND -06V to VL + 06V

Voltage on all other pins (PxA PxW and PxB) with respect to V- -03V to V+ + 03V

Input clamp current IIK (VI lt 0 VI gt VL VI gt VPP on HV pins) plusmn20 mA

Output clamp current IOK (VO lt 0 or VO gt VL) plusmn20 mA

Maximum current out of DGND pin 100 mA

Maximum current into VL pin 100 mA

Maximum current out of V- pin 100 mA

Maximum current into V+ pin 100 mA

Maximum current into PXA PXW amp PXB pins (Continuous) RAB = 5 k plusmn25 mARAB = 10 k plusmn125 mARAB = 50 k plusmn65 mARAB = 100 k plusmn65 mA

Maximum current into PXA PXW amp PXB pins (Pulsed) FPULSE gt 10 kHz (Max IContinuous)(Duty Cycle)

FPULSE 10 kHz (Max IContinuous)(Duty Cycle)

Maximum output current sunk by any Output pin 25 mA

Maximum output current sourced by any Output pin 25 mA

Package Power Dissipation (TA = + 50degC TJ = +150degC) TSSOP-14 1000 mWVQFN-20 (5x5) 2800 mW

Soldering temperature of leads (10 seconds) +300degC

ESD protection on all pins Human Body Model (HBM) plusmn4 kVMachine Model (MM) plusmn400VCharged Device Model (CDM) for TSSOP-14 plusmn1 kV

Maximum Junction Temperature (TJ) 150degCStorage temperature -65degC to +150degCAmbient temperature with power applied -40degC to +125degC

dagger Notice Stresses above those listed under ldquoMaximum Ratingsrdquo may cause permanent damage to the device Thisis a stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operational listings of this specification is not implied Exposure to maximum rating conditions for extended periodsmay affect device reliability

2013-2015 Microchip Technology Inc DS20005207B-page 3

MCP41HVX1

ACDC CHARACTERISTICS

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Digital Positive Supply Voltage (VL)

VL 27 mdash 55 V With respect to DGND(4)

18 mdash 55 V DGND = V- + 09V (referenced to V-)(14)

mdash mdash 0 V With respect to V+

Analog Positive Supply Voltage (V+)

V+ VL(16) mdash 360 V With respect to V-(4)

Digital Ground Voltage (DGND)

VDGND V- mdash V+ - VL V With respect to V-(45)

Analog Negative Supply Voltage (V-)

V- -360 + VL mdash 0 V With respect to DGND and VL = 18V

Resistor Network Supply Voltage

VRN mdash mdash 36V V Delta voltage between V+ and V-(4)

VL Start Voltage to ensure Wiper Reset

VDPOR mdash mdash 18 V With respect to DGND V+ gt 60V RAM retention voltage (VRAM) lt VDBOR

V+ Voltage to ensure Wiper Reset

VAPOR mdash mdash 60 V With respect to V- VL = 0V RAM retention voltage (VRAM) lt VBOR

Digital to Analog Level Shifter Operational Voltage

VLS mdash mdash 23 V VL to V- voltage DGND = V-

Power Rail Voltages during Power-Up(1)

VLPOR mdash mdash 55 V Digital Powers (VLDGND) up 1st V+ and V- floating oras V+V- powers up(V+ must be to DGND)(18)

V+POR mdash mdash 36 V Analog Powers (V+V-) up 1st VL and DGND floatingoras VLDGND powers up (DGND must be between V- and V+)(18)

VL Rise Rate to ensure Power-on Reset

VLRR Note 6 Vms With respect to DGND

Note 1 This specification is by design

Note 4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digitallogic DGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

Note 5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for oper-ation equals 18V So 36V - 18V = 342V

Note 6 PORBOR is not rate dependent

Note 16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

Note 18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analogand Digital) should have a common reference to ensure that the driven DGND voltage is not at a higherpotential than the driven V+ voltage

DS20005207B-page 4 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Delay after device exits the reset state (VL gt VBOR)

TBORD mdash 10 20 micros

Supply Current(7) IDDD mdash 45 300 microA Serial Interface Active Write all 0rsquos to Volatile Wiper 0 (address 0h)VL = 55V CS = VIL FSCK = 5 MHz V- = DGND

mdash mdash 7 microA Serial Interface Inactive VL = 55V SCK = VIH CS = VIH Wiper = 0 V- = DGND

IDDA mdash mdash 5 microA Current V+ to V- PxA = PxB = PxW DGND = V- +(V+2)

Resistance(plusmn 20)(8)

RAB 40 5 60 k -502 devices V+V- = 10V to 36V

80 10 120 k -103 devices V+V- = 10V to 36V

400 50 600 k -503 devices V+V- = 10V to 36V

800 100 1200 k -104 devices V+V- = 10V to 36V

RAB Current IAB mdash mdash 900 mA -502 devices 36V RAB(MIN) V- = -18V V+ = +18V(9)

mdash mdash 450 mA -103 devices

mdash mdash 090 mA -503 devices

mdash mdash 045 mA -104 devices

Resolution N 256 Taps 8-bit No Missing Codes

128 Taps 7-bit No Missing Codes

Step Resistance(see Appendix B4)

RS mdash RAB(255) mdash 8-bit Note 1

mdash RAB(127) mdash 7-bit Note 1

Note 1 This specification is by design

Note 7 Supply current (IDDD and IDDA) is independent of current through the resistor network

Note 8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

Note 9 Guaranteed by the RAB specification and Ohms Law

2013-2015 Microchip Technology Inc DS20005207B-page 5

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

AMERICASCorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200 Fax 480-792-7277Technical Support httpwwwmicrochipcomsupportWeb Address wwwmicrochipcom

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 4: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Digital Positive Supply Voltage (VL)

VL 27 mdash 55 V With respect to DGND(4)

18 mdash 55 V DGND = V- + 09V (referenced to V-)(14)

mdash mdash 0 V With respect to V+

Analog Positive Supply Voltage (V+)

V+ VL(16) mdash 360 V With respect to V-(4)

Digital Ground Voltage (DGND)

VDGND V- mdash V+ - VL V With respect to V-(45)

Analog Negative Supply Voltage (V-)

V- -360 + VL mdash 0 V With respect to DGND and VL = 18V

Resistor Network Supply Voltage

VRN mdash mdash 36V V Delta voltage between V+ and V-(4)

VL Start Voltage to ensure Wiper Reset

VDPOR mdash mdash 18 V With respect to DGND V+ gt 60V RAM retention voltage (VRAM) lt VDBOR

V+ Voltage to ensure Wiper Reset

VAPOR mdash mdash 60 V With respect to V- VL = 0V RAM retention voltage (VRAM) lt VBOR

Digital to Analog Level Shifter Operational Voltage

VLS mdash mdash 23 V VL to V- voltage DGND = V-

Power Rail Voltages during Power-Up(1)

VLPOR mdash mdash 55 V Digital Powers (VLDGND) up 1st V+ and V- floating oras V+V- powers up(V+ must be to DGND)(18)

V+POR mdash mdash 36 V Analog Powers (V+V-) up 1st VL and DGND floatingoras VLDGND powers up (DGND must be between V- and V+)(18)

VL Rise Rate to ensure Power-on Reset

VLRR Note 6 Vms With respect to DGND

Note 1 This specification is by design

Note 4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digitallogic DGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

Note 5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for oper-ation equals 18V So 36V - 18V = 342V

Note 6 PORBOR is not rate dependent

Note 16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

Note 18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analogand Digital) should have a common reference to ensure that the driven DGND voltage is not at a higherpotential than the driven V+ voltage

DS20005207B-page 4 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Delay after device exits the reset state (VL gt VBOR)

TBORD mdash 10 20 micros

Supply Current(7) IDDD mdash 45 300 microA Serial Interface Active Write all 0rsquos to Volatile Wiper 0 (address 0h)VL = 55V CS = VIL FSCK = 5 MHz V- = DGND

mdash mdash 7 microA Serial Interface Inactive VL = 55V SCK = VIH CS = VIH Wiper = 0 V- = DGND

IDDA mdash mdash 5 microA Current V+ to V- PxA = PxB = PxW DGND = V- +(V+2)

Resistance(plusmn 20)(8)

RAB 40 5 60 k -502 devices V+V- = 10V to 36V

80 10 120 k -103 devices V+V- = 10V to 36V

400 50 600 k -503 devices V+V- = 10V to 36V

800 100 1200 k -104 devices V+V- = 10V to 36V

RAB Current IAB mdash mdash 900 mA -502 devices 36V RAB(MIN) V- = -18V V+ = +18V(9)

mdash mdash 450 mA -103 devices

mdash mdash 090 mA -503 devices

mdash mdash 045 mA -104 devices

Resolution N 256 Taps 8-bit No Missing Codes

128 Taps 7-bit No Missing Codes

Step Resistance(see Appendix B4)

RS mdash RAB(255) mdash 8-bit Note 1

mdash RAB(127) mdash 7-bit Note 1

Note 1 This specification is by design

Note 7 Supply current (IDDD and IDDA) is independent of current through the resistor network

Note 8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

Note 9 Guaranteed by the RAB specification and Ohms Law

2013-2015 Microchip Technology Inc DS20005207B-page 5

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 5: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Delay after device exits the reset state (VL gt VBOR)

TBORD mdash 10 20 micros

Supply Current(7) IDDD mdash 45 300 microA Serial Interface Active Write all 0rsquos to Volatile Wiper 0 (address 0h)VL = 55V CS = VIL FSCK = 5 MHz V- = DGND

mdash mdash 7 microA Serial Interface Inactive VL = 55V SCK = VIH CS = VIH Wiper = 0 V- = DGND

IDDA mdash mdash 5 microA Current V+ to V- PxA = PxB = PxW DGND = V- +(V+2)

Resistance(plusmn 20)(8)

RAB 40 5 60 k -502 devices V+V- = 10V to 36V

80 10 120 k -103 devices V+V- = 10V to 36V

400 50 600 k -503 devices V+V- = 10V to 36V

800 100 1200 k -104 devices V+V- = 10V to 36V

RAB Current IAB mdash mdash 900 mA -502 devices 36V RAB(MIN) V- = -18V V+ = +18V(9)

mdash mdash 450 mA -103 devices

mdash mdash 090 mA -503 devices

mdash mdash 045 mA -104 devices

Resolution N 256 Taps 8-bit No Missing Codes

128 Taps 7-bit No Missing Codes

Step Resistance(see Appendix B4)

RS mdash RAB(255) mdash 8-bit Note 1

mdash RAB(127) mdash 7-bit Note 1

Note 1 This specification is by design

Note 7 Supply current (IDDD and IDDA) is independent of current through the resistor network

Note 8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

Note 9 Guaranteed by the RAB specification and Ohms Law

2013-2015 Microchip Technology Inc DS20005207B-page 5

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 6: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Wiper Resistance (see Appendix B5)

RW mdash 75 170 IW = 1 mA V+ = +18V V- = -18V code = 00h PxA = floating PxB = V-

mdash 145 200 IW = 1 mA V+ = +50V V- = -50V code = 00h PxA = floating PxB = V-(2)

Nominal Resistance Temperature Coefficient (see Appendix B23)

RABT mdash 50 mdash ppmdegC TA = -40degC to +85degC

mdash 100 mdash ppmdegC TA = -40degC to +125degC

Ratiometeric Tempco (see Appendix B22)

VWBT mdash 15 mdash ppmdegC Code = Mid-scale (80h or 40h)

Resistor Terminal Input Voltage Range (Terminals A B and W)

VAVWVB V- mdash V+ V Note 1 Note 11

Current through Terminals (A B and Wiper)(1)

IT IW mdash mdash 25 mA -502 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 125 mA -103 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -503 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 65 mA -104 devices IBW(W ne ZS) and IAW(W ne FS)

mdash mdash 36 mA IBW(W = ZS) or IAW(W = FS)

Leakage current into A W or B

ITL mdash 5 mdash nA A = W = B = V-

Note 1 This specification is by design

Note 2 This parameter is not tested but specified by characterization

Note 11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

DS20005207B-page 6 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 7: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Full-Scale Error VWFSE -105 mdash mdash LSb 5 k

8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = FFh 7-bit code = 7Fh)(1017) (VA = V+ VB = V-)(see Appendix B10)

-85 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-135 mdash mdash LSb VAB = 10V to 36V

-55 mdash mdash LSb

7-bit

VAB = 20V to 36V

-45 mdash mdash LSb VAB = 20V to 36V -40degC TA +85degC(2)

-70 mdash mdash LSb VAB = 10V to 36V

-45 mdash mdash LSb 10 k 8-bit

VAB = 20V to 36V

-60 mdash mdash LSb VAB = 10V to 36V

-265 mdash mdash LSb

7-bit

VAB = 20V to 36V

-225 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-35 mdash mdash LSb VAB = 10V to 36V

-10 mdash mdash LSb 50 k

8-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 20V to 36V-40degC TA +85degC(2)

-14 mdash mdash LSb VAB = 10V to 36V

-125 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-095 mdash mdash LSb

7-bit

VAB = 20V to 36V

-12 mdash mdash LSb VAB = 10V to 36V

-11 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-07 mdash mdash LSb 100 k

8-bit

VAB = 20V to 36V

-095 mdash mdash LSb VAB = 10V to 36V

-07 mdash mdash LSb VAB = 10V to 36V-40degC TA +85degC(2)

-085 mdash mdash LSb7-bit

VAB = 20V to 36V

-09 mdash mdash LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 7

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 8: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Zero-Scale Error VWZSE mdash mdash +85 LSb 5 k 8-bit

VAB = 20V to 36V

(Potentiometer) (8-bit code = 00h 7-bit code = 00h)(1017)

(VA = V+ VB = V- )(see Appendix B11)

mdash mdash +135 LSb VAB = 10V to 36V

mdash mdash +45 LSb7-bit

VAB = 20V to 36V

mdash mdash +70 LSb VAB = 10V to 36V

mdash mdash +40 LSb 10 k

8-bit

VAB = 20V to 36V

mdash mdash +65 LSb VAB = 10V to 36V

mdash mdash +60 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +20 LSb

7-bit

VAB = 20V to 36V

mdash mdash +325 LSb VAB = 10V to 36V

mdash mdash +30 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +09 LSb 50 k

8-bit

VAB = 20V to 36V

mdash mdash +08 LSb VAB = 20V to 36V -40degC TA +85degC(2)

mdash mdash +13 LSb VAB = 10V to 36V

mdash mdash +12 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +05 LSb7-bit

VAB = 20V to 36V

mdash mdash +07 LSb VAB = 10V to 36V

mdash mdash +05 LSb 100 k

8-bit

VAB = 20V to 36V

mdash mdash +095 LSb VAB = 10V to 36V

mdash mdash +07 LSb VAB = 10V to 36V -40degC TA +85degC(2)

mdash mdash +025 LSb7-bit

VAB = 20V to 36V

mdash mdash +04 LSb VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 8 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

AMERICASCorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200 Fax 480-792-7277Technical Support httpwwwmicrochipcomsupportWeb Address wwwmicrochipcom

AtlantaDuluth GA Tel 678-957-9614 Fax 678-957-1455

Austin TXTel 512-257-3370

BostonWestborough MA Tel 774-760-0087 Fax 774-760-0088

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ASIAPACIFICAsia Pacific OfficeSuites 3707-14 37th FloorTower 6 The GatewayHarbour City KowloonHong KongTel 852-2943-5100Fax 852-2401-3431

Australia - SydneyTel 61-2-9868-6733Fax 61-2-9868-6755

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China - ChengduTel 86-28-8665-5511Fax 86-28-8665-7889

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China - Dongguan

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012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 9: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Potentiometer Integral Nonlinearity(10 17) (see Appendix B12)

P-INL -1 plusmn05 +1 LSb 5 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb 10 k 8-bit VAB = 10V to 36V

-05 plusmn025 +05 LSb 7-bit VAB = 10V to 36V

-11 plusmn05 +11 LSb 50 k 8-bit VAB = 10V to 36V

-1 plusmn05 +1 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-06 plusmn025 +06 LSb 7-bit VAB = 10V to 36V

-185 plusmn05 +185 LSb 100 k 8-bit VAB = 10V to 36V

-12 plusmn05 +12 LSb VAB = 20V to 36V(2)

-1 plusmn05 +1 LSb VAB = 10V to 36V -40degC TA +85degC(2)

-1 plusmn05 +1 LSb 7-bit VAB = 10V to 36V

Potentiometer Differential Nonlinearity(10 17)

(see Appendix B13)

P-DNL -05 plusmn025 +05 LSb 5 k 8-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 7-bit VAB = 10V to 36V

-0375 plusmn0125 +0375 LSb 10 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 50 k 8-bit VAB = 10V to 36V

-0125 plusmn01 +0125 LSb 7-bit VAB = 10V to 36V

-025 plusmn0125 +025 LSb 100 k 8-bit VAB = 10V to 36V

-0125 -015 +0125 LSb 7-bit VAB = 10V to 36V

Note 2 This parameter is not tested but specified by characterization

Note 10 Measured at VW with VA = V+ and VB = V-Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 9

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 10: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Bandwidth -3 dB (load = 30 pF) (see Appendix B24)

BW mdash 480 mdash kHz 5 k 8-bit Code = 7Fh

mdash 480 mdash kHz 7-bit Code = 3Fh

mdash 240 mdash kHz 10 k 8-bit Code = 7Fh

mdash 240 mdash kHz 7-bit Code = 3Fh

mdash 48 mdash kHz 50 k 8-bit Code = 7Fh

mdash 48 mdash kHz 7-bit Code = 3Fh

mdash 24 mdash kHz 100 k 8-bit Code = 7Fh

mdash 24 mdash kHz 7-bit Code = 3Fh

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 1 mdash micros 10 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 25 mdash micros 50 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

mdash 5 mdash micros 100 k Code = 00h rarr FFh (7Fh) FFh (7Fh) rarr 00h

DS20005207B-page 10 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

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012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 11: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Integral Nonlinear-ity(12131417) (see Appendix B5)

R-INL -175 mdash +175 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-25 mdash +25 LSb IW = 33 mA (V+ - V-) = 20V(2)

-40 mdash +40 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-15 mdash +15 LSb IW = 33 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 17 mA (V+ - V-) = 10V

-10 mdash +10 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-175 mdash +175 LSb IW = 17 mA (V+ - V-) = 20V(2)

-20 mdash +20 LSb IW = 830 microA (V+ - V-) = 10V

-06 mdash +06 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 20V(2)

-10 mdash +10 LSb IW = 830 microA (V+ - V-) = 10V

-10 mdash +10 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 330 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 170 microA (V+ - V-) = 10V

-10 mdash +10 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-10 mdash +10 LSb IW = 170 microA (V+ - V-) = 20V(2)

-12 mdash +12 LSb IW = 83 microA (V+ - V-) = 10V

-05 mdash +05 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-06 mdash +06 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

2013-2015 Microchip Technology Inc DS20005207B-page 11

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Rheostat Differential Nonlinearity(12131417) (see Appendix B5)

R-DNL -05 mdash +05 LSb 5 k 8-bit IW = 60 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 33 mA (V+ - V-) = 20V(2)

-08 mdash +08 LSb IW = 17 mA (V+ - V-) = 10V

-06 mdash +06 LSb IW = 17 mA (V+ - V-) = 10V -40degC TA +85degC(2)

-025 mdash +025 LSb 7-bit IW = 60 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 33 mA (V+ - V-) = 20V(2)

-03 mdash +03 LSb IW = 17 mA (V+ - V-) = 10V

-05 mdash +05 LSb 10 k 8-bit IW = 30 mA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 17 mA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 830 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 30 mA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 17 mA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 830 microA (V+ - V-) = 10V

-05 mdash +05 LSb 50 k 8-bit IW = 600 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 330 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 600 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 330 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 10V

-05 mdash +05 LSb 100 k 8-bit IW = 300 microA (V+ - V-) = 36V(2)

-05 mdash +05 LSb IW = 170 microA (V+ - V-) = 20V(2)

-05 mdash +05 LSb IW = 83 microA (V+ - V-) = 10V

-025 mdash +025 LSb 7-bit IW = 300 microA (V+ - V-) = 36V(2)

-025 mdash +025 LSb IW = 170 microA (V+ - V-) = 20V(2)

-025 mdash +025 LSb IW = 83 microA (V+ - V-) = 10V

Note 2 This parameter is not tested but specified by characterization

Note 12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

Note 13 Externally connected to a Rheostat configuration (RBW) and then tested

Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+and V- (voltages are 36V 20V and 10V)

Note 17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

DS20005207B-page 12 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless notedV+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Capacitance (PA) CA mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (Pw) CW mdash 120 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Capacitance (PB) CB mdash 75 mdash pF Measured to V- f =1 MHz Wiper code = Mid-Scale

Common-Mode Leakage

ICM mdash 5 mdash nA VA = VB = VW

Digital Interface Pin Capacitance

CIN COUT

mdash 10 mdash pF fC = 400 kHz

Digital InputsOutputs (CS SDI SDO SCK SHDN WLAT)

Schmitt Trigger High-Input Threshold

VIH 045 VL mdash VL + 03V V 27V VL 55V

05 VL mdash VL + 03V V 18V VL 27V

Schmitt Trigger Low-Input Threshold

VIL DGND - 05V mdash 02 VL V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VL mdash V

Output Low Voltage (SDO)

VOL DGND mdash 02 VL V VL = 55V IOL = 5 mA

DGND mdash 02 VL V VL = 18V IOL = 800 microA

Output High Voltage (SDO)

VOH 08 VL mdash VL V VL = 55V IOH = -25 mA

08 VL mdash VL V VL = 18V IOL = -800 microA

Input Leakage Current

IIL -1 1 uA VIN = VL and VIN = DGND

2013-2015 Microchip Technology Inc DS20005207B-page 13

MCP41HVX1

ACDC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

RAM (Wiper TCON) Value

Wiper Value Range N 0h mdash FFh hex 8-bit

0h mdash 7Fh hex 7-bit

Wiper PORBOR Value NPORBOR 7Fh hex 8-bit

3Fh hex 7-bit

TCON Value Range N 0h mdash FFh hex

TCON PORBOR Value NTCON FF hex All Terminals connected

Power Requirements

Power Supply Sensitivity (see Appendix B20)

PSS mdash 00015 00035 8-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 7Fh

mdash 00015 00035 7-bit VL = 27V to 55V V+ = 18V V- = -18V Code = 3Fh

Power Dissipation PDISS mdash 260 mdash mW 5 k VL = 55V V+ = 18V V- = -18V(15)

mdash 130 mdash mW 10 k

mdash 26 mdash mW 50 k

mdash 13 mdash mW 100 k

Note 15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

DS20005207B-page 14 2013-2015 Microchip Technology Inc

MCP41HVX1

ACDC Notes

1 This specification is by design

2 This parameter is not tested but specified by characterization

3 See Absolute Maximum Ratings

4 V+ voltage is dependent on V- voltage The maximum delta voltage between V+ and V- is 36V The digital logicDGND potential can be anywhere between V+ and V- The VL potential must be ge DGND and le V+

5 The minimum value determined by maximum V- to V+ potential equals 36V and the minimum value for operationequals 18V So 36V - 18V = 342V

6 PORBOR is not rate dependent

7 Supply current (IDDD and IDDA) is independent of current through the resistor network

8 Resistance (RAB) is defined as the resistance between Terminal A to Terminal B

9 Guaranteed by the RAB specification and Ohms Law

10 Measured at VW with VA = V+ and VB = V-

11 Resistor terminals A W and Brsquos polarity with respect to each other is not restricted

12 Nonlinearity is affected by wiper resistance (RW) which changes significantly over voltage and temperature

13 Externally connected to a Rheostat configuration (RBW) and then tested

14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition the delta voltage between V+ and V-(voltages are 36V 20V and 10V)

15 PDISS = I V or ((IDDD 55V) + (IDDA 36V) + (IAB 36V))

16 For specified analog performance V+ must be 20V or greater (unless otherwise noted)

17 Analog switch leakage affects this specification Higher temperatures increase the switch leakage

18 During the power-up sequence to ensure expected Analog POR operation the two power systems (Analog andDigital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential thanthe driven V+ voltage

2013-2015 Microchip Technology Inc DS20005207B-page 15

MCP41HVX1

11 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1 Settling Time Waveforms

W

plusmn 1 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC le TA le +125degC (extended)

All parameters apply across the specified operating ranges unless noted V+ = 10V to 36V (referenced to V-) V+ = +5V to +18V amp V- = -50V to -18V (referenced to DGND ge plusmn5V to plusmn18V) VL = +27V to 55V 5 k 10 k 50 k 100 k devices Typical specifications represent values for VL = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

VW Settling Time (VA = 10V VB = 0V plusmn1LSb error band CL = 50 pF) (see Appendix B17)

tS mdash 1 mdash micros 5 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 1 mdash micros 10 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 25 mdash micros 50 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

mdash 5 mdash micros 100 k Code = 00h ge FFh (7Fh) FFh (7Fh) ge 00h

DS20005207B-page 16 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 1-2 SPI Timing Waveform (Mode = 11)

CS

SCK

SDO

SDI

70a

72

71

7374

77

80

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

84

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquoldquo1rdquo

83b70b

85

83a

TABLE 1-2 SPI REQUIREMENTS (MODE = 11)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (set-up time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

83a CS Inactive (VIH) after SCK edge TscH2csI 100 mdash ns

83b WLAT Inactive (VIH) after eighth (or sixteenth) SCK edge (hold time)

TscH2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

2013-2015 Microchip Technology Inc DS20005207B-page 17

MCP41HVX1

FIGURE 1-3 SPI Timing Waveform (Mode = 00)

CS

SCK

SDO

SDI

70a

71 72

82

74

75 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83a

84

73

WLAT ldquo0rdquoldquo0rdquo

ldquo1rdquo ldquo1rdquo

70b

83b

TABLE 1-3 SPI REQUIREMENTS (MODE = 00)

Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK mdash 10 MHz VL = 27V to 55V

mdash 1 MHz VL = 18V to 27V

70a CS Active (VIL) to SCK input TcsA2scH 25 mdash ns

70b WLAT Active (VIL) to eighth (or sixteenth) SCK of the Serial Command to ensure previous data is latched (setup time)

TwlA2scH 20 mdash ns

71 SCK input high time TscH 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

72 SCK input low time TscL 35 mdash ns VL = 27V to 55V

120 mdash ns VL = 18V to 27V

73 Set-up time of SDI input to SCK edge TDIV2scH 10 mdash ns

74 Hold time of SDI input from SCK edge TscH2DIL 20 mdash ns

77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ mdash 50 ns Note 1

80 SDO data output valid after SCK edge TscL2DOV mdash 55 ns VL = 27V to 55V

90 ns VL = 18V to 27V

82 SDO data output valid after CS Active (VIL) TscL2DOV mdash 70 ns

83a CS Inactive (VIH) after SCK edge TscL2csI 100 mdash ns

83b WLAT Inactive (VIH) after SCK edge TscL2wlatI 50 mdash ns

84 Hold time of CS (or WLAT) Inactive (VIH) to CS (or WLAT) Active (VIL)

TcsA2csI 20 mdash ns

85 WLAT input low time TWLATL 25 mdash ns

Note 1 This specification is by design

DS20005207B-page 18 2013-2015 Microchip Technology Inc

MCP41HVX1

TEMPERATURE CHARACTERISTICSElectrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 14L-TSSOP (ST) JA mdash 100 mdash degCW

Thermal Resistance 20L-VQFN (MQ) JA mdash 383 mdash degCW

2013-2015 Microchip Technology Inc DS20005207B-page 19

MCP41HVX1

20 TYPICAL PERFORMANCE CURVES

Note The device Performance Curves are available in a separate document This is done to keep the file size ofthis PDF document less than the 10 MB file attachment limit of many mail servers The MCP41HVX1 Performance Curves document is literature number DS20005209 and can be found onthe Microchip website Look at the MCP41HVX1 Product Page under Documentation and Software in theData Sheets category

DS20005207B-page 20 2013-2015 Microchip Technology Inc

MCP41HVX1

30 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1Additional descriptions of the device pins follows

TABLE 3-1 PINOUT DESCRIPTION FOR THE MCP41HVX1

Pin

FunctionTSSOP VQFNSymbol Type

BufferType14L 20L

1 1 VL P mdash Positive Digital Power Supply Input

2 2 SCK I ST SPI Serial Clock pin

3 3 CS I ST Chip Select

4 4 SDI I ST SPI Serial Data In pin

5 5 SDO O mdash SPI Serial Data Out

6 6 WLAT I ST Wiper Latch Enable0 = Received SPI Shift Register Buffer (SPIBUF) value is

transferred to Wiper register1 = Received SPI data value is held in SPI Shift Register

Buffer (SPIBUF)

7 7 SHDN I ST Shutdown

8 11 DGND P mdash Ground

9 8 9 10 17 18 19 20

NC mdash mdash Pin not internally connected to die To reduce noise coupling connect pin either to DGND or VL

10 12 V- P mdash Analog Negative Potential Supply

11 13 P0B IO A Potentiometer 0 Terminal B

12 14 P0W IO A Potentiometer 0 Wiper Terminal

13 15 P0A IO A Potentiometer 0 Terminal A

14 16 V+ P mdash Analog Positive Potential Supply

mdash 21 EP P mdash Exposed Pad connect to V- signal or Not Connected (floating)(1)

Legend A = Analog ST = Schmitt Trigger I = Input O = Output IO = InputOutput P = Power

Note 1 The VQFN package has a contact on the bottom of the package This contact is conductively connected to the die substrate and therefore should be unconnected or connected to the same ground as the devicersquos V- pin

2013-2015 Microchip Technology Inc DS20005207B-page 21

MCP41HVX1

31 Positive Power Supply Input (VL)

The VL pin is the devicersquos positive power supply inputThe input power supply is relative to DGND and canrange from 18V to 55V A decoupling capacitor on VL(to DGND) is recommended to achieve maximumperformance

While the devicersquos VL lt Vmin (27V) the electricalperformance of the device may not meet the data sheetspecifications

32 Serial Clock (SCK)

The SCK pin is the serial interfaces Serial Clock pinThis pin is connected to the host controllersrsquo SCK pinThe MCP41HVX1 is an SPI slave device so its SCKpin is an input-only pin

33 Chip Select (CS)

The CS pin is the serial interfacersquos chip select inputForcing the CS pin to VIL enables the serial commands

34 Serial Data In (SDI)

The SDI pin is the serial interfacersquos Serial Data In pinThis pin is connected to the host controllerrsquos SDO pin

35 Serial Data Out (SDO)

The SDO pin is the serial interfacersquos Serial Data Outpin This pin is connected to the host controllerrsquos SDIpin This pin allows the host controller to read the digitalpotentiometer registers (Wiper and TCON) or monitorthe state of the command error bit

36 Wiper Latch (WLAT)

The WLAT pin is used to delay the transfer of thereceived wiper value (in the shift register) to the wiperregister This allows this transfer to be synchronized toan external event (such as zero crossing) SeeSection 432 ldquoWiper Latchrdquo

37 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state SeeSection 431 ldquoShutdownrdquo

38 Digital Ground (DGND)

The DGND pin is the devicersquos digital ground reference

39 Not Connected (NC)

This pin is not internally connected to the die To reducenoise coupling these pins should be connected toeither VL or DGND

310 Analog Negative Voltage (V-)

Analog circuitry negative supply voltage Must nothave a higher potential then the DGND pin

311 Potentiometer Terminal B

The Terminal B pin is connected to the internalpotentiometerrsquos terminal B

The potentiometerrsquos terminal B is the fixed connectionto the zero-scale wiper value of the digitalpotentiometer This corresponds to a wiper value of0x00 for both 7-bit and 8-bit devices

The Terminal B pin does not have a polarity relative tothe Terminal W or A pins The Terminal B pin cansupport both positive and negative current The voltageon Terminal B must be between V+ and V-

312 Potentiometer Wiper (W) Terminal

The Terminal W pin is connected to the internalpotentiometerrsquos Terminal W (the Wiper) The wiperterminal is the adjustable terminal of the digitalpotentiometer The Terminal W pin does not have apolarity relative to terminalrsquos A or B pins The TerminalW pin can support both positive and negative currentThe voltage on Terminal W must be between V+ and V-

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the Analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the Digital POR voltage the wiper isforced to the value in the wiper register once theAnalog POR voltage is crossed

313 Potentiometer Terminal A

The Terminal A pin is connected to the internalpotentiometerrsquos Terminal A

The potentiometerrsquos Terminal A is the fixed connectionto the full-scale wiper value of the digital potentiometerThis corresponds to a wiper value of 0xFF for 8-bitdevices or 0x7F for 7-bit devices

The Terminal A pin does not have a polarity relative tothe Terminal W or B pins The Terminal A pin cansupport both positive and negative current The voltageon Terminal A must be between V+ and V-

314 Analog Positive Voltage (V+)

The analog circuitryrsquos positive supply voltage The V+pin must have a higher potential then the V- pin

315 Exposed Pad (EP)

This pad is only on the bottom of the VQFN packagesThis pad is conductively connected to the devicesubstrate The EP pin must be connected to the V-signal or left floating This pad could be connected to aPrinted Circuit Board (PCB) heat sink to assist as aheat sink for the device

DS20005207B-page 22 2013-2015 Microchip Technology Inc

MCP41HVX1

40 FUNCTIONAL OVERVIEW

This data sheet covers a family of two volatile digitalpotentiometer devices that will be referred to asMCP41HVX1

As the Device Block Diagram shows there are sixmain functional blocks These are

bull Operating Voltage Range

bull PORBOR Operation

bull Memory Map

bull Control Module

bull Resistor Network

bull Serial Interface (SPI)

The PORBOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections TheDevice Commands are discussed in Section 70ldquoDevice Commandsrdquo

41 Operating Voltage Range

The MCP41HVX1 devices have four voltage signalsThese are

bull V+ - Analog power bull VL - Digital power bull DGND - Digital ground bull V- - Analog ground

Figure 4-1 shows the two possible power-upsequences analog power rails power-up first or digitalpower rails power-up first The device has beendesigned so that either power rail may power-up firstThe device has a POR circuit for both digital powercircuitry and analog power circuitry

If the V+ voltage powers-up before the VL voltage thewiper is forced to mid-scale once the analog PORvoltage is crossed

If the V+ voltage powers-up after the VL voltage isgreater than the digital POR voltage the wiper is forcedto the value in the wiper register once the analog PORvoltage is crossed

Figure 4-2 shows the three cases of the digital powersignals (VLDGND) with respect to the analog powersignals (V+V-) The device implements level shiftsbetween the digital and analog power systems whichallows the digital interface voltage to be anywhere inthe V+V- voltage window

FIGURE 4-1 Power-On Sequences

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

V-

V+

DGND

VL

V-

V+

DGND

VL

Referenced to V-

Referenced to DGND

Analog Voltage Powers-Up First Digital Voltage Powers-Up First

2013-2015 Microchip Technology Inc DS20005207B-page 23

MCP41HVX1

FIGURE 4-2 Voltage RangesV- and DGND

V+

VL

Case 1

V-

V+

DGND

Case 2

V-

V+ and VL

DGND

Case 3

VL AnywherebetweenV+ and V-

High- Voltage Range

High- Voltage Range

High- Voltage Range(VL DGND)

DS20005207B-page 24 2013-2015 Microchip Technology Inc

MCP41HVX1

42 PORBOR Operation

The resistor networkrsquos devices are powered by the analogpower signals (V+V-) but the digital logic (including thewiper registers) is powered by the digital power signals(VLDGND) So both the digital circuitry and analogcircuitry have independent PORBOR circuits

The wiper position will be forced to the default statewhen the V+ voltage (relative to V-) is above the analogPORBOR trip point The wiper register will be in thedefault state when the VL voltage (relative to DGND) isabove the digital PORBOR trip point

The digital-signal-to-analog-signal voltage level shiftersrequire a minimum voltage between the VL and V-signals This voltage requirement is below theoperating supply voltage specifications The wiperoutput may fluctuate while the VL voltage is less thanthe level shifter operating voltage since the analogvalues may not reflect the digital value Output issuesmay be reduced by powering-up the digital supplyvoltages to their operating voltage before powering theanalog supply voltage

421 POWER-ON RESET

Each power system has its own independent Power-onReset circuitry This is done so that regardless of thepower-up sequencing of the analog and digital powerrails the wiper output will be forced to a default valueafter minimum conditions are met for either power supply

Table 4-1 shows the interaction between the analogand digital PORs for the V+ and VL voltages on thewiper pin state

4211 Digital Circuitry

A Digital Power-on Reset (DPOR) occurs when thedevicersquos VL signal has power applied (referenced fromDGND) and the voltage rises above the trip point ABrown-out Reset (BOR) occurs when a device has powerapplied to it and the voltage drops below the trip point

The devicersquos RAM retention voltage (VRAM) is lowerthan the PORBOR voltage trip point (VPORVBOR) Themaximum VPORVBOR voltage is less then 18V

When the device powers-up the device VL will crossthe VPORVBOR voltage Once the VL voltage crossesthe VPORVBOR voltage the following happens

bull The volatile wiper registers are loaded with the PORBOR value

bull The TCON registers are loaded with the default values

bull The device is capable of digital operation

Table 4-2 shows the default PORBOR wiper registersetting selection

When VPORVBOR lt VDD lt 27V the electricalperformance may not meet the data sheet specificationsIn this region the device is capable of incrementingdecrementing reading and writing to its volatile memoryif the proper serial command is executed

TABLE 4-1 WIPER PIN STATE BASEDON POR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VAPOR

V+ ge VAPOR

VL lt VDPOR Unknown Mid-Scale

VL ge VDPOR Unknown Wiper

Register Value(1)

Wiper Register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

TABLE 4-2 DEFAULT PORBOR WIPER REGISTER SETTING (DIGITAL)

Typical RAB

Value Pac

kag

eC

od

e

Default POR Wiper

Register Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale8-bit 7Fh

7-bit 3Fh

Note 1 Register setting independent of analog power voltage

2013-2015 Microchip Technology Inc DS20005207B-page 25

MCP41HVX1

4212 Analog Circuitry

An Analog Power-on Reset (APOR) occurs when thedevicersquos V+ pin voltage has power applied (referencedfrom V-) and the V+ pin voltage rises above the trip point

Once the VL pin voltage exceeds the digital POR trip pointvoltage the wiper register will control the wiper setting

Table 4-3 shows the default PORBOR Wiper Settingfor when the VL pin is not powered (lt digital POR trippoint)

FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples

TABLE 4-3 DEFAULT PORBOR WIPER SETTING (ANALOG)

Typical RAB Value

Pac

kag

e

Co

de Default

POR Wiper Setting

Device Resolution

50 k -502 Mid-Scale8-bit

7-bit

100 k -103 Mid-Scale8-bit

7-bit

500 k -503 Mid-Scale8-bit

7-bit

1000 k -104 Mid-Scale8-bit

7-bit

Note 1 Wiper setting is dependent on the wiper register value if the VL voltage is greater than the digital POR voltage

V-

V+

VL

Referenced to DGND

VPORVBOR

DGND

Brown-out conditionWiper value unknown

Digital logic has been reset (POR) Thisincludes the wiper register

Digital logic has been reset (POR) Thisincludes the wiper register

Analog Poweris recovering (still low) and VL

Digital logic has been reset (POR) Thisincludes the wiper registerBrown-out

conditionWiper value unknown

Analog Poweris Low

railpin no longer sources current to V+

Note When VL is above V+ (floating the VL pin ESD clamping diode will cause the V+ level to be pulled up

DS20005207B-page 26 2013-2015 Microchip Technology Inc

MCP41HVX1

422 BROWN-OUT RESET

Each power system has its own independentBrown-out Reset circuitry This is done so that regard-less of the power-down sequencing of the analog anddigital power rails the wiper output will be forced to adefault value after the low-voltage conditions are metfor either power supply

Table 4-4 shows the interaction between the analogand digital BORs for the V+ and VL voltages on thewiper pin state

4221 Digital Circuitry

When the devicersquos digital power supply powers-downthe devicersquos VL pin voltage will cross the digitalVDPORVDBOR voltage

Once the VL voltage decreases below theVDPORVDBOR voltage the following happens

bull Serial Interface is disabled

If the VL voltage decreases below the VRAM voltagethe following happens

bull Volatile wiper registers may become corrupted bull TCON registers may become corrupted

Section 421 ldquoPower-on Resetrdquo describes whatoccurs as the voltage recovers above theVDPORVDBOR voltage

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted

The brown-out circuit establishes a minimum VDBORthreshold for operation (VDBOR lt 18V) The digitalBOR voltage (VDBOR) is higher than the RAM retentionvoltage (VRAM) so that as the device voltage crossesthe digital BOR threshold the value that is loaded intothe volatile wiper register is not corrupted due to RAMretention issues

When VL lt VDBOR all communications are ignoredand the potentiometer terminals are forced to theanalog BOR state

Whenever VL transitions from VL lt VDBOR to VL gtVDBOR (a POR event) the wiperrsquos PORBOR value islatched into the wiper register and the volatile TCONregister is forced to the PORBOR state

When 18V le VL the device is capable of digitaloperation

Table 4-5 shows the digital potentiometerrsquos level offunctionality across the entire VL range while Figure 4-4illustrates the Power-up and Brown-out functionality

4222 Analog Circuitry

An Analog Brown-out Reset (ABOR) occurs when thedevicersquos V+ pin has power applied (referenced from V-)and the V+ pin voltage drops below the trip point In thiscase the resistor network terminal pins can become anunknown state

TABLE 4-4 WIPER PIN STATE BASED ON BOR CONDITIONS

VL Voltage

V+ Voltage

CommentsV+ lt VABOR

V+ ge VABOR

VL lt VDBOR Unknown Mid-Scale

VL ge VDBOR Unknown Wiper

register value (1)

Wiper register can be updated

Note 1 The default POR state of the wiper register value is the mid-scale value

2013-2015 Microchip Technology Inc DS20005207B-page 27

MCP41HVX1

FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage

TABLE 4-5 DEVICE FUNCTIONALITY AT EACH VL REGION

VL Level V+ V- Level Serial

InterfacePotentiometer Terminals(2)

Wiper

CommentRegister Setting

Output(2)

VL lt VDBOR lt 18V Valid Range Ignored ldquounknownrdquo Unknown Invalid

Invalid Range Ignored ldquounknownrdquo Unknown Invalid

VDBOR le VL lt 18V Valid Range ldquoUnknownrdquo connected Volatile wiper Register initialized

Valid The volatile registers are forced to the PORBOR state when VL transitions above the VDPOR trip point

Invalid Range ldquoUnknownrdquo connected Invalid

18V le VL le 55V Valid Range Accepted connected Volatile wiper Register determines Wiper Setting

Valid

Invalid Range Accepted connected Invalid

Note 1 For system voltages below the minimum operating voltage it is recommended to use a voltage supervisor to hold the system in reset This ensures that MCP41HVX1 commands are not attempted out of the oper-ating range of the device

2 Assumes that V+ gt VAPOR

VPORBOR

DGND

VLOutside Specified

Normal Operation Range

Devicersquos Serial

Wiper Forced to Default PORBOR setting

VBOR Delay

Normal Operation Range

18V

Interface is ldquoNot Operationalrdquo

ACDC Range

VRAM

Devicersquos Serial Interface is ldquoNot Specified

DS20005207B-page 28 2013-2015 Microchip Technology Inc

MCP41HVX1

43 Control Module

The control module controls the following functionalities

bull Shutdown

bull Wiper Latch

431 SHUTDOWN

The MCP41HVX1 has two methods to disconnect theterminalrsquos pins (P0A P0W and P0B) from the resistornetwork These are

bull Hardware Shutdown pin (SHDN)bull Terminal Control Register (TCON)

4311 Hardware Shutdown Pin Operation

The SHDN pin has the same functionality asMicrochiprsquos family of standard-voltage devices Whenthe SHDN pin is low the P0A terminal will disconnect(become open) while the P0W terminal simultaneouslyconnects to the P0B terminal (see Figure 4-5)

The Hardware Shutdown pin mode does not corruptthe volatile wiper register When Shutdown is exitedthe device returns to the wiper setting specified by thevolatile wiper value See Section 57 for additionaldescription details

FIGURE 4-5 Hardware Shutdown Resistor Network Configuration

4312 Terminal Control Register

The Terminal Control (TCON) register allows thedevicersquos terminal pins to be independently removedfrom the application circuit These terminal controlsettings do not modify the wiper setting values Thishas no effect on the serial interface and thememorywipers are still under full user control

The resistor network has four TCON bits associatedwith it one bit for each terminal (A W and B) and oneto have a software configuration that matches theconfiguration of the SHDN pin These bits are namedR0A R0W R0B and R0HW Register 4-1 describes theoperation of the R0HW R0A R0B and R0W bits

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of each resistor network (independently)

FIGURE 4-6 R0HW Bit and SHDN Pin Interaction

Note When the SHDN pin is Active (VIL) thestate of the TCON register bits isoverridden (ignored) When the state ofthe SHDN pin returns to the Inactive state(VIH) the TCON register bits return tocontrolling the terminal connection stateThis ensures the value in the TCONregister is not corrupted

Note When the SHDN pin is active the SerialInterface is not disabled and serialinterface activity is executed

A

B

W

Res

isto

r N

etw

ork

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON register R0A R0Wand R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON registerR0A R0W and R0B bits return tocontrolling the terminal connection stateThat is the R0HW bit does not corrupt thestate of the R0A R0W and R0B bits

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

2013-2015 Microchip Technology Inc DS20005207B-page 29

MCP41HVX1

432 WIPER LATCH

The wiper latch pin is used to control when the newwiper value in the wiper register is transferred to thewiper This is useful for applications that need tosynchronize the wiper updates This may be forsynchronization to an external event such as zerocrossing or to synchronize the update of multipledigital potentiometers

When the WLAT pin is high transfers from the wiperregister to the wiper are inhibited When the WLAT pinis low transfers may occur from the Wiper register tothe wiper Figure 4-7 shows the interaction of the WLATpin and the loading of the wiper

If the external event crossing time is long then thewiper could be updated the entire time that the WLATsignal is low Once the WLAT signal goes high thetransfer from the wiper register is disabled The wiperregister can continue to be updated Only the CS pin isused to enabledisable serial commands

If the application does not require synchronized wiperregister updates then the WLAT pin should be tied low

433 DEVICE CURRENT MODES

There are two current modes for Volatile devicesThese are

bull Serial Interface Inactive (Static Operation)

bull Serial Interface Active

For the SPI interface Static Operation occurs whenthe CS pin is at the VIH voltage and the SCK pin isstatic (high or low)

FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)

Note 1 This feature only inhibits the data transferfrom the wiper register to the wiper

2 When the WLAT pin becomes active datatransferred to the wiper will not be cor-rupted due to the wiper register buffer get-ting loaded from an active SPI command

CS

SCK

WiperRegister

VIH

VIL

WLAT

VIH

VIL

Loaded

Wiper Register Transferred

16 SCK 16 SCK 16 SCK 16 SCK

When WLAT goes low during an SPI active transferthe previously loaded Wiper Register value is

When WLAT goes high during an SPI active transferthe wiper register value will be updated with the new value from this serial command when the command completes The wiper will retain the

transferred to the wiper (1)

VIL

to Wiper

value that was last transferred from the wiper register before the WLAT pin went high

Note 1 The wiper register may be updated on 16 SCK cycles for a Write command or on 8 SCK cycles withand Increment or Decrement command

2 The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Incrementor Decrement command or the 16th clock cycle of a Write command

DS20005207B-page 30 2013-2015 Microchip Technology Inc

MCP41HVX1

44 Memory Map

The device memory supports 16 locations that areeight bits wide (16 x 8 bits) This memory spacecontains only volatile locations (see Table 4-7)

441 VOLATILE MEMORY (RAM)

There are two volatile memory locations These are

bull Volatile Wiper 0

bull Terminal Control (TCON0) Register 0

The volatile memory starts functioning at the RAMretention voltage (VRAM) The PORBOR wiper code isshown in Table 4-6

Table 4-7 shows this memory map and which serialcommands operate (and donrsquot) on each of theselocations

Accessing an ldquoinvalidrdquo address (for that device) or aninvalid command for that address will cause an errorcondition (CMDERR) on the serial interface

4411 Write to Invalid (Reserved) Addresses

Any write to a reserved address will be ignored and willgenerate an error condition To exit the error conditionthe user must take the CS pin to the VIH level and thenback to the active state (VIL)

TABLE 4-6 WIPER POR STANDARD SETTINGS

Resistance Code

Typical RAB Value

Default POR Wiper

Setting

Wiper Code

8-bit 7-bit

-502 50 k Mid-Scale 7Fh 3Fh

-103 100 k Mid-Scale 7Fh 3Fh

-503 500 k Mid-Scale 7Fh 3Fh

-104 1000 k Mid-Scale 7Fh 3Fh

TABLE 4-7 MEMORY MAP AND THE SUPPORTED COMMANDS

Address Function Allowed Commands Disallowed Commands (1) Memory Type

00h Volatile Wiper 0 Read Write Increment Decrement

mdash RAM

01h - 03h Reserved none Read Write Increment Decrement

mdash

04h Volatile TCON Register

Read Write Increment Decrement RAM

05h - 0Fh Reserved none Read Write Increment Decrement

mdash

Note 1 This command on this address will generate an error condition To exit the error condition the user musttake the CS pin to the VIH level and then back to the active state (VIL)

2013-2015 Microchip Technology Inc DS20005207B-page 31

MCP41HVX1

4412 Terminal Control (TCON) Registers

The Terminal Control (TCON) register contains fourcontrol bits for Wiper 0 Register 4-1 describes each bitof the TCON register

The state of each resistor network terminal connectionis individually controlled That is each terminalconnection (A B and W) can be individually con-necteddisconnected from the resistor network Thisallows the system to minimize the currents through thedigital potentiometer

The value that is written to this register will appear onthe resistor network terminals when the serialcommand has completed

On a PORBOR these registers are loaded with FFhfor all terminals connected The host controller needsto detect the PORBOR event and then update thevolatile TCON register values

REGISTER 4-1 TCON0 BITS(1)

R-1 R-1 R-1 R-1 RW-1 RW-1 RW-1 RW-1

D7 D6 D5 D4 R0HW R0A R0W R0B

bit 7 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo

-n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

bit 7-4 D7-D4 Reserved Forced to ldquo1rdquo

bit 3 R0HW Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the ldquoshutdownrdquo configuration of the Hardware pin1 = Resistor 0 is not forced to the hardware pin ldquoshutdownrdquo configuration0 = Resistor 0 is forced to the hardware pin ldquoshutdownrdquo configuration

bit 2 R0A Resistor 0 Terminal A (P0A pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal A to the Resistor 0 Network1 = P0A pin is connected to the Resistor 0 Network0 = P0A pin is disconnected from the Resistor 0 Network

bit 1 R0W Resistor 0 Wiper (P0W pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Wiper to the Resistor 0 Network1 = P0W pin is connected to the Resistor 0 Network0 = P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B Resistor 0 Terminal B (P0B pin) Connect Control bitThis bit connectsdisconnects the Resistor 0 Terminal B to the Resistor 0 Network1 = P0B pin is connected to the Resistor 0 Network0 = P0B pin is disconnected from the Resistor 0 Network

Note 1 These bits do not affect the wiper register values

2 The hardware SHDN pin (when active) overrides the state of these bits When the SHDN pin returns to the inactive state the TCON register will control the state of the terminals The SHDN pin does not modify the state of the TCON bits

DS20005207B-page 32 2013-2015 Microchip Technology Inc

MCP41HVX1

50 RESISTOR NETWORK

The resistor network has either 7-bit or 8-bit resolutionEach resistor network allows zero-scale to full-scaleconnections Figure 5-1 shows a block diagram for theresistive network of a device The resistor network has upto three external connections These are referred to asTerminal A Terminal B and the wiper (or Terminal W)

The resistor network is made up of several parts Theseinclude

bull Resistor Ladder Modulebull Wiperbull Shutdown Control (Terminal Connections)

Terminals A and B as well as the wiper W do not havea polarity These terminals can support both positiveand negative current

FIGURE 5-1 Resistor Block Diagram

51 Resistor Ladder Module

The RAB resistor ladder is composed of the series ofequal value Step resistors (RS) and the Full-Scale(RFS) and Zero-Scale (RZS) resistances

RAB = RZS + n times RS + RFS

Where ldquonrdquo is determined by the resolution of the deviceThe RFS and RZS resistances are discussed inSection 513 ldquoRFS and RZS Resistorsrdquo

There is a connection point (tap) between each RSresistor Each tap point is a connection point for ananalog switch The opposite side of the analog switchis connected to a common signal which is connected tothe Terminal W (Wiper) pin (see Section 52 ldquoWiperrdquo)

Figure 5-1 shows a block diagram of the ResistorNetwork The RAB (and RS) resistance has smallvariations over voltage and temperature

The end points of the resistor ladder are connected toanalog switches which are connected to the deviceTerminal A and Terminal B pins In the ideal case theseswitches would have 0 of resistance that isRFS = RZS = 0 This will also be referred as theSimplified model

For an 8-bit device there are 255 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 255 resistors thus provid-ing 256 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of7Fh is the Mid-Scale setting A wiper setting of FFhconnects Terminal W (wiper) to Terminal A (Full-Scale)Table 5-2 illustrates the full wiper setting map

For a 7-bit device there are 127 resistors in a stringbetween Terminal A and Terminal B The wiper can beset to tap onto any of these 127 resistors thus provid-ing 128 possible settings (including Terminal A andTerminal B) A wiper setting of 00h connects TerminalW (wiper) to Terminal B (Zero-Scale) A wiper setting of3Fh is the Mid-scale setting A wiper setting of 7Fh con-nects the wiper to Terminal A (Full-Scale) Table 5-2illustrates the full wiper setting map

511 RAB CURRENT (IRAB)

The current through the RAB resistor (A pin to B pin) isdependent on the voltage on the VA and VB pins andthe RAB resistance as shown in Equation 5-1

EQUATION 5-1 RAB

RS

A

RS

RS

RS

B

255

254

253

1

0

RW (1)

W

(01h)

Analog MUX

RW (1) (00h)

RW (1) (FDh)

RW (1) (FEh)

RW (1) (FFh)

Note 1 The wiper resistance is dependent onseveral factors including wiper codedevice V+ voltage terminal voltages (onA B and W) and temperature Also for the same conditions each tapselection resistance has a small variationThis RW variation has a greater effect onsome specifications (such as INL) for thesmaller resistance devices (50 k)compared to larger resistance devices(1000 k)

RAB

8-BitN =

127

126

125

1

0

(01h)

(00h)

(7Dh)

(7Eh)

(7Fh)

7-BitN = RFS

RS

RZS

Where

VA = the voltage on the VA pin

VB = the voltage on the VB pin

IRAB = the current into the VREF pin

RAB RZS n RS RFS VA VBndash

IRAB ----------------------------=+ +=

2013-2015 Microchip Technology Inc DS20005207B-page 33

MCP41HVX1

512 STEP RESISTANCE (RS)

Step resistance (RS) is the resistance from one tap set-ting to the next This value will be dependent on theRAB value that has been selected (and the full-scaleand zero-scale resistances) The RS resistors aremanufactured so that they should be very consistentwith each other and track each otherrsquos values asvoltage andor temperature change

Equation 5-2 shows the simplified and detailed equa-tions for calculating the RS value The simplified equa-tion assumes RFS = RZS = 0 Table 5-1 showsexample step resistance calculations for each deviceand the variation of the detailed model (RFS 0RZS 0) from the simplified model (RFS = RZS = 0)As the RAB resistance option increases the effects ofthe RZS and RFS resistances decrease

The total resistance of the device has minimal variationdue to operating voltage (see device characterizationgraphs)

Equation 5-2 shows calculations for the stepresistance

EQUATION 5-2 RS CALCULATION

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

8-bit 7-bit

or

RAB n RS =

RS RAB

n-----------= RS

RAB255-----------= RS

RAB127-----------=

RAB RFS n RS RZS+ +=

RS RAB RFSndash RZSndash

n---------------------------------------------=

RS

VFS VZSndash

n--------------------------------

IAB--------------------------------=

Where

ldquonrdquo = 255 (8-bit) or 127 (7-bit)

VFS = Wiper voltage at Full-Scale code

VZS = Wiper voltage at Zero-Scale code

IAB = Current between Terminal A and Terminal B

TABLE 5-1 EXAMPLE STEP RESISTANCES (RS) CALCULATIONS

Example Resistance ()

Variation(1) Resolution CommentRAB RZS

(3) RFS(3)

RS

Equation Value

5000

0 0 5000127 3937 0 7-bit (127 RS) Simplified Model(2)

80 60 4860127 3827 -280

0 0 5000255 1961 0 8-bit (255 RS) Simplified Model(2)

80 60 4860255 1906 -280

10000

0 0 10000127 7874 0 7-bit (127 RS) Simplified Model(2)

80 60 9860127 7764 -140

0 0 10000255 3922 0 8-bit (255 RS) Simplified Model (2)

80 60 9860255 3867 -140

50000

0 0 50000127 39370 0 7-bit (127 RS) Simplified Model(2)

80 60 49860127 39260 -028

0 0 50000255 19608 0 8-bit (255 RS) Simplified Model(2)

80 60 49860255 19553 -028

100000

0 0 100000127 78740 0 7-bit (127 RS) Simplified Model(2)

80 60 99860127 78630 -014

0 0 100000255 39216 0 8-bit (255 RS) Simplified Model(2)

80 60 99860255 39161 -014

Note 1 Delta from Simplified Model RS calculation value

2 Assumes RFS = RZS = 0

3 Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device including the V+ V- voltage the voltages on the A B and W terminals the wiper code selected the RAB resistance and the temperature of the device

DS20005207B-page 34 2013-2015 Microchip Technology Inc

MCP41HVX1

513 RFS AND RZS RESISTORS

The RFS and RZS resistances are artifacts of the RABresistor network implementation In the ideal model theRFS and RZS resistances would be 0 These resistorsare included in the block diagram to help better modelthe actual device operation Equation 5-3 shows how toestimate the RS RFS and RZS resistances based onthe measured voltages of VREF VFS VZS and themeasured current IVREF

EQUATION 5-3 ESTIMATING RS RFSAND RZS

52 Wiper

The wiper terminal is connected to an analog switchMUX where one side of all the analog switches areconnected together via the W terminal The other sideof each analog switch is connected to one of the tapsof the RAB resistor string (see Figure 5-1)

The value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder The wiperregister is eight bits wide and Table 5-2 shows thewiper value state for both 7-bit and 8-bit devices

The wiper resistance (RW) is the resistance of theselected analog switch in the analog MUX Thisresistance is dependent on many operationalcharacteristics of the device including the V+V- volt-age the voltages on the A B and W terminals thewiper code selected the RAB resistance and thetemperature of the device

When the wiper value is at zero-scale (00h) the wiperis connected closest to the B terminal When the wipervalue is at full-scale (FFh for 8-bit 7Fh for 7-bit) thewiper is connected closest to the A terminal

A zero-scale wiper value connects the W terminal(wiper) to the B terminal (wiper = 00h) A full-scalewiper value connects the W terminal (wiper) to the Aterminal (wiper = FFh (8-bit) or wiper = 7Fh (7-bit)) Inthese configurations the only resistance betweenTerminal W and the other terminal (A or B) is that of theanalog switches

Where

(8-bit device)

(7-bit device)

RFS VA VFSndash

IRAB --------------------------------=

RZS VZS VBndash

IRAB -------------------------------=

RS VS

IRAB ------------------=

VS VFS VZSndash

255--------------------------------=

VS VFS VZSndash

127--------------------------------=

VFS = VW voltage when the wiper code is at full-scale

VZS = VW voltage when the wiper code is at zero-scale

TABLE 5-2 VOLATILE WIPER VALUE VS WIPER POSITION

Wiper SettingProperties

7-bit 8-bit

7Fh FFh Full-Scale (W = A) Increment commands ignored

7Eh - 40h

FEh - 80h

W = N

3Fh 7Fh W = N (Mid-Scale)

3Eh - 01h

7Eh - 01h

W = N

00h 00h Zero-Scale (W = B)Decrement command ignored

2013-2015 Microchip Technology Inc DS20005207B-page 35

MCP41HVX1

521 WIPER RESISTANCE (RW)

Wiper resistance is significantly dependent on

bull The resistor networkrsquos supply voltage (VRN)bull The resistor networkrsquos terminal (A B and W)

voltagesbull Switch leakage (occurs at higher temperatures)bull IW current

Figure 5-2 shows the wiper resistance characterizationdata for all four RAB resistances and temperatures EachRAB resistance determined the maximum wiper currentbased on worst-case conditions RAB = RAB maximumand at full-scale code VBW ~= V+ (but not exceedingV+) The V+ targets were 10V 20V and 36V What thisgraph shows is that at higher RAB resistances (50 kand 100 k) and at the highest temperature (+125degC)the analog switch leakage causes an increase in themeasured result of RW where RW is measured in arheostat configuration with RW = (VBW - VBA)IBW

FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code

Since there is minimal variation of the total deviceresistance (RAB) over voltage at a constant tempera-ture (see device characterization graphs) the changein wiper resistance over voltage can have a significantimpact on the RINL and RDNL errors

522 POTENTIOMETER CONFIGURATION

In a potentiometer configuration the wiper resistancevariation does not affect the output voltage seen on theW pin and therefore is not a significant source of error

523 RHEOSTAT CONFIGURATION

In a rheostat configuration the wiper resistance varia-tion creates nonlinearity in the RBW (or RAW) value Thelower the nominal resistance (RAB) the greater thepossible relative error Also a change in voltage needsto be taken into account For the 50 k device themaximum wiper resistance at 55V is approximately 6of the total resistance while at 27V it is approximately65 of the total resistance

524 LEVEL SHIFTERS (DIGITAL-TO-ANALOG)

Since the digital logic may operate anywhere within theanalog power range level shifters are present so that thedigital signals control the analog circuitry This level shifterlogic is relative to the V- and VL voltages A delta voltageof 27V between VL and V- is required for the serialinterface to operate at the maximum specified frequency

800

1000

1200

1400

1600

1800

2000

2200

2400

esis

tanc

e R

W(

)

40C 5k IW = 17mA +25C 5k IW = 17mA +85C 5k IW = 17mA +125C 5k IW = 17mA40C 5k IW = 33mA +25C 5k IW = 33mA +85C 5k IW = 33mA +125C 5k IW = 33mA40C 5k IW =60mA +25C 5k IW = 60mA +85C 5k IW = 60mA +125C 5k IW = 60mA40C 10k IW = 830uA +25C 10k IW = 830uA +85C 10k IW = 830uA +125C 10k IW = 830uA40C 10k IW = 17mA +25C 10k IW = 17mA +85C 10k IW = 17mA +125C 10k IW = 17mA40C 10k IW = 30mA +25C 10k IW = 30mA +85C 10k IW = 30mA +125C 10k IW = 30mA40C 50k IW = 170uA +25C 50k IW = 170uA +85C 50k IW = 170uA +125C 50k IW = 170uA40C 50k IW = 330uA +25C 50k IW = 330uA +85C 50k IW = 330uA +125C 50k IW = 330uA40C 50k IW = 600uA +25C 50k IW = 600uA +85C 50k IW = 600uA +125C 50k IW = 600uA40C 100k IW = 83uA +25C 100k IW = 83uA +85C 100k IW = 83uA +125C 100k IW = 83uA40C 100k IW =170uA +25C 100k IW = 170uA +85C 100k IW = 170uA +125C 100k IW = 170uA40C 100k IW = 300uA +25C 100k IW = 300uA +85C 100k IW = 300uA +125C 100k IW = 300uA

IW = 83uA +125C (100k ) Increased wiper resistance (RW) occursdue to increased analog switch leakage athigher temperatures (such as +125C) andlarger R resistances

0

200

400

600

800

0 32 64 96 128 160 192 224 256

Wip

er R

e

DAC Wiper Code

IW = 170uA +125C (100k )IW = 170uA +125C (50k )

IW = 300uA +125C (100k )

larger RAB resistances

DS20005207B-page 36 2013-2015 Microchip Technology Inc

MCP41HVX1

53 Terminal Currents

The terminal currents are limited by several factorsincluding the RAB resistance (RS resistance) Themaximum current occurs when the wiper is at either thezero-scale (IBW) or full-scale (IAW) code In this casethe current is only going through the analog switches(see IT specification in Section 10 ldquoElectricalCharacteristicsrdquo) When the current passes throughat least one RS resistive element then the maximumterminal current (IT) has a different limit The currentthrough the RAB resistor is limited by the RABresistance The worst case (max current) occurs whenthe resistance is at the minimum RAB value

Higher current capabilities allow a greater delta voltagebetween the desired terminals for a given resistanceThis also allows a more usable range of wiper code

values without violating the maximum terminal currentspecification Table 5-3 shows resistance and currentcalculations based on the RAB resistance (RS resis-tance) for a system that supports plusmn 18V ( 36V) InRheostat configuration the minimum wiper-code valueis shown (for VBW = 36V) As the VBW voltagedecreases the minimum wiper-code value alsodecreases Using a wiper code less then this value willcause the maximum terminal current (IT) specificationto be violated

Note For high terminal-current applications it isrecommended that proper PCB layouttechniques be used to address thethermal implications of this high currentThe VQFN package has better thermalproperties than the TSSOP package

TABLE 5-3 TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)

RAB Resistance () RS(MIN) ()

I AB

(MA

X) (

mA

) (=

36V

RA

B(M

IN))

(1)

I T (

A

B

or

W (

I W))

(m

A)

(IB

W(W

= Z

S)

I AW

(W =

FS)

(1)

RB

W (

) (=

36V

IT

(MA

X))

(2)

Rh

eo

sta

t M

in lsquo

Nrsquo

wh

en

VB

W =

36

V

N

RS

(MIN

) 3

6V

I T (

mA

) (3

)

Rh

eo

sta

t V

BW

(MA

X) W

he

n

Wip

er =

01h

(V

) (=

I T(M

AX

) R

S(M

IN))

Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit

5000 4000 6000 15686 31496 900 250 1440 91 45 0392 0787

10000 8000 12000 31373 62992 450 125 2880 91 45 0392 0787

50000 40000 60000 156863 314961 090 65 5539 35 17 1020 2047

100000 80000 120000 313725 6299 045 65 5539 17 8 2039 4094

Note 1 IBW or IAW currents can be much higher than this depending on the voltage differential between TerminalB and Terminal W or Terminal A and Terminal W

2 Any RBW resistance greater than this limits the current

3 If VBW = 36V then the wiper code value must be greater than or equal to Min lsquoNrsquo Wiper codes less thanMin lsquoNrsquo will cause the wiper current (IW) to exceed the specification Wiper codes greater than Min lsquoNrsquo willcause the wiper current to be less than the maximum The Min lsquoNrsquo number has been rounded up from thecalculated number to ensure that the wiper current does not exceed the maximum specification

2013-2015 Microchip Technology Inc DS20005207B-page 37

MCP41HVX1

Figures 5-3 through 5-6 show graphs of the calculatedcurrents (minimum typical and maximum) for eachresistor option These graphs are based on 25 mA(5 k) 125 mA (10 k) and 65 mA (50 k and100 k) specifications

To ensure no damage to the resistor network (includinglong-term reliability) the maximum terminal currentmust not be exceeded This means that the applicationmust assume that the RAB resistance is the minimumRAB value (RAB(MIN) see blue lines in graphs)

Looking at the 50 k device the maximum terminalcurrent is 65 mA That means that any wiper codevalue greater than 36 ensures that the terminal currentis less than 65 mA This is ~14 of the full-scale valueIf the application could change to the 100 k devicewhich has the same maximum terminal current specifi-cation any wiper-code value greater than 18 ensuresthat the terminal current is less than 65 mA This is~7 of the full-scale value Supporting higher terminalcurrent allows a greater wiper code range for a givenVBW voltage

FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 k

FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 k

FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 k

FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 k

Figure 5-7 shows a graph of the maximum VBW voltageversus wiper code (for 5 k and 10 k devices) Toensure that no damage is done to the resistor networkthe RAB(MIN) resistance (blue line) should be used todetermine VBW voltages for the circuit Devices wherethe RAB resistance is greater than the RAB(MIN) resis-tance will naturally support a higher voltage limit

FIGURE 5-7 Maximum VBW Vs Wiper Code (5 k and 10 k devices)

RAB = 5k

0000E+0

50E-3

100E-3

150E-3

200E-3

250E-3

300E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

RAB = 10k

0000E+0

20E-3

40E-3

60E-3

80E-3

100E-3

120E-3

140E-3

0 32 64 96 128 160 192 224 256

Wiper Code

I BW

(MA

X) (A

)

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 50k

5 0E 3

60E-3

70E-3

RAB = 50k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 50k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 50k

RAB(MAX)

RAB(TYP)

RAB(MIN)

70E-3

RAB = 100k

5 0E 3

60E-3

70E-3

RAB = 100k

RAB(MIN)

40E-3

50E-3

60E-3

70E-3

AX)

(A)

RAB = 100k

RAB(TYP)

RAB(MIN)

2 0E 3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(TYP)

RAB(MIN)

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

I BW

(MA

X)(A

)

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

0000E+0

10E-3

20E-3

30E-3

40E-3

50E-3

60E-3

70E-3

0 32 64 96 128 160 192 224 256

I BW

(MA

X)(A

)

Wiper Code

RAB = 100k

RAB(MAX)

RAB(TYP)

RAB(MIN)

00

50

100

150

200

250

300

350

400

0 32 64 96 128 160 192 224 256Wiper Code

V BW

(MA

X) (V

)

RAB(MAX)RAB(TYP)

RAB(MIN)

DS20005207B-page 38 2013-2015 Microchip Technology Inc

MCP41HVX1

Table 5-4 shows the maximum VBW voltage that can beapplied across the Terminal B to Terminal W pins for agiven wiper-code value (for the 5 k and 10 kdevices) These calculations assume the ideal model(RW = RFS = RZS = 0) and show the calculationsbased on RS(MIN) and RS(MAX) Table 5-5 shows thesame calculations for the 50 k devices and Table 5-6shows the calculations for the 100 k devices Thesetables are supplied as a quick reference

TABLE 5-4 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ ndash V- = 36V5 K AND 10 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 20h 32 12549 18824 40h 64 25098

01h 1 0392 0588 21h 33 12941 19412 41h 65 25490

02h 2 0784 1176 22h 34 13333 20000 42h 66 25882

03h 3 1176 1765 23h 35 13725 20588 43h 67 25275

04h 4 1569 2353 24h 36 14118 21176 44h 68 26667

05h 5 1961 2941 25h 37 14510 21765 45h 69 27059

06h 6 2353 3529 26h 38 14902 22353 46h 70 27451

07h 7 2745 4118 27h 39 15294 22941 47h 71 27843

08h 8 3137 4706 28h 40 15686 23529 48h 72 28235

09h 9 3529 5294 29h 41 16078 24118 49h 73 28627

0Ah 10 3922 5882 2Ah 42 16471 24706 4Ah 74 29020

0Bh 11 4314 6471 2Bh 43 16863 25294 4Bh 75 29412

0Ch 12 4706 7059 2Ch 44 17255 25882 4Ch 76 29804

0Dh 13 5098 7647 2Dh 45 17647 26471 4Dh 77 30196

0Eh 14 5490 8235 2Eh 46 18039 27059 4Eh 78 30588

0Fh 15 5882 8824 2Fh 47 18431 27647 4Fh 79 30980

10h 16 5275 9412 30h 48 18824 28235 50h 80 31373

11h 17 6667 10000 31h 49 19216 28824 51h 81 31765

12h 18 7059 10588 32h 50 19608 29412 52h 82 32157

13h 19 7451 11176 33h 51 20000 30000 53h 83 32549

14h 20 7843 11765 34h 52 20392 30588 54h 84 32941

15h 21 8235 12353 35h 53 20784 31176 55h 85 33333

16h 22 8627 12941 36h 54 21176 31765 56h 86 33725

17h 23 9020 13529 37h 55 21569 32353 57h 87 34118

18h 24 9412 14118 38h 56 21961 32941 58h 88 34510

19h 25 9804 14706 39h 57 22353 33529 59h 89 34902

1Ah 26 10196 15294 3Ah 58 22745 34118 5Ah 90 35294

1Bh 27 10588 15882 3Bh 59 23137 34706 5Bh 91 35686

1Ch 28 10980 16471 3Ch 60 23529 35294 5Ch 92 - 255 360 (1 2)

1Dh 29 11373 17059 3Dh 61 23922 35882

1Eh 30 11765 17647 3Eh 62 24314 360 (1 2)

1Fh 31 12157 18235 3Fh 63 24706

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)

2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

2013-2015 Microchip Technology Inc DS20005207B-page 39

MCP41HVX1

TABLE 5-5 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 50 K DEVICES

Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 16314 24471 20h 32 32627

01h 1 1020 1529 11h 17 17333 26000 21h 33 33647

02h 2 2039 3059 12h 18 18353 27529 22h 34 34667

03h 3 3059 4588 13h 19 19373 29059 23h 35 35686

04h 4 4078 6118 14h 20 20392 30588 24h - FFh 36 - 255 360(1 2)

05h 5 5098 7647 15h 21 21412 32118

06h 6 6118 9176 16h 22 22431 33647

07h 7 7137 10706 17h 23 23451 35176

08h 8 8157 12235 18h 24 24471 360(1 2)

09h 9 9176 13765 19h 25 25490

0Ah 10 10196 15294 1Ah 26 26510

0Bh 11 11216 16824 1Bh 27 27529

0Ch 12 12235 18353 1Ch 28 28549

0Dh 13 13255 19882 1Dh 29 29569

0Eh 14 14275 21412 1Eh 30 30588

0Fh 15 15294 22941 1Fh 31 31608

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-)2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

TABLE 5-6 MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V 100 K DEVICES

Code VBW(MAX) Code VBW(MAX)

Hex Dec RS(MIN) RS(MAX) Hex Dec RS(MIN) RS(MAX)

00h 0 0000 0000 10h 16 32627

01h 1 2039 3059 11h 17 34667

02h 2 4078 6118 12h - FFh 18 - 255 360(1 2)

03h 3 6118 9176

04h 4 8157 12235

05h 5 10196 15294

06h 6 12235 18353

07h 7 14275 21412

08h 8 16314 24471

09h 9 18353 27529

0Ah 10 20392 30588

0Bh 11 22431 33647

0Ch 12 24471 360(1 2)

0Dh 13 26510

0Eh 14 28549

0Fh 15 30588

Note 1 Calculated RBW voltage is greater than 36V (highlighted in color) must be limited to 36V (V+ - V-) 2 This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT)

DS20005207B-page 40 2013-2015 Microchip Technology Inc

MCP41HVX1

54 Variable Resistor (Rheostat)

A variable resistor is created using Terminal W and eitherTerminal A or Terminal B Since the wiper-code value of0 connects the wiper to Terminal B the RBW resistanceincreases with increasing wiper-code value Converselythe RAW resistance will decrease with increasingwiper-code value Figure 5-8 shows the connectionsfrom a potentiometer to create a rheostat configuration

FIGURE 5-8 Rheostat Configuration

Equation 5-4 shows the RBW and RAW calculationsThe RBW calculation is for the resistance between thewiper and Terminal B The RAW calculation is for theresistance between the wiper and Terminal A

EQUATION 5-4 RBW AND RAW CALCULATION

55 Analog Circuitry Power Requirements

This device has two power supplies One is for thedigital interface (VL and DGND) and the other is for thehigh-voltage analog circuitry (V+ and V-) Themaximum delta voltage between V+ and V- is 36V Thedigital power signals must be between V+ and V-

If the digital ground (DGND) pin is at half the potentialof V+ (relative to V-) then the terminal pinsrsquo potentialscan be plusmn(V+2) relative to DGND

Figure 5-9 shows the relationship of the four power sig-nals This shows that the V+V- signals do not need tobe symmetric around the DGND signal

To ensure that the wiper register has been properlyloaded with the PORBOR value the VL voltage mustbe at the minimum specified operating voltage (refer-enced to DGND)

FIGURE 5-9 Analog Circuitry Voltage Ranges

56 Resistor Characteristics

561 V+V- LOW-VOLTAGE OPERATION

The resistor network is specified from 20V to 36V Atvoltages below 20V the resistor network will functionbut the operational characteristics may be outside thespecified limits Please refer to Section 20 ldquoTypicalPerformance Curvesrdquo for additional information

562 RESISTOR TEMPCO

Biasing the ends (Terminal A and Terminal B) nearmid-supply ((V+ - |V-|)2) will give the worst switchresistance temperature coefficient

A

B

W

Resistor

RAW RBWor

RAW

RBW

Simplified Model (assumes RFS = RZS = 0)

Detailed Model

Where 8-bit 7-bit

RBW n RS =

RAW FSV nndash RS =

RS RAB

Resolution----------------------------= RS

RAB255-----------= RS

RAB127-----------=

n = Wiper code

FSV = Full-scale value (255 for 8-bit or 127 for 7-bit)

Where

n = Wiper code

FSV = The full-scale value (255 for 8-bit or 127 for 7-bit)

RBW RZS n RS +=

RAW RFS FSV nndash RS +=

DGND

Vol

tage

s R

ela

tive

to D

GN

D

Vmdash

V+ ndash V- Voltage

V+

VL +36V max +10V min

This can be anywhere between V- and V+

2013-2015 Microchip Technology Inc DS20005207B-page 41

MCP41HVX1

57 Shutdown Control

Shutdown is used to minimize the devicersquos currentconsumption The MCP41HVX1 has two methods toachieve this

bull Hardware Shutdown Pin (SHDN)

bull Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42X1 devices

571 HARDWARE SHUTDOWN PIN (SHDN)

The SHDN pin is available on the potentiometerdevices When the SHDN pin is forced active (VIL)

bull The P0A terminal is disconnectedbull The P0W terminal is connected to the P0B termi-

nal (see Figure 4-5)bull The Serial Interface is NOT disabled and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does not corruptthe values in the Volatile Wiper Registers nor theTCON register When the Shutdown mode is exited(SHDN pin is inactive (VIH))

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-10 Hardware Shutdown Resistor Network Configuration

572 TERMINAL CONTROL REGISTER (TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A B and W) to theresistor network This register is shown in Register 4-1

The R0HW bit forces the selected resistor network intothe same state as the SHDN pin Alternate low-powerconfigurations may be achieved with the R0A R0Wand R0B bits

When the R0HW bit is lsquo0rsquo

bull The P0A terminal is disconnectedbull The P0W terminal is simultaneously connected to

the P0B terminal (see Figure 5-11)

The R0HW bit does NOT corrupt the values in theVolatile Wiper registers nor the TCON register Whenthe Shutdown mode is exited (R0HW bit = 1)

bull The device returns to the wiper setting specified by the volatile wiper value

bull The TCON register bits return to controlling the terminal connection state

FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)

573 INTERACTION OF SHDN PIN AND TCON REGISTER

Figure 4-6 shows how the SHDN pin signal and theR0HW bit signal interact to control the hardwareshutdown of the resistor network

FIGURE 5-12 R0HW bit and SHDN pin Interaction

A

B

W

Re

sist

or

Net

wo

rk

Note When the R0HW bit forces the resistornetwork into the hardware SHDN statethe state of the TCON0 registerrsquos R0AR0W and R0B bits is overridden (ignored)When the state of the R0HW bit no longerforces the resistor network into thehardware SHDN state the TCON0registerrsquos R0A R0W and R0B bits returnto controlling the terminal connectionstate In other words the R0HW bit doesnot corrupt the state of the R0A R0W andR0B bits

A

B

W

Re

sist

or

Net

wo

rk

SHDN (from pin)

R0HW (from TCON register)

To Pot 0 Hardware Shutdown Control

DS20005207B-page 42 2013-2015 Microchip Technology Inc

MCP41HVX1

60 SERIAL INTERFACE (SPI)

The MCP41HVX1 devices support the SPI serialprotocol This SPI operates in the Slave mode (doesnot generate the serial clock) The devicersquos SPI com-mand format operates on multiples of eight bits

The SPI interface uses up to four pins These are

bull CS ndash Chip Select bull SCK ndash Serial Clock bull SDI ndash Serial Data In bull SDO ndash Serial Data Out

A typical SPI interface is shown in Figure 6-1 In theSPI interface the Masterrsquos Output pin is connected tothe Slaversquos Input pin and the Masterrsquos Input pin isconnected to the Slaversquos Output pin

The MCP41HVX1 SPI module supports two (of thefour) standard SPI modes These are Mode 00 and11 The SPI mode is determined by the state of theSCK pin (VIH or VIL) when the CS pin transitions frominactive (VIH) to active (VIL)

FIGURE 6-1 Typical SPI Interface Block Diagram

Note Some Host Controller SPI modules onlyoperate with 16-bit transfers For theseHost Controllers only the Read and WriteCommands or the Continuous Incrementor Decrement Commands that are aneven multiple of Increment or Decrementcommands may be used

SDISDO

MCP41HVX1

SDOSDI

SCKSCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

HostController

Typical SPI Interface Connections

CSIO

WLATIO

SHDNIO

2013-2015 Microchip Technology Inc DS20005207B-page 43

MCP41HVX1

61 SDI SDO SCK and CS Operation

The operation of the four SPI interface pins arediscussed in this section These pins are

bull Serial Data In (SDI)

bull Serial Data Out (SDO)

bull Serial Clock (SCK)

bull The Chip Select Signal (CS)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command TheChip Select (CS) pin frames the SPI commands

611 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device The value on this pin is latched on the risingedge of the SCK signal

612 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device The value on this pin is driven on thefalling edge of the SCK signal

Once the CS pin is forced to the active level (VIL) theSDO pin will be driven The state of the SDO pin isdetermined by the serial bitrsquos position in the commandthe command selected and if there is a command errorstate (CMDERR)

613 SERIAL CLOCK (SCK)

The Serial Clock (SCK) signal is the clock signal of theSPI module The frequency of the SCK pin determinesthe SPI frequency of operation

The SPI interface is specified to operate up to 10 MHzThe actual clock rate depends on the configuration ofthe system and the serial command used Table 6-1shows the SCK frequency

614 THE CHIP SELECT SIGNAL (CS)

The Chip Select (CS) signal is used to select the deviceand frame a command sequence To start a commandor sequence of commands the CS signal must transitionfrom the inactive state (VIH) to an active state (VIL)

After the CS signal has gone active the SDO pin isdriven and the clock bit counter is reset

If an error condition occurs for an SPI command thenthe command bytersquos Command Error (CMDERR) bit (onthe SDO pin) will be driven low (VIL) To exit the errorcondition the user must take the CS pin to the VIH level

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the Address Pointer)While the CS pin is in the inactive state (VIH) the serialinterface is ignored This allows the host controller tointerface to other SPI devices using the same SDISDO and SCK signals

615 LOW-VOLTAGE SUPPORT

The Serial Interface is designed to also support 18Voperation (at reduced specifications ndash frequencythresholds etc) This allows the MCP41HVX1 deviceto interface to low-voltage host controllers

At 18V VL operation the DGND signal must be 09V orgreater above the V- signal If VL is 20V or greaterthen the DGND signal can be tied to the V- signal (seeTable 6-1)

616 SPLIT RAIL SUPPORT

The Serial Interface is designed to support split railsystems In a split rail system the microcontroller canoperate at a lower voltage than the MCP41HXX1device This is achieved with the VIH specification

For VL 27V the minimum VIH = 045 VL So if themicrocontroller VOH at 18V is 08 VDD then VL canbe a maximum of 32V (see Equation 6-1)

See Section 81 ldquoSplit Rail Applicationsrdquo for addi-tional discussion on split rail support

EQUATION 6-1 CALCULATING MAX VL FOR MICROCONTROLLER AT 18V

TABLE 6-1 SCK FREQUENCY

VL Voltage

Command

CommentRead

Write Increment Decrement

27V 10 MHz 10 MHz

18V 1 MHz 1 MHz DGND = V- + 09V

20V 1 MHz 1 MHz DGND = V-

Note There is a required delay after the CS pingoes active to the 1st edge of the SCK pin

If VOH = 08 times VDD = 08 times 18V = 144V

Then VIH(MIN) = 144V

With VIH = 045 times VL

Then VL = 144V045 = 32V

DS20005207B-page 44 2013-2015 Microchip Technology Inc

MCP41HVX1

62 The SPI Modes

The SPI module supports two (of the four) standard SPImodes These are Mode 00 and 11 The mode isdetermined by the state of the SDI pin on the risingedge of the first clock bit (of the 8-bit byte)

621 MODE 00

In Mode 00 SCK Idle state = low (VIL) data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK

622 MODE 11

In Mode 11 SCK Idle state = high (VIH) data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK

63 SPI Waveforms

Figures 6-2 through 6-5 show the different SPI com-mand waveforms Figure 6-2 and Figure 6-3 are readand write commands Figure 6-4 and Figure 6-5 areIncrement and Decrement commands

64 Daisy Chaining

This SPI Interface does NOT support daisy chaining

FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)

FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

2013-2015 Microchip Technology Inc DS20005207B-page 45

MCP41HVX1

FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)

FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

PIC Writes to SSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PIC Writes to SSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0 C1 X X

ldquo1rdquo = Valid Commandldquo0rdquo = Invalid Command

CMDERR bit

DS20005207B-page 46 2013-2015 Microchip Technology Inc

MCP41HVX1

70 DEVICE COMMANDS

The MCP41HVX1rsquos SPI command format supportssixteen memory address locations and four com-mands These commands are shown in Table 7-1

Commands may be sent when the CS pin is driven to VILThe 8-bit commands (Increment Wiper and DecrementWiper commands) contain a command byte while 16-bitcommands (Read Data and Write Data commands)contain a command byte and a data byte The commandbyte contains two data bits (see Figure 7-1)

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on theSDI and SDO pins

71 Command Format

All commands have a Command Byte which specifiesthe register address and the command Commandswhich require data (write and read commands) alsohave the Data Byte

711 COMMAND BYTE

The command byte has three fields the address thecommand and two data bits (see Figure 7-1)Currently only one of the data bits is defined (D8) Thisis for the Write command

The device memory is accessed when the mastersends a proper command byte to select the desiredoperation The memory location to be accessed is con-tained in the command bytersquos AD3AD0 bits The actiondesired is contained in the command bytersquos C1C0 bits(see Table 7-1) C1C0 determines if the desired mem-ory location will be read written incremented (wipersetting +1) or decremented (wiper setting -1) TheIncrement and Decrement commands are only valid onthe volatile wiper registers

As the command byte is being loaded into the deviceon the SDI pin the devicersquos SDO pin is driving TheSDO pin will output high bits for the first six bits of thatcommand On the 7th bit the SDO pin will output theCMDERR bit state (see Section 7111 ldquoErrorConditionrdquo) The 8th bit state depends on thecommand selected

FIGURE 7-1 General SPI Command Formats

TABLE 7-1 COMMANDS

C1C0 Bit

StatesCommand Name

of Bits

11 Read Data 16-Bits

00 Write Data 16-Bits

01 Increment Wiper 8-Bits

10 Decrement Wiper 8-Bits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

Data Address Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

Data Address Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

D9

D8

This bit is only used as the CMDERR bit

This bit is not used Maintained for code compatibility with MCP41XX MCP42XX and MCP43XX devices

2013-2015 Microchip Technology Inc DS20005207B-page 47

MCP41HVX1

TABLE 7-2 MEMORY MAP AND THE SUPPORTED COMMANDS

AddressCommand

Data(10-bits)(1)

SPI String (Binary)

Value Function MOSI (SDI pin) MISO (SDO pin)(2)

00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn

Increment Wiper mdash 0000 0100 1111 1111Decrement Wiper mdash 0000 1000 1111 1111

01h ndash 03h(4)

Reserved mdash mdash mdash mdash

04h(3) Volatile TCON Register

Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn

05h ndash 0Fh(4)

Reserved mdash mdash mdash mdash

Note 1 The data memory is eight bits wide so the two MSbs (D9D8) are ignored by the device 2 All these addresscommand combinations are valid so the CMDERR bit is set Any other

addresscommand combination is a command error state and the CMDERR bit will be clear3 Increment or Decrement commands are invalid for these addresses

4 Reserved addresses Any command is invalid for these addresses

DS20005207B-page 48 2013-2015 Microchip Technology Inc

MCP41HVX1

7111 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3AD0) and the two command bitsreceived (C1C0) are a valid combination TheCMDERR bit is high if the combination is valid and lowif the combination is invalid (see Table 7-3)

The command error bit will also be low if a write to aReserved Address has been specified SPI commandsthat do not have a multiple of eight clocks are ignored

Once an error condition has occurred any followingcommands are ignored All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH)

Aborting a Transmission

All SPI transmissions must have the correct number ofSCK pulses to be executed The command is notexecuted until the complete number of clocks havebeen received Some commands also require the CSpin to be forced inactive (VIH) If the CS pin is forced tothe inactive state (VIH) the serial interface is resetPartial commands are not executed

SPI is more susceptible to noise than other busprotocols The most likely case is that this noisecorrupts the value of the data being clocked into theMCP41HVX1 or the SCK pin is injected with extra clockpulses This may cause data to be corrupted in thedevice or cause a command error to occur since theaddress and command bits were not a valid combina-tion The extra SCK pulse will also cause the SPI data(SDI) and clock (SCK) to be out of sync Forcing the CSpin to the inactive state (VIH) resets the serial interfaceThe SPI interface will ignore activity on the SDI andSCK pins until the CS pin transition to the active stateis detected (VIH to VIL)

712 DATA BYTE

Only the Read command and the Write command usethe data byte (see Figure 7-1) These commandsconcatenate the eight bits of the data byte with the onedata bit (D8) contained in the command byte to formnine bits of data (D8D0) The command byte formatsupports up to nine bits of data but the MCP41HVX1only uses the lower eight bits That means that thefull-scale code of the 8-bit resistor network is FFhWhen at full-scale the wiper connects to Terminal AThe D8 bit is maintained for code compatibility with theMCP41XX MCP42XX and MCP43XX devices

The D9 bit is currently unused and corresponds to theposition on the SDO data of the CMDERR bit

713 CONTINUOUS COMMANDS

The device supports the ability to execute commandscontinuously while the CS pin is in the active state (VIL)Any sequence of valid commands may be received

The following example is a valid sequence of events

1 CS pin driven active (VIL)

2 Read Command

3 Increment Command (Wiper 0)

4 Increment Command (Wiper 0)

5 Decrement Command (Wiper 0)

6 Write Command

7 Read Command

8 CS pin driven inactive (VIH)

TABLE 7-3 COMMAND ERROR BIT

CMDERR Bit States

Description

1 ldquoValidrdquo CommandAddress combination

0 ldquoInvalidrdquo CommandAddress combination

Note 1 When data is not being received by theMCP41HVX1 it is recommended that theCS pin be forced to the inactive level (VIL)

2 It is also recommended that longcontinuous command strings should bebroken down into single commands orshorter continuous command strings Thisreduces the probability of noise on the SCKpin corrupting the desired SPI commands

Note 1 It is recommended that while the CS pinis active only one type of commandshould be issued When changing com-mands it is recommended to take the CSpin inactive then force it back to theactive state

2 It is also recommended that longcommand strings should be broken downinto shorter command strings Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string

2013-2015 Microchip Technology Inc DS20005207B-page 49

MCP41HVX1

72 Write Data

The Write command is a 16-bit command The formatof the command is shown in Figure 7-2

A Write command to a volatile memory locationchanges that location after a properly formatted Writecommand (16-clock) has been received

721 SINGLE WRITE TO VOLATILE MEMORY

The write operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Write command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinOnce all 16 bits have been received the specifiedvolatile address is updated A write will not occur if thewrite command isnrsquot exactly 16 clocks pulses

Figures 6-2 and 6-3 show possible waveforms for asingle write

FIGURE 7-2 Write Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid AddressCommand combination (1)

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

DS20005207B-page 50 2013-2015 Microchip Technology Inc

MCP41HVX1

722 CONTINUOUS WRITES TO VOLATILE MEMORY

Continuous writes are possible only when writing to thevolatile memory registers (address 00h and 04h)

Figure 7-3 shows the sequence for three continuouswrites The writes do not need to be to the same volatilememory address

FIGURE 7-3 Continuous Write Sequence

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AD3

AD2

AD1

AD0

0 0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 51

MCP41HVX1

73 Read Data

The Read command is a 16-bit command The formatof the command is shown in Figure 7-4

The first six bits of the Read command determine theaddress and the command The 7th clock will outputthe CMDERR bit on the SDO pin The 8th clock will befixed at 1 and with the remaining eight clocks thedevice will transmit the eight data bits (D7D0) of thespecified address (AD3AD0)

Figure 7-4 shows the SDI and SDO information for aRead command

731 SINGLE READ

The read operation requires that the CS pin be in theactive state (VIL) Typically the CS pin will be in theinactive state (VIH) and is driven to the active state(VIL) The 16-bit Read command (command byte anddata byte) is then clocked (SCK pin) in on the SDI pinThe SDO pin starts driving data on the 7th bit(CMDERR bit) and the addressed data comes out onthe 8th through 16th clocks Figures 6-2 through 6-3show possible waveforms for a single read

FIGURE 7-4 Read Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

Valid AddressCommand combination

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location

COMMAND BYTE DATA BYTE

SDI

SDO

READ DATA

DS20005207B-page 52 2013-2015 Microchip Technology Inc

MCP41HVX1

732 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly Continuous reads are possible to allmemory locations

Figure 7-5 shows the sequence for three continuousreads The reads do not need to be to the samememory address

FIGURE 7-5 Continuous Read Sequence

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

AD3

AD2

AD1

AD0

1 1 X X X X X X X X X X

1 1 1 1 1 1 1 1 D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BYTE DATA BYTE

SDI

SDO

Note 1 If a Command Error (CMDERR) occurs at this bit location () then all following SDO bits will bedriven low until the CS pin is driven inactive (VIH)

2013-2015 Microchip Technology Inc DS20005207B-page 53

MCP41HVX1

74 Increment Wiper

The Increment command is an 8-bit command TheIncrement command can only be issued to specificvolatile memory locations (the wiper register) The for-mat of the command is shown in Figure 7-6

An Increment command to the volatile memory locationchanges that location after a properly formattedcommand (eight clocks) has been received

Increment commands provide a quick and easymethod to modify the value of the volatile wiper locationby +1 with minimal overhead

FIGURE 7-6 Increment Command ndash SDI and SDO States

741 SINGLE INCREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle increment The increment operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) The 8-bit Increment command(command byte) is then clocked in on the SDI pin by theSCK pins The SDO pin drives the CMDERR bit on the7th clock

The wiper value will increment up to FFh on 8-bitdevices and 7Fh on 7-bit devices After the wiper valuehas reached full-scale (8-bit = FFh 7-bit = 7Fh) thewiper value will not be incremented further SeeTable 7-4 for additional information on the Incrementcommand versus the current volatile wiper value

The increment operations only require the Incrementcommand byte while the CS pin is active (VIL) for asingle increment

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

Note Table 7-2 shows the valid addresses forthe Increment Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(INCR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared (the CSpin is forced to the inactive state) TABLE 7-4 INCREMENT OPERATION VS

VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Increment Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) No

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) Yes

DS20005207B-page 54 2013-2015 Microchip Technology Inc

MCP41HVX1

742 CONTINUOUS INCREMENTS

Continuous increments are possible only when writingto the volatile wiper registers (address 00h)

Figure 7-7 shows a continuous increment sequence

When executing a continuous Increment commandthe selected wiper will be altered from n to n+1 for eachIncrement command received The wiper value willincrement up to FFh on 8-bit devices and 7Fh on 7-bitdevices After the wiper value has reached full-scale(8-bit = FFh 7-bit = 7Fh) the wiper value will not beincremented further

Increment commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theIncrement command can be followed by any other validcommand

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is incremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired increment occurs

FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X AD3

AD2

AD1

AD0

0 1 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper register (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an error condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 55

MCP41HVX1

75 Decrement Wiper

The Decrement command is an 8-bit command TheDecrement command can only be issued to volatilewiper locations The format of the command is shownin Figure 7-8

A Decrement command to the volatile wiper locationchanges that location after a properly formattedcommand (eight clocks) has been received

Decrement commands provide a quick and easymethod to modify the value of the volatile wiper locationby -1 with minimal overhead

FIGURE 7-8 Decrement Command ndash SDI and SDO States

751 SINGLE DECREMENT

Typically the CS pin starts at the inactive state (VIH)but may already be in the active state due to thecompletion of another command

Figures 6-4 through 6-5 show possible waveforms for asingle decrement The decrement operation requiresthat the CS pin be in the active state (VIL) Typically theCS pin will be in the inactive state (VIH) and is driven tothe active state (VIL) Then the 8-bit Decrementcommand (command byte) is clocked in on the SDI pinby the SCK pin The SDO pin drives the CMDERR biton the 7th clock

The wiper value will decrement from the wiperrsquosfull-scale value (FFh on 8-bit devices and 7Fh on 7-bitdevices) If the wiper register has a zero-scale value(00h) then the wiper value will not decrement SeeTable 7-5 for additional information on the Decrementcommand vs the current volatile wiper value

The Decrement commands only require the Decrementcommand byte while the CS pin is active (VIL) for asingle decrement

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatunexpected transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

Note Table 7-2 shows the valid addresses forthe Decrement Wiper command Otheraddresses are invalid

AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 Note 1 3

(DECR COMMAND (n+1))

SDI

SDO

COMMAND BYTE

Note 1 Only functions when writing the volatilewiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combinationall following SDO bits will be low until theCMDERR condition is cleared(the CS pin is forced to the inactivestate)

TABLE 7-5 DECREMENT OPERATION VS VOLATILE WIPER VALUE

Current Wiper Setting Wiper (W)

Properties

Decrement Command Operates7-bit

Pot 8-bit Pot

7Fh FFh Full-Scale (W = A) Yes

7Eh40h

FEh80h

W = N

3Fh 7Fh W = N (Mid-Scale) Yes

3Eh01h

7Eh01h

W = N

00h 00h Zero-Scale (W = B) No

DS20005207B-page 56 2013-2015 Microchip Technology Inc

MCP41HVX1

752 CONTINUOUS DECREMENTS

Continuous decrements are possible only when writingto the volatile wiper register (address 00h)

Figure 7-9 shows a continuous decrement sequence

When executing continuous Decrement commandsthe selected wiper will be altered from n to n-1 for eachDecrement command received The wiper value willdecrement from the wiperrsquos full-scale value (FFh on8-bit devices and 7Fh on 7-bit devices) If the Wiperregister has a zero-scale value (00h) then the wipervalue will not decrement See Table 7-5 for additionalinformation on the Decrement command vs the currentvolatile wiper value

Decrement commands can be sent repeatedly withoutraising CS until a desired condition is met

When executing a continuous command string theDecrement command can be followed by any othervalid command

The wiper terminal will move after the command hasbeen received (8th clock)

After the wiper is decremented to the desired positionthe CS pin should be forced to VIH to ensure thatldquounexpectedrdquo transitions on the SCK pin do not causethe wiper setting to change Driving the CS pin to VIHshould occur as soon as possible (within devicespecifications) after the last desired decrement occurs

FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States

AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X AD3

AD2

AD1

AD0

1 0 X X

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1 2

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3 4

(DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE COMMAND BYTE COMMAND BYTE

Note 1 Only functions when writing the volatile wiper registers (AD3AD0 = 0h)

2 Valid AddressCommand combination

3 Invalid AddressCommand combination

4 If an Error Condition occurs (CMDERR = L) all following SDO bits will be low until the CMDERRcondition is cleared (the CS pin is forced to the inactive state)

2013-2015 Microchip Technology Inc DS20005207B-page 57

MCP41HVX1

NOTES

DS20005207B-page 58 2013-2015 Microchip Technology Inc

MCP41HVX1

80 APPLICATIONS EXAMPLES

Digital potentiometers have a multitude of practicaluses in modern electronic circuits The most popularuses include precision calibration of set pointthresholds sensor trimming LCD bias trimming audioattenuation adjustable power supplies motor controlovercurrent trip setting adjustable gain amplifiers andoffset trimming

81 Split Rail Applications

Split rail applications are when one device operatesfrom one voltage level (rail) and the second deviceoperates from a second voltage level (rail) The typicalscenario will be when the microcontroller is operating ata lower voltage level (for power savings etc) and theMCP41HVX1 is operating at a higher voltage level tomaximize operational performance This configurationis shown in Figure 8-1

To ensure that communication properly occursbetween the devices care must be done to verify thecompatibility of the VIL VIH VOL and VOH levels of theinterface signals between the devices These interfacesignals are

bull CS bull SCK bull SDI bull SDObull SHDN bull WLAT

When the microcontroller is at a lower-voltage rail theVOH of the microcontroller needs to be greater than theVIH of the MCP41HVX1 and the VIL of the microcon-troller needs to be greater than the VOL of theMCP41HVX1

Table 8-1 shows the calculated maximumMCP41HVX1 VL based on the microcontrollerrsquosminimum VOH

FIGURE 8-1 Example Split Rail System

FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)

Note VOH specifications typically have a currentload specified This is due to the pinexpected to drive externally circuitry If thepin is unloaded (or lightly loaded) then theVOH of the pin could approach the deviceVDD (this is dependent on the implemen-tation of the output driver circuit) For VOLunloaded (or lightly loaded) pins couldapproach the device VSS For VOH and VOL characterization graphsfrom an example microcontroller see thePIC16F1934 data sheet (DS41364) Fig-ure 31-15 and Figure 31-16

TABLE 8-1 MCP41HVX1 VL VOLTAGE BASED ON MICROCONTROLLER VOH

PICreg MCU

MCP41HVX1 Max VL VDD

(minimum)

VOH (minimum)(1)

Formula (with load)

Calculated

18V

07 times VDD 126V 28V

08 times VDD 144V 32V

085 times VDD 153V 34V

09 times VDD 162V 36V

VDD 18V 40V

VDD - 07V 11V 244V

27V

07 times VDD 189V 42V

08 times VDD 216V 48V

09 times VDD 243V 54V

VDD 27V 55V

Note 1 The VOH minimum voltage is determined by the load on the pin If the load is small a typical outputrsquos voltage should approach the devicersquos VDD voltage This is depen-dent on the devicersquos output driver design

2 Split Rail voltages are dependent on VIL VIH VOL and VOH of the microcontroller and the MCP41HVX1 devices

VoltageRegulator

20V (18V min)

30V

PICreg MCU MCP41HVX1SDICS SCK

WLAT

SDOCS

SCK

IO

SDOSDI

SHDN IO

2013-2015 Microchip Technology Inc DS20005207B-page 59

MCP41HVX1

82 Using Shutdown Modes

Figure 8-3 shows a possible application circuit wherethe independent terminals could be usedDisconnecting the wiper allows the transistor input tobe taken to the bias voltage level (disconnecting Aandor B may be desired to reduce system current)Disconnecting Terminal A modifies the transistor inputby the RBW rheostat value to the Common BDisconnecting Terminal B modifies the transistor inputby the RAW rheostat value to the Common A TheCommon A and Common B connections could beconnected to V+ and V-

FIGURE 8-3 Example Application Circuit using Terminal Disconnects

83 High-Voltage DAC

A high-voltage DAC can be implemented using theMCP41HVXX with voltages as high as 36V The circuitis shown in Figure 8-4 The equation to calculate thevoltage output is shown in Equation 8-1

FIGURE 8-4 High-Voltage DAC

EQUATION 8-1 DAC OUTPUT VOLTAGE CALCULATION

Balance Bias

W

B

Input

Input

To baseof Transistor(or Amplifier)

A

Common B

Common AR2

OPA170

R1

D1

MCP41HVXX

A

B

OPA170VOUT

V+

V+

V+

+

+

-

-

VD

High Voltage DAC

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N N255--------- VD 1

R1R2-------+

=

VOUT N N127--------- VD 1

R1R2-------+

=

DS20005207B-page 60 2013-2015 Microchip Technology Inc

MCP41HVX1

84 Variable Gain Instrumentation Amplifier

A variable gain instrumentation amplifier can beimplemented using the MCP41HVXX along with ahigh-voltage dual analog switch and a high-voltageinstrumentation amplifier An example circuit is shownin Figure 8-5 The equation to calculate the voltageoutput is shown in Equation 8-2

FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System

EQUATION 8-2 DAC OUTPUT VOLTAGE CALCULATION

85 Audio Volume Control

A digital volume control can be implemented with theMCP41HVXX Figure 8-6 shows a simple audiovolume control implementation

Figure 8-7 shows a circuit-referenced voltage crossingdetect circuit The output of this circuit could be used tocontrol the wiper latch of the MCP41HVXX device inthe audio volume control circuit to reduce zipper noiseor to update the different channels at the same time

The op amp (U1) could be an MCP6001 while the gen-eral purpose comparators (U2 and U3) could be anMCP6541 U4 is a simple AND gate

U1 establishes the signal zero reference The upperlimit of the comparator is set above its offset The WLATpin is forced high whenever the voltage falls between2502V and 2497V (a 0005V window)

The capacitor C1 AC couples the VIN signal into the cir-cuit before feeding into the windowed comparator (andMCP41HVXX Terminal A pin)

FIGURE 8-6 Audio Volume Control

FIGURE 8-7 Referenced Voltage Crossing Detect

AAD8221 VOUT

V+

BW

MC

P41

HV

xx

DA

DB

ADG1207S1A

S8A

S1B

S8B

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

Gain N 1494 kN

255--------- RAB---------------------------+=

Gain N 1494 kN

127--------- RAB---------------------------+=

MCP41HVXXA

B

VOUT

V+

V+

VIN

V-

V-

SDISCKWLAT

VL GND +

-

R1

R5

WLAT

+5V

+5V

VIN +5V

R2

100 k

+5V

R3

R4

100 k

200 k

10 k

90 k

+

-

+

-

+

-

C1 1 microF

U1

U2

U3

U4

2013-2015 Microchip Technology Inc DS20005207B-page 61

MCP41HVX1

86 Programmable Power Supply

The ADP1611 is a step-up DC-to-DC switching con-verter Using the MCP41HVXX device allows the powersupply to be programmable up to 20V Figure 8-8shows a programmable power supply implementation

Equation 8-3 shows the equation to calculate theoutput voltage of the programmable power supply Thisoutput is derived from the RBW resistance of theMCP41HVXX device and the R2 resistor TheADP1611 will adjust its output voltage to maintain123V on the FB pin

When power is connected L1 acts as a short andVOUT is a diode drop below the +5V voltage The VOUTvoltage will ramp to the programmed value

FIGURE 8-8 Programmable Power Supply

EQUATION 8-3 POWER SUPPLY OUTPUT VOLTAGE CALCULATION

87 Programmable Bidirectional Current Source

A programmable bidirectional current source can beimplemented with the MCP41HVXX Figure 8-9 showsan implementation where U1 and U2 work together todeliver the desired current (dependent on selecteddevice) in both directions The circuit is symmetrical(R1A = R1B R2A = R2B R3A = R3B) in order to improvestability If the resistors are matched the load current(IL) calculation is shown below

EQUATION 8-4 LOAD CURRENT (IL)

FIGURE 8-9 Programmable Bidirectional Current Source

MCP41HVXX

A

B

VOUT

R1

D1

ADP1611

+5V

WV+

C1 01 microF

220 k

85 k

IN

SW

COMP

RT

FB

SS

C5 10 microF

C4 150 pF

C3 22 nF

C2 10 microF

R2

(100 k)

L147 microF

N = 0 to 255 (decimal)

7-bit

8-bit

N = 0 to 127 (decimal)

VOUT N 123V 1

N RAB

255---------------------

R2----------------------

+

=

VOUT N 123V 1

N RAB

127---------------------

R2----------------------

+

=

IL R2A R3A+

R1A R3A--------------------------------- VW=

R1A

+15V

+15V

150 k

R3A

R4

50 k

500

+

-

-

+

C1

10 pF

U2

U1

MC

P41

HV

XX A

B

W

V+

V--15V

-15V

VL

C2

10 pF

R2A

1495 k

R1B

150 k

R2B

15 k

IL

R3B 50 k

DS20005207B-page 62 2013-2015 Microchip Technology Inc

MCP41HVX1

88 LCD Contrast Control

The MCP41HVXX can be used for LCD contrastcontrol Figure 8-10 shows a simple programmableLCD contrast control implementation

Some LCD panels support a fixed power supply of upto 28V The high voltage digital potentiometers wipercan support contrast adjustments through the entirevoltage range

FIGURE 8-10 Programmable Contrast Control

89 Serial Interface Communication Times

Table 8-2 shows the time for each SPI serial interfacecommand as well as the effective data update rate thatcan be supported by the digital interface (based on thetwo SPI serial interface frequencies) So the SerialInterface performance along with the wiper responsetime would be used to determine your applicationrsquosvolatile Wiper register update rate

MC

P41

HV

XX A

B

D1 LCD Panel

W

C1 10 microF

VOUT (LCD Bias) Fixed

+16V to +26VContrast Adj

uController

SDOSCK

CS

(up to +28V)

TABLE 8-2 SERIAL INTERFACE TIMESFREQUENCIES(1)

Command of Serial

Interface bits

Example Command Time (μs)

Effective Data Update

Frequency (kHz)(2)

Bytes Transferred

of Serial Interface bits 1 MHz 10 MHz 1 MHz 10 MHz

Write Single Byte 16 1 16 16 16 62500 625000

Write Continuous Bytes

N times 16 5 80 80 8 12500 125000

Read Byte 16 1 16 16 16 62500 625000

Read Continuous Bytes

N times 16 5 80 80 8 12500 125000

Increment Wiper 8 1 8 8 08 125000 1250000

Continuous Increments

N times 8 5 40 40 4 25000 250000

Decrement Wiper 8 1 8 8 08 125000 1250000

Continuous Decrements

N times 8 5 40 40 4 25000 250000

Note 1 Includes the Start or Stop bits

2 This is the command frequency multiplied by the number of bytes transferred

2013-2015 Microchip Technology Inc DS20005207B-page 63

MCP41HVX1

810 Implementing Log Steps with a Linear Digital Potentiometer

In audio volume control applications the use oflogarithmic steps is desirable since the human earhears in a logarithmic manner The use of a linearpotentiometer can approximate a log potentiometerbut with fewer steps An 8-bit potentiometer canachieve fourteen 3 dB log steps plus a 100 (0 dB)and a mute setting

Figure 8-11 shows a block diagram of one of theMCP45HVx1 resistor networks being used to attenuatean input signal In this case the attenuation will beground referenced Terminal B can be connected to acommon-mode voltage but the voltages on the A Band wiper terminals must not exceed theMCP45HVX1rsquos V+V- voltage limits

FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced

Equation 8-5 shows the equation to calculate voltagedB gain ratios for the digital potentiometer whileEquation 8-6 shows the equation to calculateresistance dB gain ratios These two equations assumethat the B terminal is connected to ground

If Terminal B is not directly resistively connected toground then this Terminal B to ground resistance(RB2GND) must be included into the calculationEquation 8-7 shows this equation

EQUATION 8-5 dB CALCULATIONS (VOLTAGE)

EQUATION 8-6 dB CALCULATIONS (RESISTANCE) ndash CASE 1

EQUATION 8-7 dB CALCULATIONS (RESISTANCE) ndash CASE 2

Table 5-3 shows the codes that can be used for 8-bitdigital potentiometers to implement the log attenuationThe table shows the wiper codes for -3 dB -2 dB and-1 dB attenuation steps This table also shows thecalculated attenuation based on the wiper codersquos linearstep Calculated attenuation values less than thedesired attenuation are shown with red text At lowerwiper code values the attenuation may skip a step Ifthis occurs the next attenuation value is coloredmagenta to highlight that a skip occurred For examplein the -3 dB column the -48 dB value is highlightedsince the -45 dB step could not be implemented (thereare no wiper codes between 2 and 1)

P0A

MCP45HVX1

P0W

P0B

L = 20 times log10 (VOUTVIN)

dB VOUTVIN Ratio

-3 070795-2-1

079433089125

L = 20 times log10 (RBWRAB)

Terminal B connected to Ground (see Figure 8-11)

L = 20 times log10 ( (RBW + RB2GND)(RAB + RB2GND) )

Terminal B through RB2GND to Ground

DS20005207B-page 64 2013-2015 Microchip Technology Inc

MCP41HVX1

TABLE 8-3 LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

of Steps

-3 dB Steps -2 dB Steps -1 dB Steps

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

Desired Attenuation

Wiper Code

Calculated Attenuation

(1)

0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB

1 -3 dB 180 -3025 dB -2 dB 203 -1981 dB -1 dB 227 -1010 dB

2 -6 dB 128 -5987 dB -4 dB 161 -3994 dB -2 dB 203 -1981 dB

3 -9dB 90 -9046 dB -6 dB 128 -5987 dB -3 dB 180 -3025 dB

4 -12 dB 64 -12007 dB -8 dB 101 -8044 dB -4 dB 161 -3994 dB

5 -15 dB 45 -15067 dB -10 dB 81 -9961 dB -5 dB 143 -5024 dB

6 -18 dB 32 -18028 dB -12 dB 64 -12007 dB -6 dB 128 -5987 dB

7 -21 dB 23 -20896 dB -14 dB 51 -13979 dB -7 dB 114 -6993 dB

8 -24 dB 16 -24048 dB -16 dB 40 -16090 dB -8 dB 101 -8044 dB

9 -27 dB 11 -27303 dB -18 dB 32 -18028 dB -9 dB 90 -9046 dB

10 -30 dB 8 -30069 dB -20 dB 25 -20172 dB -10 dB 81 -9961 dB

11 -33 dB 6 -32568 dB -22 dB 20 -22110 dB -11 dB 72 -10984 dB

12 -36 dB 4 -36090 dB -24 dB 16 -24048 dB -12 dB 64 -12007 dB

13 -39 dB 3 -38588 dB -26 dB 13 -25852 dB -13 dB 57 -13013 dB

14 -42 dB 2 -42110 dB -28 dB 10 -28131 dB -14 dB 51 -13979 dB

15 -48 dB 1 -48131 dB -30 dB 8 -30069 dB -15 dB 45 -15067 dB

16 Mute 0 Mute -32 dB 6 -32602 dB -16 dB 40 -16090 dB

17 -34 dB 5 -34151 dB -17 dB 36 -17005 dB

18 -36 dB 4 -36090 dB -18 dB 32 -18028 dB

19 -38 dB 3 -38588 dB -19 dB 29 -18883 dB

20 -42 dB 2 -42110 dB -20 dB 25 -20172 dB

21 -48 dB 1 -48131 dB -21 dB 23 -20896 dB

22 Mute 0 Mute -22 dB 20 -22110 dB

23 -23 dB 18 -23025 dB

24 -24 dB 16 -24048 dB

25 -25 dB 14 -25208 dB

26 -26 dB 13 -25852 dB

27 -27dB 11 -27303 dB

28 -28 dB 10 -28131 dB

29 -29 dB 9 -29046 dB

30 -30 dB 8 -30069 dB

31 -31 dB 7 -31229 dB

32 -33 dB 6 -32568 dB

33 -34 dB 5 -34151 dB

34 -36 dB 4 -36090 dB

35 -39 dB 3 -38588 dB

36 -42 dB 2 -42110 dB

37 -48 dB 1 -48131 dB

38 Mute 0 Mute

Legend Calculated Attenuation Value Color Code Black rarr Above Target Value Red rarr Below Target Value Desired Attenuation Value Color Code Magenta rarr Skipped Desired Attenuation Value(s)

Note 1 Attenuation values do not include errors from digital potentiometer errors such as Full-Scale Error or Zero-Scale Error

2013-2015 Microchip Technology Inc DS20005207B-page 65

MCP41HVX1

811 Design Considerations

In the design of a system with the MCP41HVX1devices the following considerations should be takeninto account

bull Power Supply Considerations

bull Layout Considerations

8111 POWER SUPPLY CONSIDERATIONS

The typical application will require a bypass capacitorin order to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-12 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VL) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies V+ and V-should reside on the analog plane

FIGURE 8-12 Typical Microcontroller Connections

8112 LAYOUT CONSIDERATIONS

In the design of a system with the MCP41HVX1devices the following layout considerations should betaken into account

bull Noise

bull PCB Area Requirements

bull Power Dissipation

81121 Noise

Inductively-coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP41HVX1rsquos performanceCareful board layout minimizes these effects andincreases the Signal-to-Noise Ratio (SNR) Multi-layerboards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that thesilicon is capable of providing Particularly harshenvironments may require shielding of critical signals

If low noise is desired breadboards and wire-wrappedboards are not recommended

81122 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-4 shows the package dimensionsand area for the different package options The tablealso shows the relative area factor compared to thesmallest area The VQFN package is the suggestedpackage for space critical applicationsVL

VDD

DGND VSS

MC

P41

HV

XX

01 microF

PIC

reg M

icro

con

tro

ller

01 microF

SDI

CS

W

B

ASDO

SCK

V+

01 microF

V-

V-

TABLE 8-4 PACKAGE FOOTPRINT (1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm)

Are

a (

mm

2 )

Re

lati

ve A

rea

X Y

14 TSSOP ST 510 640 3264 131

20 VQFN MQ 500 500 2500 1

Note 1 Does not include recommended landpattern dimensions

DS20005207B-page 66 2013-2015 Microchip Technology Inc

MCP41HVX1

8113 RESISTOR TEMPERATURE COEFFICIENT

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in the devicecharacterization graphs

These curves show that the resistor network isdesigned to correct for the change in resistance astemperature increases This technique reduces theend-to-end change in RAB resistance

81131 Power Dissipation

The power dissipation of the high-voltage digital poten-tiometer will most likely be determined by the powerdissipation through the resistor networks

Table 8-5 shows the power dissipation through the resis-tor ladder (RAB) when Terminal A = +18V and TerminalB = -18V This is not the worst case power dissipationbased on the 25 mA terminal current specificationTable 8-6 shows the worst-case current (per resistornetwork) which is independent of the RAB value)

TABLE 8-5 RAB POWER DISSIPATION

RAB Resistance () | VA | + |VB | = (V)

Power (mW)(1) Typical Min Max

5000 4000 6000 36 324

10000 8000 12000 36 162

50000 40000 60000 36 324

100000 80000 120000 36 162

Note 1 Power = V times I = V2RAB(MIN)

TABLE 8-6 RBW POWER DISSIPATION

RAB () (Typical)

| VW | + |VB | = (V)IBW

(mA)(2)Power (mW)(1)

5000 36 25 900

10000 36 125 450

50000 36 65 234

100000 36 65 234

Note 1 Power = V times I

2 See Electrical Specifications (max IW)

2013-2015 Microchip Technology Inc DS20005207B-page 67

MCP41HVX1

90 DEVICE OPTIONS

91 Standard Options

911 PORBOR WIPER SETTING

The default wiper setting (mid-scale) is indicated to thecustomer in three digit suffixes -202 -502 -103 and-503 Table 9-1 indicates the devicersquos default settings

92 Custom Options

Custom options can be made available

921 CUSTOM WIPER VALUE ON PORBOR EVENT

Customers can specify a custom wiper setting via theNSCAR process

TABLE 9-1 DEFAULT PORBOR WIPER SETTING SELECTION

Typical RAB

Value Pa

ckag

e

Co

de Default

POR Wiper Setting

Device Resolution

Wiper Code

50 k -502 Mid-Scale 8-bit 7Fh

7-bit 3Fh

100 k -103 Mid-Scale 8-bit 7Fh

7-bit 3Fh

500 k -503 Mid-Scale 8-bit 7Fh

7-bit 3Fh

1000 k -104 Mid-Scale 8-bit 7Fh

7-bit 3Fh

Note 1 Non-Recurring Engineering (NRE)charges and minimum ordering require-ments apply for custom orders Pleasecontact Microchip sales for additionalinformation

2 A custom device will be assigned customdevice marking

DS20005207B-page 68 2013-2015 Microchip Technology Inc

MCP41HVX1

100 DEVELOPMENT SUPPORT

101 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP41HVX1 devices Thecurrently available tools are shown in Table 10-1

Figure 10-1 shows how the TSSOP20EV bond-outPCB can be populated to easily evaluate theMCP41HVX1 devices Evaluations can use thePICkittrade Serial Analyzer to control the position of thevolatile wiper and state of the TCON register

Figure 10-2 shows how the SOIC14EV bond-out PCBcan be populated to evaluate the MCP41HVX1devices The use of the PICkit Serial Analyzer wouldrequire blue wire since the header H1 is not compatiblyconnected

These boards may be purchased directly from theMicrochip web site at wwwmicrochipcom

102 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 10-2 showssome of these documents

TABLE 10-1 DEVELOPMENT TOOLS

Board Name Part Comment

20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit Serial Analyzer (Order DV164122)

14-pin SOICTSSOPDIP Evaluation Board SOIC14EV

TABLE 10-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073

AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316

AN1080 Understanding Digital Potentiometers Resistor Variations DS01080

AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737

AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692

AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691

AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219

mdash Digital Potentiometer Design Guide DS22017

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005

2013-2015 Microchip Technology Inc DS20005207B-page 69

MCP41HVX1

FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV

0 0

0

0

41HV

X1

Four blue wire jumpers to connectPICkittrade Serial interface (SPI) to device pins 1x6 male header with 90deg right angle

MCP41HVX1-xxxESTinstalled in U3 (bottom 14 pins of TSSOP-20 footprint)

Connected toDigital Ground

Connected toDigital Power (VL) Plane

Through-hole TestPoint (Orange)Wiper 0

VL

SCK

CS

SDI

SDO

V+

P0A

P0W

P0B

V-

(DGND) Plane

WLAT

SHDN

DGND

NC0

10 microF

P0A pin shorted(jumpered) to V+ pin

P0B pin shorted(jumpered) to V- pin

DS20005207B-page 70 2013-2015 Microchip Technology Inc

MCP41HVX1

FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV

MC

P41

HV

X1

10 microF VL

SC

KC

SS

DI

SD

OW

LA

TS

HD

N

V+

P0

AP

0W

P0

BV

-D

GN

DN

C

0

0

0

0

2013-2015 Microchip Technology Inc DS20005207B-page 71

MCP41HVX1

NOTES

DS20005207B-page 72 2013-2015 Microchip Technology Inc

MCP41HVX1

110 PACKAGING INFORMATION

111 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code RoHS Compliant JEDEC designator for Matte Tin (Sn) This package is RoHS Compliant The RoHS Compliant

JEDEC designator ( ) can be found on the outer packagingfor this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

20-Lead VQFN (5x5x09 mm) Example

PIN 1PIN 1

3e

14-Lead TSSOP (44 mm) Example

YYWWNNN

XXXXXXXX

Part Number Code Part Number Code

MCP41HV51-502EST 41H51502 MCP41HV31-502EST 41H31502

MCP41HV51-103EST 41H51103 MCP41HV31-103EST 41H31103

MCP41HV51-503EST 41H51503 MCP41HV31-503EST 41H31503

MCP41HV51-104EST 41H51104 MCP41HV31-104EST 41H31104

41H51502

E524

256

Part Number Code Part Number Code

MCP41HV51-502EMQ 502EMQ MCP41HV31-502EMQ 502EMQ

MCP41HV51-103EMQ 103EMQ MCP41HV31-103EMQ 103EMQ

MCP41HV51-503EMQ 503EMQ MCP41HV31-503EMQ 503EMQ

MCP41HV51-104EMQ 104EMQ MCP41HV31-104EMQ 104EMQ

41HV31

502EMQ

1524256

2013-2015 Microchip Technology Inc DS20005207B-page 73

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 74 2013-2015 Microchip Technology Inc

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

2013-2015 Microchip Technology Inc DS20005207B-page 75

MCP41HVX1

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

DS20005207B-page 76 2013-2015 Microchip Technology Inc

MCP41HVX1

020 C

020 C

010 C A B005 C

(DATUM B)(DATUM A)

CSEATING

PLANE

NOTE 1

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

010 C A B

010 C A B

010 C

008 C

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

2X

20X

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

D

E

BA

D2

E2

K20X b

e

L

(A3)

A

A1

With 040 mm Contact Length

2013-2015 Microchip Technology Inc DS20005207B-page 77

MCP41HVX1

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

REF Reference Dimension usually without tolerance for information purposes onlyBSC Basic Dimension Theoretically exact value shown without tolerances

123

Notes

Pin 1 visual index feature may vary but must be located within the hatched areaPackage is saw singulatedDimensioning and tolerancing per ASME Y145M

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Contact-to-Exposed Pad

Contact WidthContact Length 035L

K 020

b 025040

-

030045

-

035

MINDimension Limits

StandoffContact Thickness

Number of Terminals

Overall HeightPitch

000A1(A3)

eA 080

N

UnitsMAXNOM

005002020 REF

065 BSC090

20

100

MILLIMETERS

335325315Exposed Pad Length D2Overall WidthExposed Pad Width

Overall Length D

E2 315E

325

500 BSC

500 BSC335

With 040 mm Contact Length

DS20005207B-page 78 2013-2015 Microchip Technology Inc

MCP41HVX1

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2139B (MQ)

20-Lead Plastic Quad Flat No Lead Package (MQ) ndash 5x5x10 mm Body [VQFN]

SILK SCREEN

1

2

20

Thermal Via Diameter VThermal Via Pitch EV

030100

BSC Basic Dimension Theoretically exact value shown without tolerances

NotesDimensioning and tolerancing per ASME Y145M

For best soldering results thermal vias if used should be filled or tented to avoid solder loss duringreflow process

1

2

For the most current package drawings please see the Microchip Packaging Specification located athttpwwwmicrochipcompackaging

Note

Dimension LimitsUnits

C1

Optional Center Pad Width

Contact Pad SpacingContact Pad Spacing

Optional Center Pad Length

Contact Pitch

C2

T2W2

335335

MILLIMETERS

065 BSCMIN

EMAX

450450

Contact Pad Length (X20)Contact Pad Width (X20)

Y1X1

055040

GDistance Between Pads 020

NOM

With 040 mm Contact Length

C1

C2

EV

EV

E

X2

Y2OslashV

G

Y1

X1

2013-2015 Microchip Technology Inc DS20005207B-page 79

MCP41HVX1

NOTES

DS20005207B-page 80 2013-2015 Microchip Technology Inc

MCP41HVX1

APPENDIX A REVISION HISTORY

Revision B (June 2015)

bull Test limits in Section 10 ldquoElectrical Character-isticsrdquo were corrected The following specifica-tions were updated

- Full-Scale Error

- Zero-Scale Error

- Potentiometer Differential Nonlinearity(10 17) (see Appendix B13)

- Rheostat Integral Nonlinearity(12131417) (see Appendix B5)

- Rheostat Differential Nonlinearity (12131417) (see Appendix B5)

bull Corrected the packaging diagram for the VQFN package The 5 x 5 mm VQFN package is speci-fied but the 4 x 4 mm QFN package information was shown

bull Updated Device Features table to include MCP45HVX1 devices

bull Added Section 810 ldquoImplementing Log Steps with a Linear Digital Potentiometerrdquo

Revision A (May 2013)

bull Original Release of this Document

APPENDIX B TERMINOLOGY

This appendix discusses the terminology used in thisdocument and describes how a parameter is measured

B1 Potentiometer (Voltage Divider)

The potentiometer configuration is when all threeterminals of the device are tied to different nodes in thecircuit This allows the potentiometer to output avoltage proportional to the input voltage Thisconfiguration is sometimes called voltage dividermode The potentiometer is used to provide a variablevoltage by adjusting the wiper position between the twoendpoints as shown in Figure B-1 Reversing thepolarity of the A and B terminals will not affectoperation

FIGURE B-1 POTENTIOMETER CONFIGURATION

The temperature coefficient of the RAB resistors isminimal by design In this configuration the resistors allchange uniformly so minimal variation should be seen

B2 Rheostat (Variable Resistor)

The rheostat configuration is when two of the three dig-ital potentiometerrsquos terminals are used as a resistiveelement in the circuit With Terminal W (wiper) andeither Terminal A or Terminal B a variable resistor iscreated The resistance will depend on the tap settingof the wiper (and the wiperrsquos resistance) Theresistance is controlled by changing the wiper settingFigure B-2 shows the two possible resistors that can beused Reversing the polarity of the A and B terminalswill not affect operation

FIGURE B-2 RHEOSTAT CONFIGURATION

Note Devices tested after the product markingDate Code of June 30 2015 are tested tothese new limits

A

B

W

V1

V3

V2

A

B

W

Resistor

RAW RBWor

2013-2015 Microchip Technology Inc DS20005207A-page 81

MCP41HVX1

B3 Resolution

The resolution is the number of wiper output states thatdivide the full-scale range For the 8-bit digitalpotentiometer the resolution is 28 meaning the digitalpotentiometer wiper code ranges from 0 to 255

B4 Step Resistance (RS)

The resistance step size (RS) equates to one LSb of theresistor ladder Equation B-1 shows the calculation forthe step resistance (RS)

EQUATION B-1 RS CALCULATION

B5 Wiper Resistance

Wiper resistance is the series resistance of the analogswitch that connects the selected resistor ladder nodeto the wiper terminal common signal (see Figure 5-1)

A value in the volatile wiper register selects whichanalog switch to close connecting the W terminal tothe selected node of the resistor ladder

The resistance is dependent on the voltages on theanalog switch source gate and drain nodes as well asthe devicersquos wiper code temperature and the currentthrough the switch As the device voltage decreasesthe wiper resistance increases

The wiper resistance is measured by forcing a currentthrough the W and B terminals (IWB) and measuring thevoltage on the W and A terminals (VW and VA)Equation B-2 shows how to calculate this resistance

EQUATION B-2 RW CALCULATION

The wiper resistance in potentiometer-generatedvoltage divider applications is not a significant sourceof error (it does not effect the output voltage seen onthe W pin)

The wiper resistance in rheostat applications cancreate significant nonlinearity as the wiper is movedtoward zero scale (00h) The lower the nominalresistance the greater the possible error

B6 RZS Resistance

The analog switch between the resistor ladder and theTerminal B pin introduces a resistance which we callthe Zero-Scale resistance (RZS) Equation B-3 showshow to calculate this resistance

EQUATION B-3 RZS CALCULATION

B7 RFS Resistance

The analog switch between the resistor ladder and theTerminal A pin introduces a resistance which we callthe Full-Scale resistance (RFS) Equation B-4 showshow to calculate this resistance

EQUATION B-4 RFS CALCULATION

Ideal

Measured

RS Ideal RAB

2N

1ndash----------------= or

VA VBndash

IAB-------------------------

2N

1ndash--------------------------

RS Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

RW Measured VW VAndash

IWB---------------------------=

Where

VA = Voltage on Terminal A pin

VW = Voltage on Terminal W pin

IWB = Measured current through W and B pins

RZS Measured VW ZS VBndash

IAB--------------------------------------------=

Where

VW(ZS) = Voltage on Terminal W pin at Zero-Scale wiper code

VB = Voltage on Terminal B pin

IAB = Measured Current through A and B pins

Where

VA = Voltage on Terminal A pin

VW(FS) = Voltage on Terminal W pin at Full-Scale wiper code

IAB = Measured Current through A and B pins

RFS Measured VA VW FS ndash

IAB--------------------------------------------=

DS20005207A-page 82 2013-2015 Microchip Technology Inc

MCP41HVX1

B8 Least Significant Bit (LSb)

This is the difference between two successive codes(either in resistance or voltage) For a given outputrange it is divided by the resolution of the device(Equation B-5)

EQUATION B-5 LSb CALCULATION

B9 Monotonic Operation

Monotonic operation means that the devicersquos output(resistance (RBW) or voltage (VW)) increases with everyone code step (LSb) increment of the wiper register

FIGURE B-3 THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION)

FIGURE B-4 THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION)

In Resistance In Voltage Ideal

Measured

LSb Ideal =RAB

2N

1ndash---------------

VA VBndash

2N

1ndash-------------------

LSb Measured

VW FS VW ZS ndash

IAB---------------------------------------------------------------

2N

1ndash---------------------------------------------------------------=

VW FS VW ZS ndash

2N

1ndash----------------------------------------------------------

Where

2N - 1= 255 (MCP41HV5161)

= 127 (MCP41HV3141)

VA = Voltage on Terminal A pin

VB = Voltage on Terminal B pin

VAB = Measured Voltage between A and B pins

IAB = Measured Current through A and B pins

VW(FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh)

VW(ZS) = Measured Voltage on W pin at Zero-Scale code (00h)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =

0x3F

0x3E

0x3D

0x03

0x02

0x01

0x00

Dig

ital I

npu

t Cod

e

Resistance (RBW)

RW ( tap)

RS0

RS1

RS3

RS62

RS63

RBW = RSn + RW( Tap n) n = 0

n =

2013-2015 Microchip Technology Inc DS20005207A-page 83

MCP41HVX1

B10 Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-5) is the error ofthe VW pin relative to the expected VW voltage(theoretical) for the maximum device wiper registercode (code FFh for 8-bit and code 7Fh for 7-bit) seeEquation B-6 The error is dependent on the resistiveload on the VOUT pin (and where that load is tied tosuch as VSS or VDD) For loads (to VSS) greater thanspecified the full-scale error will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-6 FULL-SCALE ERROR

FIGURE B-5 FULL-SCALE ERROR EXAMPLE

B11 Zero-Scale Error (EZS)

The Zero-Scale Error (see Figure B-6) is the differencebetween the ideal and measured VOUT voltage with theWiper register code equal to 00h (Equation B-7) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror will be greater

The error is determined by the theoretical voltage stepsize to give an error in LSb

EQUATION B-7 ZERO SCALE ERROR

FIGURE B-6 ZERO-SCALE ERROR EXAMPLE

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thefull-scale output value decreases whichincreases the full-scale error

EFS VW FS VAndash

VLSb IDEAL ---------------------------------------=

Where

EFS = Expressed in LSb

VWFS) = The VW voltage when the wiper register code is at full-scale

VIDEAL(FS) = The ideal output voltage when the wiper register code is at full-scale

VLSb(IDEAL) = The theoretical voltage step size

VW

Ideal Transfer

Actual

Wiper Code0

Full-ScaleError (EFS)

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thezero-scale output value decreases whichdecreases the zero-scale error

Where

EFS = Expressed in LSb

VWZS) = the VW voltage when the wiper register code is at zero-scale

VLSb(IDEAL) = the theoretical voltage step size

EZS VW ZS

VLSb IDEAL -------------------------------------=

VW

Ideal Transfer

Actual

Wiper Code0

Function

Full-Scale

VA

Transfer Function

VB

VFS

VZS

Zero-ScaleError (EZS)

DS20005207A-page 84 2013-2015 Microchip Technology Inc

MCP41HVX1

B12 Integral Nonlinearity (P-INL) Potentiometer Configuration

The Potentiometer Integral nonlinearity (P-INL) error isthe maximum deviation of an actual VW transferfunction from an ideal transfer function (straight line)

In the MCP41HVX1 P-INL is calculated using the zero-scale and full-scale wiper code end points P-INL isexpressed in LSb P-INL is also called relativeaccuracy Equation B-8 shows how to calculate the P-INL error in LSb and Figure B-7 shows an example ofP-INL accuracy

Positive P-INL means higher VW voltage than idealNegative P-INL means lower VW voltage than ideal

EQUATION B-8 P-INL ERROR

FIGURE B-7 P-INL ACCURACY

B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration

The Potentiometer Differential nonlinearity (P-DNL)error (see Figure B-8) is the measure of VW step sizebetween codes The ideal step size between codes is1 LSb A P-DNL error of zero would imply that everycode is exactly 1 LSb wide If the P-DNL error is lessthan 1 LSb the Digital Potentiometer guaranteesmonotonic output and no missing codes The P-DNLerror between any two adjacent codes is calculated inEquation B-9

P-DNL error is the measure of variations in code widthsfrom the ideal code width

EQUATION B-9 P-DNL ERROR

FIGURE B-8 P-DNL ACCURACY

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the INL Error

Where

INL = Expressed in LSb

Code = Wiper Register Value

VW(Code) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS))255

EINL VW Code VLSb Measured Code ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

VW Output Voltage

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the DNL Error

Where

DNL = Expressed in LSb

VW(Code = n) = The measured VW output voltage with a given Wiper register code

VLSb = For Ideal VAB Resolution For Measured (VW(FS) - VW(ZS)) of RS

EDNL VW code n 1+= VW code n= ndash VLSb Measured ndash

VLSb Measured -----------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

VW Output Voltage

2013-2015 Microchip Technology Inc DS20005207A-page 85

MCP41HVX1

B14 Integral Nonlinearity (R-INL) Rheostat Configuration

The Rheostat Integral nonlinearity (R-INL) error is themaximum deviation of an actual RBW transfer functionfrom an ideal transfer function (straight line)

In the MCP41HVX1 INL is calculated using the Zero-Scale and Full-Scale wiper code end points R-INL isexpressed in LSb R-INL is also called relativeaccuracy Equation B-10 shows how to calculate the R-INL error in LSb and Figure B-9 shows an example ofR-INL accuracy

Positive R-INL means higher VOUT voltage than idealNegative R-INL means lower VOUT voltage than ideal

EQUATION B-10 R-INL ERROR

FIGURE B-9 R-INL ACCURACY

B15 Differential Nonlinearity (R-DNL) Rheostat Configuration

The Rheostat Differential nonlinearity (R-DNL) error(see Figure B-10) is the measure of RBW step sizebetween codes in actual transfer function The idealstep size between codes is 1 LSb A R-DNL error ofzero would imply that every code is exactly 1 LSb wideIf the R-DNL error is less than 1 LSb the RBW Resis-tance guarantees monotonic output and no missingcodes The R-DNL error between any two adjacentcodes is calculated in Equation B-11

R-DNL error is the measure of variations in code widthsfrom the ideal code width A R-DNL error of zero wouldimply that every code is exactly 1 LSb wide

EQUATION B-11 R-DNL ERROR

FIGURE B-10 R-DNL ACCURACY

Where

INL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EINL RBW code RBW Ideal ndash

RLSb Ideal -----------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

INL lt 0

Ideal transferfunction

INL lt 0

RBW Resistance

Where

DNL = Expressed in LSb

RBW(Code = n) = The measured RBW resistance with a given wiper register code

RLSb = For Ideal RAB Resolution For Measured RBW(FS) of RS

EDNL VOUT code n 1+= VOUT code n= ndash VLSb Measured ndash

VLSB Measured --------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

111

110

101

100

011

010

001

000

WiperCode

Actualtransferfunction

Ideal transferfunction

Narrow code lt 1 LSb

Wide code gt 1 LSb

RBW Resistance

DS20005207A-page 86 2013-2015 Microchip Technology Inc

MCP41HVX1

B16 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VW voltageTypically calibration of the output voltage isimplemented to improve system performance

The error in bits is determined by the theoretical voltagestep size to give an error in LSb

Equation B-12 shows the Total Unadjusted Errorcalculation

EQUATION B-12 TOTAL UNADJUSTED ERROR CALCULATION

B17 Settling Time

The settling time is the time delay required for the VWvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVW voltage is within the specified accuracy It is relatedto the RC characteristics of the resistor ladder andwiper switches

In the MCP41HVX1 the settling time is a measure ofthe time delay until the VW voltage reaches within 05LSb of its final value when the volatile wiper registerchanges from zero-scale to full-scale (or full-scale tozero-scale)

B18 Major-Code Transition Glitch

Major-code transition glitch is the impulse energyinjected into the Wiper pin when the code in the Wiperregister changes state It is normally specified as thearea of the glitch in nV-Sec and is measured when thedigital code is changed by 1 LSb at the major carry tran-sition (Example 01111111 to 10000000 or10000000 to 01111111)

B19 Digital Feedthrough

The Digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all 0s to all 1s and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe digital potentiometer is not being written to the out-put register

B20 Power-Supply Sensitivity (PSS)

PSS indicates how the output (VW or RBW) of the digitalpotentiometer is affected by changes in the supply volt-age PSS is the ratio of the change in VW to a changein VDD for mid-scale output of the digital potentiometerThe VW is measured while the VDD is varied from 55Vto 27V as a step and expressed in which is the change of the VW output voltage with respect to the change of the VDD voltage

EQUATION B-13 PSS CALCULATION

B21 Power-Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the digital potentiom-eter is affected by changes in the supply voltage PSRRis the ratio of the change in VW to a change in VDD forfull-scale output of the digital potentiometer The VW ismeasured while the VDD is varied plusmn10 (VA and VBvoltages held constant) and expressed in dB or microVV

Note Analog switch leakage increases withtemperature This leakage increasessubstantially at higher temperatures (gt ~100degC) As analog switch leakage increases thewiper output voltage (VW) decreaseswhich affects the total Unadjusted Error

Where

ET = Expressed in LSb

VW_Actual(code) = The measured W pin output voltage at the specified code

VW_Ideal(code) = The calculated W pin output voltage at the specified code(code times VLSb(Ideal))

VLSb(Ideal) = VAB RS 8-bit = VAB255 7-bit = VAB127

ET VW_Actual code VW_Ideal Code ndash

VLSb Ideal ------------------------------------------------------------------------------------------------------------=

Where

PSS = Expressed in

VW(55V) = The measured VW output voltage with VDD = 55V

VW(27V) = The measured VW output voltage with VDD = 27V

PSS

VW 55V VW 27V ndash

VW 55V ----------------------------------------------------------------------

55V 27Vndash 55V

--------------------------------------------------------------------------------------------------------=

2013-2015 Microchip Technology Inc DS20005207A-page 87

MCP41HVX1

B22 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies theerror in the ratio RAWRWB due to temperature driftThis is typically the critical error when using a digitalpotentiometer in a voltage divider configuration

B23 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end resistance (Nominal resistanceRAB) due to temperature drift This is typically thecritical error when using the device in an adjustableresistor configuration

Characterization curves of the resistor temperaturecoefficient (Tempco) are shown in Section 20 ldquoTypi-cal Performance Curvesrdquo

B24 -3 dB Bandwidth

This is the frequency of the signal at the A terminal thatcauses the voltage at the W pin to be -3 dB from itsexpected value based on its wiper code The expectedvalue is determined by the static voltage value on the ATerminal and the wiper-code value The output decreasesdue to the RC characteristics of the resistor network

B25 Resistor Noise Density (eN_WB)

This is the random noise generated by the devicersquosinternal resistances It is specified as a spectral density(voltage per square root Hertz)

DS20005207A-page 88 2013-2015 Microchip Technology Inc

MCP41HVX1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP41HV31 Single Potentiometer (7-bit) with SPI Interface

MCP41HV31T Single Potentiometer (7-bit) with SPI Interface (Tape and Reel)

MCP41HV51 Single Potentiometer (8-bit) with SPI Interface

MCP41HV51T Single Potentiometer (8-bit) with SPI Interface (Tape and Reel)

Resistance Version

502 = 5 k103 = 10 k503 = 50 k104 = 100 k

Temperature Range

E = -40degC to +125degC

Package ST = 14-Lead Plastic Thin Shrink Small Outline 44 mm Body

MQ = 20-Lead Plastic Quad Flat No Lead Package 5 x 5 x 09 mm Body

PART NO X XX

PackageTemperatureRange

Device

Examples

a) MCP41HV51T-502EST 5 k 8-bit 14-LD TSSOP

b) MCP41HV51T-103EST 10 k 8-bit 14-LD TSSOP

c) MCP41HV31T-503EST 50 k 7-bit 14-LD TSSOP

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

a) MCP41HV51T-502EMQ 5 k 8-bit 20-LD VQFN (5x5)

b) MCP41HV51T-103EMQ 10 k 8-bit 20-LD VQFN (5x5)

c) MCP41HV31T-503EMQ 50 k 7-bit 20-LD VQFN (5x5)

d) MCP41HV31T-104EMQ 100 k 7-bit 20-LD VQFN (5x5)

XXX

ResistanceVersion

2013-2015 Microchip Technology Inc DS20005207B-page 89

MCP41HVX1

NOTES

DS20005207B-page 90 2013-2015 Microchip Technology Inc

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights

2013-2015 Microchip Technology Inc

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISOTS 16949 ==

Trademarks

The Microchip name and logo the Microchip logo dsPIC FlashFlex flexPWR JukeBlox KEELOQ KEELOQ logo Kleer LANCheck MediaLB MOST MOST logo MPLAB OptoLyzer PIC PICSTART PIC32 logo RightTouch SpyNIC SST SST Logo SuperFlash and UNIO are registered trademarks of Microchip Technology Incorporated in the USA and other countries

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the USA

Analog-for-the-Digital Age BodyCom chipKIT chipKIT logo CodeGuard dsPICDEM dsPICDEMnet ECAN In-Circuit Serial Programming ICSP Inter-Chip Connectivity KleerNet KleerNet logo MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail RightTouch logo REAL ICE SQI Serial Quad IO Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademarks of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries

All other trademarks mentioned herein are property of their respective companies

copy 2013-2015 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-63277-544-3

Microchip received ISOTS-169492009 certification for its worldwide

DS20005207B-page 91

headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India The Companyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

DS20005207B-page 92 2013-2015 Microchip Technology Inc

AMERICASCorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200 Fax 480-792-7277Technical Support httpwwwmicrochipcomsupportWeb Address wwwmicrochipcom

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Austin TXTel 512-257-3370

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China - Dongguan

Tel 86-769-8702-9880

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ASIAPACIFICChina - XiamenTel 86-592-2388138 Fax 86-592-2388130

China - ZhuhaiTel 86-756-3210040 Fax 86-756-3210049

India - BangaloreTel 91-80-3090-4444 Fax 91-80-3090-4123

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Korea - DaeguTel 82-53-744-4301Fax 82-53-744-4302

Korea - SeoulTel 82-2-554-7200Fax 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala LumpurTel 60-3-6201-9857Fax 60-3-6201-9859

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Thailand - BangkokTel 66-2-694-1351Fax 66-2-694-1350

EUROPEAustria - WelsTel 43-7242-2244-39Fax 43-7242-2244-393Denmark - CopenhagenTel 45-4450-2828 Fax 45-4485-2829

France - ParisTel 33-1-69-53-63-20 Fax 33-1-69-30-90-79

Germany - DusseldorfTel 49-2129-3766400

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Germany - PforzheimTel 49-7231-424750

Italy - Milan Tel 39-0331-742611 Fax 39-0331-466781

Italy - VeniceTel 39-049-7625286

Netherlands - DrunenTel 31-416-690399 Fax 31-416-690340

Poland - WarsawTel 48-22-3325737

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Sweden - StockholmTel 46-8-5090-4654

UK - WokinghamTel 44-118-921-5800Fax 44-118-921-5820

Worldwide Sales and Service

012715

  • 78-Bit Single +36V (plusmn18V) Digital POT with SPI Serial Interface and Volatile Memory
  • Features
  • Package Types
  • Description
  • Device Block Diagram
  • Device Features
  • 10 Electrical Characteristics
    • Absolute Maximum Ratings dagger
    • ACDC Characteristics
      • ACDC Notes
        • 11 SPI Mode Timing Waveforms and Requirements
          • FIGURE 1-1 Settling Time Waveforms
          • TABLE 1-1 Wiper Settling Timing
          • FIGURE 1-2 SPI Timing Waveform (Mode = 11)
          • TABLE 1-2 SPI Requirements (Mode = 11)
          • FIGURE 1-3 SPI Timing Waveform (Mode = 00)
          • TABLE 1-3 SPI Requirements (Mode = 00)
            • Temperature Characteristics
              • 20 Typical Performance Curves
              • 30 Pin Descriptions
                • TABLE 3-1 Pinout Description for The MCP41HVX1
                • 31 Positive Power Supply Input (VL)
                • 32 Serial Clock (SCK)
                • 33 Chip Select (CS)
                • 34 Serial Data In (SDI)
                • 35 Serial Data Out (SDO)
                • 36 Wiper Latch (WLAT)
                • 37 Shutdown (SHDN)
                • 38 Digital Ground (DGND)
                • 39 Not Connected (NC)
                • 310 Analog Negative Voltage (V-)
                • 311 Potentiometer Terminal B
                • 312 Potentiometer Wiper (W) Terminal
                • 313 Potentiometer Terminal A
                • 314 Analog Positive Voltage (V+)
                • 315 Exposed Pad (EP)
                  • 40 Functional Overview
                    • 41 Operating Voltage Range
                      • FIGURE 4-1 Power-On Sequences
                      • FIGURE 4-2 Voltage Ranges
                        • 42 PORBOR Operation
                          • TABLE 4-1 Wiper Pin State based on POR Conditions
                          • TABLE 4-2 Default PORBOR Wiper Register Setting (digital)
                          • TABLE 4-3 Default PORBOR Wiper Setting (Analog)
                          • FIGURE 4-3 DGND VL V+ and V- Signal Waveform Examples
                          • TABLE 4-4 Wiper Pin State based on BOR Conditions
                          • TABLE 4-5 Device functionality at each VL Region
                          • FIGURE 4-4 Power-up and Brown-out - V+V- at Normal Operating Voltage
                            • 43 Control Module
                              • FIGURE 4-5 Hardware Shutdown Resistor Network Configuration
                              • FIGURE 4-6 R0HW Bit and SHDN Pin Interaction
                              • FIGURE 4-7 WLAT Interaction with Wiper During Serial Communication ndash (SPI Mode 11)
                                • 44 Memory Map
                                  • TABLE 4-6 Wiper POR Standard Settings
                                  • TABLE 4-7 Memory Map and the Supported Commands
                                  • Register 4-1 TCON0 Bits(1)
                                      • 50 Resistor Network
                                        • FIGURE 5-1 Resistor Block Diagram
                                        • 51 Resistor Ladder Module
                                          • TABLE 5-1 Example Step Resistances (RS) Calculations
                                            • 52 Wiper
                                              • TABLE 5-2 Volatile Wiper Value vs Wiper Position
                                              • FIGURE 5-2 RW Resistance Vs RAB Wiper Current (IW) Temperature and Wiper Code
                                                • 53 Terminal Currents
                                                  • TABLE 5-3 Terminal (Wiper) Current and Wiper Settings (RW = RFS = RZS = 0W)
                                                  • FIGURE 5-3 Maximum IBW Vs Wiper Code ndash 5 kW
                                                  • FIGURE 5-4 Maximum IBW Vs Wiper Code ndash 10 kW
                                                  • FIGURE 5-5 Maximum IBW Vs Wiper Code ndash 50 kW
                                                  • FIGURE 5-6 Maximum IBW Vs Wiper Code ndash 100 kW
                                                  • FIGURE 5-7 Maximum VBW Vs Wiper Code (5 kW and 10 kW devices)
                                                  • TABLE 5-4 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ ndash V- = 36V 5 kW and 10 kW devices
                                                  • TABLE 5-5 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 50 kW devices
                                                  • TABLE 5-6 Max VBW at each Wiper Code (RW = RFS = RZS = 0W) for V+ - V- = 36V 100 kW devices
                                                    • 54 Variable Resistor (Rheostat)
                                                      • FIGURE 5-8 Rheostat Configuration
                                                        • 55 Analog Circuitry Power Requirements
                                                          • FIGURE 5-9 Analog Circuitry Voltage Ranges
                                                            • 56 Resistor Characteristics
                                                            • 57 Shutdown Control
                                                              • FIGURE 5-10 Hardware Shutdown Resistor Network Configuration
                                                              • FIGURE 5-11 Resistor Network Shutdown State (R0HW = 0)
                                                              • FIGURE 5-12 R0HW bit and SHDN pin Interaction
                                                                  • 60 Serial Interface (SPI)
                                                                    • FIGURE 6-1 Typical SPI Interface Block Diagram
                                                                    • 61 SDI SDO SCK and CS Operation
                                                                      • TABLE 6-1 SCK Frequency
                                                                        • 62 The SPI Modes
                                                                        • 63 SPI Waveforms
                                                                        • 64 Daisy Chaining
                                                                          • FIGURE 6-2 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 11)
                                                                          • FIGURE 6-3 16-Bit Commands (Write Read) ndash SPI Waveform (Mode 00)
                                                                          • FIGURE 6-4 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 11)
                                                                          • FIGURE 6-5 8-Bit Commands (Increment Decrement) ndash SPI Waveform with PIC MCU (Mode 00)
                                                                              • 70 Device Commands
                                                                                • TABLE 7-1 Commands
                                                                                • 71 Command Format
                                                                                  • FIGURE 7-1 General SPI Command Formats
                                                                                  • TABLE 7-2 Memory Map and the Supported Commands
                                                                                  • TABLE 7-3 Command Error Bit
                                                                                  • Aborting a Transmission
                                                                                    • 72 Write Data
                                                                                      • FIGURE 7-2 Write Command ndash SDI and SDO States
                                                                                      • FIGURE 7-3 Continuous Write Sequence
                                                                                        • 73 Read Data
                                                                                          • FIGURE 7-4 Read Command ndash SDI and SDO States
                                                                                          • FIGURE 7-5 Continuous Read Sequence
                                                                                            • 74 Increment Wiper
                                                                                              • FIGURE 7-6 Increment Command ndash SDI and SDO States
                                                                                              • TABLE 7-4 Increment operation vs Volatile Wiper Value
                                                                                              • FIGURE 7-7 Continuous Increment Command ndash SDI and SDO States
                                                                                                • 75 Decrement Wiper
                                                                                                  • FIGURE 7-8 Decrement Command ndash SDI and SDO States
                                                                                                  • TABLE 7-5 Decrement operation vs Volatile Wiper Value
                                                                                                  • FIGURE 7-9 Continuous Decrement Command ndash SDI and SDO States
                                                                                                      • 80 Applications Examples
                                                                                                        • 81 Split Rail Applications
                                                                                                          • FIGURE 8-1 Example Split Rail System
                                                                                                          • TABLE 8-1 MCP41HVX1 VL Voltage based on Microcontroller VOH
                                                                                                          • FIGURE 8-2 Example PICreg Microcontroller VOH Characterization Graph (VDD = 18V)
                                                                                                            • 82 Using Shutdown Modes
                                                                                                              • FIGURE 8-3 Example Application Circuit using Terminal Disconnects
                                                                                                                • 83 High-Voltage DAC
                                                                                                                  • FIGURE 8-4 High-Voltage DAC
                                                                                                                    • 84 Variable Gain Instrumentation Amplifier
                                                                                                                      • FIGURE 8-5 Variable Gain Instrumentation Amplifier for Data Acquisition System
                                                                                                                        • 85 Audio Volume Control
                                                                                                                          • FIGURE 8-6 Audio Volume Control
                                                                                                                          • FIGURE 8-7 Referenced Voltage Crossing Detect
                                                                                                                            • 86 Programmable Power Supply
                                                                                                                              • FIGURE 8-8 Programmable Power Supply
                                                                                                                                • 87 Programmable Bidirectional Current Source
                                                                                                                                  • FIGURE 8-9 Programmable Bidirectional Current Source
                                                                                                                                    • 88 LCD Contrast Control
                                                                                                                                      • FIGURE 8-10 Programmable Contrast Control
                                                                                                                                        • 89 Serial Interface Communication Times
                                                                                                                                          • TABLE 8-2 Serial Interface TimesFrequencies(1)
                                                                                                                                            • 810 Implementing Log Steps with a Linear Digital Potentiometer
                                                                                                                                              • FIGURE 8-11 Signal Attenuation Block Diagram ndash Ground Referenced
                                                                                                                                              • TABLE 8-3 Linear to Log Attenuation for 8-bit Digital Potentiometers
                                                                                                                                                • 811 Design Considerations
                                                                                                                                                  • FIGURE 8-12 Typical Microcontroller Connections
                                                                                                                                                  • TABLE 8-4 Package Footprint (1)
                                                                                                                                                  • TABLE 8-5 RAB Power Dissipation
                                                                                                                                                  • TABLE 8-6 RBW Power Dissipation
                                                                                                                                                      • 90 Device Options
                                                                                                                                                        • 91 Standard Options
                                                                                                                                                          • TABLE 9-1 Default PORBOR Wiper Setting Selection
                                                                                                                                                            • 92 Custom Options
                                                                                                                                                              • 100 Development support
                                                                                                                                                                • 101 Development Tools
                                                                                                                                                                • 102 Technical Documentation
                                                                                                                                                                  • TABLE 10-1 Development Tools
                                                                                                                                                                  • TABLE 10-2 Technical Documentation
                                                                                                                                                                  • FIGURE 10-1 Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV
                                                                                                                                                                  • FIGURE 10-2 Digital Potentiometer Evaluation Board Circuit Using SOIC14EV
                                                                                                                                                                      • 110 Packaging Information
                                                                                                                                                                        • 111 Package Marking Information
                                                                                                                                                                          • Appendix A Revision History
                                                                                                                                                                          • Appendix B Terminology
                                                                                                                                                                            • B1 Potentiometer (Voltage Divider)
                                                                                                                                                                              • FIGURE B-1 Potentiometer Configuration
                                                                                                                                                                                • B2 Rheostat (Variable Resistor)
                                                                                                                                                                                  • FIGURE B-2 Rheostat Configuration
                                                                                                                                                                                    • B3 Resolution
                                                                                                                                                                                    • B4 Step Resistance (RS)
                                                                                                                                                                                    • B5 Wiper Resistance
                                                                                                                                                                                    • B6 RZS Resistance
                                                                                                                                                                                    • B7 RFS Resistance
                                                                                                                                                                                    • B8 Least Significant Bit (LSb)
                                                                                                                                                                                    • B9 Monotonic Operation
                                                                                                                                                                                      • FIGURE B-3 Theoretical VW Output vs Code (Monotonic Operation)
                                                                                                                                                                                      • FIGURE B-4 Theoretical RBW Output vs Code (Monotonic Operation)
                                                                                                                                                                                        • B10 Full-Scale Error (EFS)
                                                                                                                                                                                          • FIGURE B-5 Full-Scale Error Example
                                                                                                                                                                                            • B11 Zero-Scale Error (EZS)
                                                                                                                                                                                              • FIGURE B-6 ZERO-Scale Error Example
                                                                                                                                                                                                • B12 Integral Nonlinearity (P-INL) Potentiometer Configuration
                                                                                                                                                                                                  • FIGURE B-7 P-INL Accuracy
                                                                                                                                                                                                    • B13 Differential Nonlinearity (P-DNL) Potentiometer Configuration
                                                                                                                                                                                                      • FIGURE B-8 P-DNL Accuracy
                                                                                                                                                                                                        • B14 Integral Nonlinearity (R-INL) Rheostat Configuration
                                                                                                                                                                                                          • FIGURE B-9 R-INL Accuracy
                                                                                                                                                                                                            • B15 Differential Nonlinearity (R-DNL) Rheostat Configuration
                                                                                                                                                                                                              • FIGURE B-10 R-DNL Accuracy
                                                                                                                                                                                                                • B16 Total Unadjusted Error (ET)
                                                                                                                                                                                                                • B17 Settling Time
                                                                                                                                                                                                                • B18 Major-Code Transition Glitch
                                                                                                                                                                                                                • B19 Digital Feedthrough
                                                                                                                                                                                                                • B20 Power-Supply Sensitivity (PSS)
                                                                                                                                                                                                                • B21 Power-Supply Rejection Ratio (PSRR)
                                                                                                                                                                                                                • B22 Ratiometric Temperature Coefficient
                                                                                                                                                                                                                • B23 Absolute Temperature Coefficient
                                                                                                                                                                                                                • B24 -3 dB Bandwidth
                                                                                                                                                                                                                • B25 Resistor Noise Density (eN_WB)
                                                                                                                                                                                                                  • Product Identification System
                                                                                                                                                                                                                  • Trademarks13
                                                                                                                                                                                                                  • Worldwide Sales and Service
Page 12: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 13: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 14: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 15: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 16: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 17: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 18: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 19: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 20: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 21: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 22: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 23: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 24: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 25: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 26: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 27: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 28: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 29: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 30: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 31: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 32: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 33: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 34: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 35: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 36: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 37: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 38: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 39: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 40: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 41: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 42: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 43: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 44: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 45: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 46: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 47: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 48: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 49: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 50: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 51: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 52: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 53: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 54: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 55: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 56: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 57: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 58: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 59: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 60: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 61: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 62: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 63: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 64: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 65: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 66: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 67: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 68: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 69: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 70: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 71: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 72: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 73: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 74: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 75: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 76: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 77: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 78: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 79: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 80: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 81: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 82: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 83: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 84: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 85: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 86: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 87: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 88: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 89: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 90: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 91: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND
Page 92: file.elecfans.com · 2019. 7. 31. · 2013-2015 Microchip Technology Inc. DS20005207B-page 1 MCP41HVX1 Features • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND