Figure 4–1 Application of commutative law of addition. Thomas L. Floyd Digital Fundamentals, 9e...

Figure 4–1 Application of commutative law of addition.

Thomas L. FloydDigital Fundamentals, 9e

Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

Figure 4–2 Application of commutative law of multiplication.




Figure 4–3 Application of associative law of addition. Open file F04-03 to verify.




Figure 4–4 Application of associative law of multiplication. Open file F04-04 to verify.




Figure 4–5 Application of distributive law. Open file F04-05 to verify.




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Figure 4–15 Gate equivalencies and the corresponding truth tables that illustrate DeMorgan’s theorems. Notice the equality of the two output columns in each table. This shows that the equivalent gates perform the same logic function.




Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.




Figure 4–17 Gate circuits for Example 4–8. Open file F04-17 to verify equivalency.




Figure 4–18 Implementation of the SOP expression AB + BCD + AC.




Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.




Figure 4–20 Implementation of the POS expression (A + B)(B + C + D)(A + C).




Figure 4–21 A 3-variable Karnaugh map showing product terms.




Figure 4–22 A 4-variable Karnaugh map.




Figure 4–23 Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.




Figure 4–24 Example of mapping a standard SOP expression.




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Figure 4–35 Example of mapping directly from a truth table to a Karnaugh map.




Figure 4–36 Example of the use of “don’t care” conditions to simplify an expression.




Figure 4–37 Example of mapping a standard POS expression.




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Figure 4–42 A 5-variable Karnaugh map.




Figure 4–43 Illustration of groupings of 1s in adjacent cells of a 5-variable map.




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Figure 4–45 A VHDL program for a 2-input AND gate.




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Figure 4–47 Seven-segment display format showing arrangement of segments.




Figure 4–48 Display of decimal digits with a 7-segment device.




Figure 4–49 Arrangements of 7-segment LED displays.




Figure 4–50 Block diagram of 7-segment logic and display.




Figure 4–51 Karnaugh map minimization of the segment-a logic expression.




Figure 4–52 The minimum logic implementation for segment a of the 7-segment display.




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Figure 4–1 Application of commutative law of addition. Thomas L. Floyd Digital Fundamentals, 9e...

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