Fiber Channel Video Controller Mid-Project Review Tsachy Kapchitz & Michael Grinkrug Super.: Alex...
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Transcript of Fiber Channel Video Controller Mid-Project Review Tsachy Kapchitz & Michael Grinkrug Super.: Alex...
Fiber Channel Video ControllerMid-Project Review
Tsachy Kapchitz & Michael Grinkrug
Super.: Alex Gurovich
Technion Digital Lab, Elbit Systems
Project Goals
• Design a controller that receives FC traffic from an external receiver and passes to memory only video data directed to it.
Block Diagram
• Input:– HP Receiver
• Output:– SRAM / LCD
• Interface:– Config. Params
(address, video params etc.)
– Status Register
f/2
f
S I Tabley ns ft oe rm m a t i o n
SRAM
Dat
a [3
1:0]
Addr [XX:0]
Con
tain
er_D
ata
[31:
0]D
ata
[31:
0]
CO
M_W
RX
[7:0
]
RX
[15:
8]
RC
LK
CO
M_D
ET
BC
Val
id_C
ont_
Dat
a_R
eady
M EM O RYUNIT
CO N TAIN ERCO N TRO LLER
FRAM ECO N TRO LLER
IN PU TU N IT
New
_Con
tain
er
WE
f/2 C lock
BE
set_next_addr
set_new_object
F
f/2
Index[15:0]
G et_Index
Ancillary_Inside
Block
Resolution
New
StatusInterface
C on ta ine r_C on f_R eg is te r
C on ta ine r_S ta tus_R eg is te r
F ram e_C on f_R eg is te r
F ram e_S ta tus_R eg is te r
Conf_Stat
ConfigureInterface
Input Unit
• Functionality:– Get data [words], comma
and clock from HP receiver
– Combine the data into DW and pass to Frame Controller
– Generate clock of half the frequency of the clock provided by HP receiver
– Pass COM_DET signal with the relevant DW
• Input: (from HP receiver)– Data [15:0]
– COM_DET signal
– Clock (RBC)
• Output: (to Frame Controller)– Data [31:0]
– Comma signal
– Clock (half the frequency of RBC)
Input Unit - uArch
0
1
LD0 = 1LD1 = 0
com m a#LD0 = 0LD1 = 1
commaLD0 = 1LD1 = 0
To Fram e C ontro lle r D ata [31 :0 ] , C om m a
From H P R ece iver D ata [15 :0 ] , C om m a
D1 D0 C om m a_Extender
iu_ fc_com m a
com m a
Rx [15:0]
LD 1 LD 0
rclk
gb
l_rs
t
iu_ fc_data [31 :0 ]
Com m a_Extender
Input Unit - clock generation
R B C 0 (c lockfrom H P
R ece ive r)
G ene ra tedc lock fo r the
in te rna l b locks
'1 '
Reset
G enerated C lock
RBC0
• This clock (f/2) will be the operating clock of the controller (Frame / Container Controllers)
• Memory Unit (address placement and SRAM / LCD interface) will work at a different frequency (a bit higher)
Input Unit - Assumptions
• HP Receiver operates in 2-Bytes per clock mode (not Ping-Pong)
• FC frames are DW aligned, so comma always will be passed in parallel with SOF / EOF
• The data from HP is in 8 bits per Byte format (after 10 to 8 conversion)
Frame Controller
• Functionality:– Receive data from Input
Unit by DW
– Analyze the data on FC Header level
– Pass the relevant payload to Container Controller
– Generate FC frame status according to internal state in order to know the cause of the problem
• Input: (from Input Unit)– Data [31:0]– Clock (half of RBC)– Comma signal– Configuration registers
(DID etc. from ConfStat)
• Output: (to Container Controller)– Data [31:0]– Valid + BC– New_Container– Frame Status Register
Frame Controller - functionalityS O F = S O Fn4
D_ID M atch
R _C T L[7 :4 ] = V ideo
Yes
Yes
TYP E = V en.U n ique
Yes
Sequence Analyse
S E Q _ID = P rev_S E Q _ ID
S E Q _C N T = 0
SEQ_CNT =Prev_SEQ_CNT+1
Yes
No
N ew _C on t_S igna lP rev_S E Q _ ID := S E Q _ ID
Yes
Transfer PayloadTo C ontainer C ontro ller
Prev_SEQ _C N T := SEQ _C N T
Yes
Yes
Dis
ca
rd
No
No
No
No
No
No
Yes
Frame Controller - Block Diagram
• Frame header Analyzer - main FSM, that parses FC frame header fields
• Sequence Follower - figures the next expected sequence num. and sequence count
• CRC is only compared and OK/NOK bit set in status register
• Suspender - FIFO of depth 2 that suspends the data in order to get the end of the frame (CRC)
Fram e HeaderAnalyzer
FSM
S equence Fo llowerFS M
fc_data[31:0 ]
fc_com m a
fc_newcont
S uspender
fc_cc_data[31:0]
Frame Controller
fc_check_seq
fc_seq_det
iu_ fc_data[31:0 ]
iu_ fc_com m a
E O F & C R CC om parator
fc_CS_set_EOF
fc_aux_da ta(C R C bus)
fc_CS_set_CRC
con f_C R C
con f_E O F
con f_ven_un ique
con f_d id
con f_video
con f_S O F
Byte_fillextract
fc_byte_fill# fc_va lid_4con t
fc_cc_bcfc_cc_va l
fc_cc_new con t
fc_ fr_s ta tus_ rdyRSFFfc_s t_ rd_ rs t
R
S
fc_CS_set_SOF
fc_CS_set_RCTL
fc_CS_set_DID
fc_CS_set_TYPE
fc_CS_set_SEQ
ended_well
fc_load_bf
Frame Controller
- uArchFrame
Header Analyzer
W ait_For_SOF
Check_SOF_EOF
fc_sof_det#, fc_com m a#IF ignr_status_rdy# fc_fr_status_rdyELSE stop_ignr_st_rdy
fc_com m a
Check_RCTL_ D IDIF fc_rctl_video fc_CS_set_RCTL;IF fc_did_our fc_CS_set_D ID
dum m y
Check_Type
Check_SEQ
W ait_For_
Payload2
W ait_ For_EOF _IF fc_eof_det ended_well
fc_com m afc_ fr_s ta tus_ rdy
fc_so f_de t, fc_com m a#fc_C S _se t_S O F
fc_com m a#fc_ load_b f
fc_ rc tl_v ideo ,fc_d id_ou r,fc_com m a#
fc_ven_un ique# , fc_com m a#
fc_ fr_s ta tus_ rdy non_m atch_st
fc_com m afc_ fr_s ta tus_ rdy
fc_ven_un ique , fc_com m a#fc_check_seqfc_C S _se t_TY P E
good_seq# , fc_com m a#fc_ fr_s ta tus_ rdynon_m atch_s t
fc_com m afc_ fr_s ta tus_ rdy
good_seq , fc_com m a#fc_C S _se t_S E Q
fc_com m a#
fc_com m afc_ fr_s ta tus_ rdy
fc_com m a#
fc_com m afc_ fr_s ta tus_ rdy
fc_com m afc_ fr_s ta tus_ rdy
fc_com m a#fc_valid4cont
fc_com m a
W ait_For_
Payload1
fc_com m a#
fc_com m afc_ fr_s ta tus_ rdy
(fc_ rc tl_v ideo o r fc_d id_ou r)# , fc_com m a#fc_ fr_s ta tus_ rdy; non_m atch_s t
Frame Controller - uArch
Sequence Follower
• New_container is a pulse that accompanies the first DW of container header
W A IT_F O R _N E W_C O N TA IN E R
(fc_check_seq=0 ) o r(fc_check_seq=1 andseq_cn t_ze ro=0 )
G E TTIN G _C O N TAIN E R
N E W _C O N TA IN ER _S TA R T
fc_check_seq=1 andseq_cnt_next=1 andsam e_seq_id=1fetch_seq_cntfc_seq_det
(fc_check_seq=1 ) and((seq_cn t_ze ro=1 and
sam e_seq_ id=0 ) o r(seq_cn t_next=0 andseq_cn t_ze ro=1 and
sam e_seq_ id=1 ))fe tch_seq_ id
fe tch_seq_cn tfc_seq_de tfc_new con t
(fc_check_seq=1 ) and((seq_cn t_next=0 and seq_cn t_ze ro= 0) o r
(seq_cn t_next=0 and seq_cn t_ze ro=1 and sam e_seq_ id=1 ) o r(seq_cn t_next=1 and seq_cn t_ze ro=0 and sam e_seq_ id=0 ))
fc_check_seq=1 and seq_cn t_ze ro=1fe tch_seq_ id
fe tch_seq_cn tfc_seq_de t
fc_new _con t
fc_check_seq=1 and seq_cnt_next=1 and sam e_seq_id=0fetch_seq_id
fetch_seq_cntfc_seq_detfc_newcont
fc_check_seq=1 and seq_cn t_next=1 and sam e_seq_ id=1fe tch_seq_cn t
fc_seq_de t
(fc_check_seq=1 ) and((seq_cn t_ze ro=0 and
seq_cn t_next= 0 ) o r(seq_cn t_next=1 andseq_cn t_ze ro=0 and
sam e_seq_ id=0 ))
fc_data[31:24]
fe tch_seq_ id
seq [7:0]
fc_data[15:0]
fe tch_seq_cn t
cnt [7:0]
LOGIC
fc_data[31 :0 ]
cnt[15 :0 ]
seq[7 :0 ]
seq_cnt_zero
seq_cnt_zero
seq_cnt_next
sam e_seq_ id
Frame Controller - uArchSuspender
• BC :– 11 - DW
– 10 - 3 Bytes
– 01 - 2 Bytes
– 00 - 1 Byte
– @comma - #byte_fill
fc_cc_da ta
fc_aux_da ta
fc_va lid_4con t fc_new con tfc_da ta [31 :0 ]
'11' fc_byte_fill#
fc_com m a
To CRC Com parator
0 1
fc_cc_va l fc_cc_bcfc_cc_new con t
Frame Controller - Assumptions
• Sequence on FC level 1 video container
• Single sequence at a time (one video stream)
• The link is FIFO (no surpassing frames)
• Point to point connection (single sender)
• If an error on FC frame level occurs - current sequence will be discarded (thus current video frame will be partially lost)
• Upon CRC error only, the data will be passed through and an appropriate status will be generated
Frame Controller -Testing Methodology
• Frame Controller:– C program that generates a text file with FC frames
• Parameters to the program: (some are randomized to increase test coverage)
– Num. of sequences
– Max num. of frames per sequence
– Frame size range (low & high limits)
• FC payload is a sequential data, that will be later changed to “FC Containers”
– VHDL test-bench that reads an input file (text) and “simulates” HP-receiver using that input
Container Controller
• Functionality:– Get container from
Frame Controller and write video objects to memory using an appropriate method, according to video system (with help of Memory Unit)
– Write ancillary object to a separate memory
• Input: (from Frame Controller)– Data [31:0]
– BC
– Valid
– New_Container
– Memory Unit interface
• Output: (to Memory Unit)– SRAM interface
– Memory Unit interface
Container Header
Container Controller -
Block Diagram
H eaderA na lyzer
O b jectsIn fo rm ation
O bjectsE xtracto r
A ligner
oe_oi_ctrl
data
[31
:0]
valid
bc
new
_con
tain
er
s ize_offset [63:0]
data
[31
:0]
valid
bc
new
_con
tain
er
data
[31
:0]
valid
be1
new
_o
bj
data
[31
:0]
we
be
get_index
ancillary_inside
index[15:0]
oi_oe_data[31:0]
block
set_next_addr
be2
C onta inerC ontro ller
set_new_object
Me
mo
ry U
nit
SRAM
new_container
resolution
extr
act
load_size_offset
init
FIFO
W ait fo rnew
con ta ine r
S k ip toob jec t
0
C heckanc illa ry
ob jec ts ize
Loadanc illa ry
ob jec ts ize_o ffse t
S k ip toob jec t 2
C heckob jec t 2
s ize
Loadob jec t 2
s ize_o ffse t
S k ip toob jec t 3
C heckob jec t 3
s ize
Loadob jec t 3
s ize_o ffse t
F e tchindex
ifTY P E =10h
new_container
DW _offset = 14
TYPE = 10h
size > 0load_size_offset
size > 0load_size_offset
.extract
new_container#init = 0
DW _offset != 7
DW _offset = 18
DW _offset != 14
DW _offset = 7size > 0
load_size_offset
size = 0
TYPE != 10h
size = 0
F etchindex
ifTY P E =10h
size > 0load_size_offset
TYPE != 10h
size = 0
Container Controller - Header Analyzer
Container Controller -Header Analyzer (cont.)
• Data flows through the block and relevant fields are checked and loaded into Object Information registers
• Objects size is loaded into a “temp” register and transferred together with offset
Data
SIZE
Object Info
Frame Contrl.
Obj. Extractor
Container Controller - Objects Information
rs t
rs t
rs t
in it
size
_off
set
fe tch_ob j_ in fo
load1
load2
load3ld
ld
ld
1
10
0
Mux_1
Mux_2
Mux_3
load_s ize_o ffse t#
load_s ize_o ffse t#
load_s ize_o ffse t#
load_s ize_o ffse tload1
load_s ize_o ffse tload2
anystate
Mux_1
in it#
Container Controller - Object Extractor
O bject Extractor
O bjects In fo
H eader Analyzer
valid
new
bc
offse t2 size2
Data
Control
offse t1 size1
valid
new
BE
splt
Aligner
b lock
O bjectE xtractor
FS M
data
fetc
h_
ob
j_in
fo
Container Controller - Object Extractor FSM
wait_ for_valid_ in fo
wait_ for_object
(cnt>=offset1+1) &(cnt>=offset1+size1+1)&(size2=0)pass
cnt<offset1+1
E xtract_ob ject
(cnt>=offset1+1)&(cnt<offset1+size1+1)pass
(cn t>= o ffse t1+s ize1+1)& (s ize2=0 o r(o ffse t2+1 < cn t-bc )pass
cnt < offset1+size1+1pass
(cnt>=offset1+size1+1)&(cnt-bc<=offset2+1<=cnt)&(size2!=0))pass, split, fetch_bj_info
A nyS ta tewait_ for_valid_ in fo
block
extract# or b lock
(cnt>=offset1+size1+1)&(size2!=0)&(cnt>=offset2+1)passfetch_obj_info
(cnt>=offset1+1)&(cnt>=offset1+size1+1)&(size2!=0)&(cnt>=offset2+1)passsplitfetch_obj_info
(cnt>=offset1+1)&(cnt>=offset1+size1+1)&(size2!=0)&(cnt<_offset2+1)pass
extrac t .fe tch_ob j_ in fo
Container Controller -
Aligner0 1
23
__________aligner_load
new`
new`
new`
Counter
'00'
== resolution
aligner_load
state
inc ld
data[31:0] be splitnew
new '
vld sp
data[31:0] be[3:0]we
set_next_addr
set_new_obj
Mem
ory
Un
it
Object Extractor
SRAM
Aligner
ld ld ld
Container Controller -
Memory UnitV ideoSystem
Infrom ation
index
Ancilla ryIn form ationget_ index
ld
1
0
M em -U nitFSM
Addressing
se t_next_add r
ancillary_ ins ide
ob j_ended
write_ancillary
-interlaced / non-interlaced-num of pixels per line-num of lines per video fram e-resolution-bad system
bad_sys tem
reso lution
external_ in fo
external_ contro l
ExternalEnvironment
new
se t_new _ob j
address
b lock
SRAM
Head
er A
na
lyzer
Alig
ner
Ob
ject E
xtra
cto
r
Container Controller - Memory Unit FSM
IDLE
CHECK
W RITEOBJ_1
W RITEOBJ_2
W RITEANCILLARY
getindex#block
getindexancillary_ ins ide# &bad_system
ancillary_ ins ide# &bad_system #
ancillary_ ins ide
set_new_obj#write_ancillary
set_new_obj &bad_system #
set_new_obj &bad_system
obj_ended# &start_new_obj#
obj_ended |s tart_new_obj
obj_ended#
obj_ended
anystate
IDLE
new
Container Controller - Assumptions
• Memory Unit gets Index of the first valid (TYPE & Size) object
• @ interlaced mode - video field object• Single video stream
Backup