Fetch1

Fetch2

Fetch3

Decode

JSR BR LD STJMPRET

ANDADDNOT

LC3 Controller State Machine

Fetch1

Fetch2

Fetch3

Decode

JSR BR LD STJMPRET

ANDADDNOT

LC3 Controller State Machine

Fetch1

Fetch2

Fetch3

Decode

JSR BR LD STJMPRET

ANDADDNOT

LC3 Controller State Machine

Fetch1

Fetch2

Fetch3

Decode

All other instructions

JSR BR LD STJMPRET

ANDADDNOT

LC3 Controller State Machine

Verilog State Machine

Output forming Logic

Next State logic

State Registers

Next State Logic

Fetch 0

Fetch 1

Fetch 2

Decode

Decode

JMP

Opcode CS NS

xxxx 0000000001 0000000010

xxxx 0000000010 0000000100

xxxx 0000000100 0000001000

0000 0000001000 0000010000

0001 0000001000 0000100000

0101 0000001000 0000100000

1001 0000001000 0000100000

…

xxxx 0100000000 0000000001

xxxx 1000000000 0000000001

assign NS[1] = CS[0]assign NS[5] = CS[4] & (opcode = 0001 +…

Output Forming Logic

enaPC = CS[0] + CS[7] + CS[10]

enaALU = CS[5] & IR[15:12]==4’b0101

Verilog State Machine

• Two block state machine– One n-bit register where n is the number of

states• This clocks next_state through to current_state

– Combinational logic block • This determines value of next_state and control

signals

Use parameters

parameter Fetch0 = 10’b000000001;

parameter Fetch1 = 10’b000000010;

parameter Fetch2 = 10’b000000100;...

Combinational Logic Blockalways @(current_state)

begin(refer to inactive.tcl reset values)case(current_state)

Fetch0:begin

(refer to TCL file for fetch0);next_state <= Fetch1;

endFetch1:begin

(refer to TCL file for fetch1);next_state <= …;

end...(SomeInstruction):begin

if IR[6] = 1’b1:(somesignal) <= 1’b1;

else(somesignal) <= 1’b0;

endendcase

end