Features Brief Functional Description...1.2 Brief functional description The device E525.07 is a...

Glow Plug Control IC E525.07 Preliminary Information – Apr 24, 2017

Features• 4 gate drivers for external high-side power-NMOS:• PWM controlled gate output drive with integrated

charge pump• adjustable gate charge / discharge currents• Gate sequencing for minimum current ripple• MOS protection by gate-source voltage limitation

• Glow plug current sensing with overcurrent shut-off• Battery voltage measurement, overvoltage and

undervoltage shut-down, charge pump monitoring• Regulated 3.3V supply output• Sensing ground shift at glow plugs• RMS voltage regulation by observing VBAT and

glow plug ground shift for correction of duty cycle• Overheating shut-down integrated• Two-wire interface: Control-In PWM, Diagnosis

Output - Standard 8-bit diagnosis with 1 data frame/s or 3-byte Advanced diagnosis using UART type output

• Optional use of SPI for advanced diagnosis and control via µP, watchdog function with reset

Added value factors• Autonomous system for glow plug controls and

diagnosis using PWM-interface• Advanced diagnosis features for glow plug

assessment via SPI communication• Qualified according to AEC-Q100

Brief Functional DescriptionThe E525.07 is a control IC for up to 4 high-side power-NMOS typically driving glow plugs in Diesel engines. The load current is varied by PWM duty cycle modula-tion at the power-NMOS gates according to the require-ments determined by an engine management unit.

Advanced control and diagnosis features such as load current monitoring, battery-, supply-, and charge pump-voltage and temperature supervision are included. The load current is measured via the drain-source voltage drop at the power-NMOS transistors. Ground voltage sensing at the glow plugs to compensate for ground shifts is included also.

For communication with the engine control unit either a 2-wire PWM interface which can be operated in two modes (Standard or Advanced) is used, or a SPI com-munication interface for a micro processor is available.

Main application fields• Quick start Diesel engine controls• PTC heater controls

Ordering Information

Ordering-No.: TAmb range Package

E52507A77B -40 °C ...+125 °C QFN32L6

Application diagram (Example: diagnosis via UART)

SPI data interface(option)

VBAT(KL30)

CVCP

E525.07

GD1

SCLK

GNDD PGND CSN4 CSP4 GD4 CSN3

VBAT_SENSVCPVSVDDAVDDDCI

MOSI

MISO

CUR

RESB

CSB

OCTH

MSEL

VBATDIAG

CSP1

CSN1

GD2

CSP2

CSN2

GD3

CSP3

Plug 1

MPWR2

MPWR1

MPWR3

MPWR4

Supply Voltage(KL87 or KL30)

Command IN(PWM)

Diagnosis OUT(UART or Standard-Mode)

MSEL (mode select):Connect to GND or VDD

Plug 2

Plug 3

Plug 4

Cable connectionto glow plugs

RPU2

to VDD

CVS

CVBAT

CVDDA

CVBATS

RVBAT

TMS TMODE

RVBATS

RCSP/N

CCSP/N

RCSP/N

RCSP/N

RCSP/N

RCI

CCSP/N

RCSP/N

CCSP/N

CCSP/N

CKL30

CVDDD

RVDDD DVS

DDIAG

Figure 1: Application diagram

This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.

Elmos Semiconductor AG Data Sheet QM-No.: 25DS0168E.00


Recommended external device parameters

Table 1: Recommended external devices

component recommended value remarks

DVS reverse polarity protection diode at pin VS

CKL30 >= 10 µF / 50 V capacitor at KL30 (drains of power FETs)

CVS 4.7 µF / 50 V capacitor at pin VS

CVDDA 1 µF / 4 V capacitor at pin VDDA

CVDDD 100 nF capacitor at pin VDDD

CVBAT 100 nF capacitor at pin VBAT

CVBATS 10 nF capacitor at pin VBAT_SENS

CVCP 220 nF / 50 V charge pump storage capacitor between pins VCP and VBAT

M5 VDS_max = 40 VVGS_max = +- 20 VRDSon_max = 2.2 mOhmCiss_max = 26 nF

reverse polarity protection of glow plugs / switching transistors(optional - if required, not shown in applic-ation circuit)

MPWR1 ... MPWR4 VDS_max = 40 VVGS_max = +- 15 VRDSon_max = 10 mOhmCiss_max = 6.5 nF

glow plug switching transistor

RCUR 4.8 kOhm ...50 kOhm CUR pin to ground; gate charge / dis-charge current adjustment

DDIAG serial diode at pin DIAG

RCI 2.2 kOhm serial resistor at pin CI

RVBAT, RVBATS 330 Ohm serial resistors at pins VBAT and VBAT_SENS

RCSP/N 150 Ohm serial resistors at pins CSPx and CSNx(same value for CSPx and CSNx)

CCSP/N 22 nF capacitors at pins CSPx and CSNx

RVDDD <=24 Ohm resistor between pins VDDA and VDDD


Elmos Semiconductor AG Data Sheet QM-No.: 25DS0168E.00 2 / 48


1 Principle of operation

1.1 IC Architecture

1.1.1 Block Diagram

Figure 1.1.1-1: Simplified functional block diagram

1.2 Brief functional description

The device E525.07 is a versatile control IC for up to 4 high-side power-NMOS typically driving glow plugs in Dieselengines. The load current is varied by modulation of the output PWM duty cycle at the power-NMOS gates accord-ing to the requirements determined by an engine management unit.Control and diagnosis features such as load current monitoring, battery-, supply-, and charge pump- voltage and temperature supervision are included. The load current can be measured either by shunt resistors or the drain-source voltage drop at the power-NMOS transistors themselves. Constant glow plug RMS voltage regulation by adaptation of output PWM duty cycle can be chosen as one mode of glow plug drive control.A 2-wire interface using PWM input and synchronous diagnosis output is used for communication with the engine control unit. It can operate in two different modes, both at battery supply level. The "standard diagnosis" mode just permits access to basic diagnostic flags, while in "Advanced diagnosis" mode the DIAG output operates as a UARTthat allows to transmit more diagnosis data with higher transmission rate.Moreover a SPI interface is available for advanced control and diagnosis which can be used alternatively to the UART mode. This is a low voltage interface intended for communication with an on-board micro processor (µP), e.g. for handling protocols as LIN or CAN. If the SPI communication is used, no PWM needs to be applied at CI. The duty cycle request is sent directly instead via SPI to the IC. The diagnostic data are sent via SPI to the µP also rather than using the DIAG output. A watchdog function with reset output for the µP is integrated too and the regu-lated low voltage supply VDDA can be used to supply external components such as a µP.




2 Package and Pinout

2.1 Package Reference

The product is available in a Pb free, RoHS compliant, QFN32L6 plastic package with only about 49mm2 (0.076 square inch) footprint area. For dimension details refer to JEDEC standard MO-220-K (version VJJC-2).

The package comes with side- wall plating of the contact leads.

The device (packaged device only) is qualified according to IEC 86 part 2-20 for the following soldering profile:1. (200 5) °C, dwell time (50 5) s2. (260 5) °C, dwell time <10 s

2.2 Pin Description

Table 2.2-1: Pin Description

No Name Type Description

- EP Exposed Pad. Connection to copper ground plane on PCP for optimum heat dis-sipation.

1 SCLK D_I SPI clock input

2 RESB D_O reset output (for µP)

3 VDDD S low voltage supply input (3.3V; digital; connect bypass capacitor)

4 CUR A_I reference current input for gate charge / discharge setting

5 OCTH A_I over current threshold definition input

6 TMS D_I Pin for selection of overcurrent failure reset condition

7 MSEL D_I Pin for PWM control mode selection

8 TMODE D_I test control input (for supplier test only; internal pull down; connected to GND in application circuit)

9 VDDA S regulated low voltage supply output for internal and external use (3.3V; bypass capacitor connection)

10 PGND S negative supply (power ground)

11 VS HV_S main supply input (battery)

12 DIAG HV_D_O diagnostic output (open drain stage)

13 CI HV_D_I PWM Control Input

14 VBAT_SENS

HV_A_I battery voltage sense input

15 VBAT HV_S battery voltage supply

16 VCP HV_A_O charge pump output

17 GD4 HV_A_O gate driver output for external high-side power MOS, glow plug 4

18 CSN4 HV_A_I negative current sense input glow plug 4

19 CSP4 HV_A_I positive current sense input glow plug 4










No Name Type Description




29 GNDD S negative supply (ground digital)

30 CSB D_I SPI chip select (low active)

31 MOSI D_I serial data input

32 MISO D_O serial data output

Explanation of Types:A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage

ESD:More details concerning this topic are described in the "ESD" chapter.

2.3 Package Pinout

Figure 2.3-1: Package Pinout




3 Operating Conditions

3.1 Recommended Operating Conditions

The recommended operating conditions must not be exceeded in order to ensure proper functionality of the device.All parameters specified in the following sections refer to these recommended operating conditions if not otherwise stated.

• Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.• All voltages are referred to ground (0V).• Currents flowing into the circuit have positive values.• The first electrical potential connected to the IC must be PGND. (If not specified specify timing sequence of elec-

trical contacts.)

Table 3.1-1: Recommended Operating Conditions

No. Description Condition Symbol Min Typ Max Unit

1 Main supply voltage VVS 5 16 V

2 Supply voltage at pin VBAT VVBAT 5.5 16 V

3 External capacitor at pin VS CVS 4.7 µF

4 External capacitor at pin VBAT CVBAT 47 100 nF

5 External capacitor at pin VBAT_SENS CVBATS 10 nF

6 Series resistors at pins VBAT and VBAT_SENS

RVBAT 330 Ω

7 External ceramic capacitor at pin VDDA CVDDA 0.47 1 1.5 uF

8 ESR value of VDDA capacitor ESRC_VDDA 0.5 Ω

9 Charge pump storage capacitor CVCP 180 220 260 nF

10 PWM frequency at pin CI fCI 30.5 32 33.5 Hz

11 Rise time at pin CI tr,CI 100 µs

12 Fall time at pin CI tf,CI 100 µs

13 Current at CI pin in case of negative input voltage (ground shift between engine con-trol unit and IC)

VCI <0V ICI_neg -2 0 mA

14 Duty cycle at CI for glowing without spread-ing (standard diagnosis mode)

DCI= tCI,ON/tCI,per DCI_std 4.2 98 %

15 Duty cycle at CI for glowing with spreading (Advanced diagnosis mode)

DCI= tCI,ON/tCI,per DCI_adv 5 95 %

16 External series resistors at pins CSPx and CSNx1)

RCSN,CSP_ext 150 180 Ω

17 Resistance at CUR pin to ground RCUR 4.8 50 Ωk1) Due to different input currents at pins CSPx and CSNx these resistors cause a shift of the voltage difference VCSPx-VCSNx

3.2 Absolute Maximum Ratings

Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. Theseare stress ratings only; operation of the device at these or any other conditions beyond those listed in the opera-tional sections of this document is not implied. Exposure to absolute maximum rated conditions for extended peri-ods may affect device reliability.

All voltages referred to V(PGND): currents flowing into terminals are positive, those drawn out of a terminal are negative.




Table 3.2-1: Maximum Ratings

No. Description Condition Symbol Min Max Unit

1 Junction temperature TJ -40 150 °C

2 Ambient temperature chip packaged packaged: QFN32L6

TAMB -40 125 °C

3 Ambient temperature in operating lifetime ≤ 1000h in OLT, 2)

TAMB 125 140 °C

4 storage temperature 1) TSTG -40 125 °C

5 power dissipation TAMB ≤ 125°C PTOT 800 mW

6 voltage at digital pins CSB, MOSI, MISO, SCLK, RESB, MSEL, TMS

VDPIN -0.3 VVDDD

+0.3V

7 input current at digital pins CSB, MOSI, MISO, SCLK, RESB, MSEL, TMS

IDPIN -20 +20 mA

8 Main supply voltage VVS -0.3 28 V

9 Main supply voltage at load dump tld ≤ 400ms VVS,ld -0.3 45 V

10 Battery supply voltage VVBAT -0.3 28 V

11 Battery supply voltage at load dump tld ≤ 400ms VVBAT,ld -0.3 45 V

12 Voltage at pin VDDA VVDDA -0.3 3.6 V

13 Voltage at pin VDDD VVDDD -0.3 3.6 V

14 Current at pin VDDA (limited internally) IVDDA -60 +1 mA

15 Current at pin VDDD IVDDD -5 +5 mA

16 Voltage at charge pump pin VCP VVCP -0.3 45 V

17 CI pin input current ICI -10 1 mA

18 Maximum voltage at CI pin VCI 40 V

19 Voltage at pins CSPx and CSNx VCSNx -14 VVCP+0.3

V

20 Input current at pins CSPx and CSNx ICSNx -5 +5 mA

21 Voltage at pin OCTH VOCTH -0.3 VVDDA

+0.3V

22 Input current at pin OCTH IOCTH -5 +5 mA

23 Voltage at pin DIAG VDIAG -0.3 40 V

24 Input current at pin DIAG IDIAG -20 +20 mA

25 Voltage at pin CUR VCUR -0.3 VVDDA

+0.3V

26 Input current at pin CUR ICUR -5 +5 mA

27 Voltage at pins GDx VGDx -14 VVCP+0.3

V

28 Input current at pins GDx IGDx -15 +15 mA

1) Storage is not considering packing materials such as tapes, reels, dry packs, foils, etc. Please contact ELMOS for packing material specifications. Packaged devices before soldering: For moisture sensitive devices refer to JEDEC standard J-STD-033 for handling and using details. Storage at temperatures > 90 °C for more than 96h may affect the solderability of the devices.2) During operation lifetime (OLT) the device can be operated at elevated ambient temperatures above 125°C for a limited time. Operation times at lower ambient temperature may be added, of course. For a specific temperature profile in operating life, specific exposure times can be provided on demand by ELMOS.




4 Detailed Electrical Specification

4.1 Power Supply

Table 4.1-1: Main Supply Parameters


1 Supply current at VS pin in active mode IVDDA_ext = 0;IC active

IVS 3 5 mA

Table 4.1-2: VDD Supply Parameters


1 VDDA output voltage ≤-10mA IVDDA_ext ≤ 0(IVDDA = IVDDA_ext + IVDDD)

VVDDA 3.1 3.3 3.5 V

2 VDDA load regulation VVS= 5V, -10mA < IVDDA < -0.1mA,CVDDA= 1uF

∆VVDDA(LOAD) 10 80 mV

3 VDDA short-current limitation VVDDA=0V IVDDA(SC) 15 60 mA

Table 4.1-3: Battery Supply Parameters


1 Current at VBAT pin during power-down (VS below power-on-reset level or VS not supplied)

VVS ≤ 2.5V,VVBAT in recom-mended operat-ing range

IVBAT_pd 10 60 µA

2 Supply current at VBAT pin in active mode IC in active mode

IVBAT_act 3 4 mA

3 Input current of VBAT_SENS pin VVBAT_SENS < 16V IVBAT_SENS_act 100 150 µA

Table 4.1-4: Sleep Mode Supply Parameters


1 Sum of supply current at pins VS, VBAT and VBAT_SENS in sleep mode

VVS=VVBAT=12V; IC in sleep mode; IVDDA_ext = 0mA

IVS_VBAT_(SM) 40 80 µA

4.1.1 Charge Pump

Table 4.1.1-1: Charge pump parameters


1 Charge pump voltage above VVBAT IVCP = -80 µA≤8V VVBAT≤16V

Gate drivers off

VCP 9 10 14 V

2 Charge pump voltage above VVBAT IVCP = -80 µA≤5.5V VVBAT≤8V

Gate drivers off

VCP(vbat,low) 6 14 V

3 Charging current VVCP = VVBAT +6V -IVCP 80 µA





4 Time to charge storage capacitor CVCP to VVCP(UV)min

*)

CVCP = 220 nF tCP(on) 20 ms

5 Frequency of charge pump fCP 3.2 4 4.8 MHz

6 VCP clamping resistance to VBAT VVBAT> VVBAT_VCP_clamp

RVCP_clamp 1.7 2.5 Ωk

7 Voltage threshold at VBAT pin to activate the clamping between VBAT and VCP via RVCP_clamp

VBAT_VCP_clamp 21 24 27 V

*) Not tested in production

4.1.2 Voltage Monitoring

4.1.2.1 VDD Monitoring

Table 4.1.2.1-1: VDD monitoring parameters


1 Power-on-reset threshold (VDD falling) falling supply VVDDA(LOW) 2.3 2.7 V

2 POR hysteresis (difference of rising and falling threshold)*)

VVDDA(HYS) 0.18 0.3 V

3 Output low level at pin RESB IRESB=+2mA VRESB(LOW) 0.4 V

4 Voltage difference VVDDA-VVDDD as additionalpower-on-reset condition1)

VVDDA-VDDD(POR) 0.5 1.1 V

*) Not tested in production1) needed in case of loss of external connection VDDA-VDDD

4.1.2.2 VBAT monitoring

Table 4.1.2.2-1: VBAT monitoring parameters


1 Battery supply under voltage threshold1) falling supply VBAT(UV) 4.5 5 V

2 Under voltage detection hysteresis*) 2) rising supply VBAT(UV-HYS) 0.2 0.5 V

3 Battery supply over voltage threshold1) rising supply VBAT(OV) 16.5 17.5 V

4 Battery supply over voltage threshold hys-teresis*) 2)

falling supply VBAT(OV-HYS) 0.5 1 V

5 Open-load detection supply threshold3) VBAT(OL) 6 7.5 V

6 Battery supply debounce time4) tBAT(FIL) 1 2 ms

7 Battery supply "OFF" threshold1) falling supply VBAT(OFF) 1.8 2 2.2 V

8 Battery "OFF" detection hysteresis*) 2) rising supply VBAT(OFF-HYS) 0.2 0.5 V*) Not tested in production1) Indirect test during ADC measurement2) Defined by design3) Indirect test during ADC measurement; An open load event will be suppressed below this supply level4) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.1.2.3 VCP monitoring

Table 4.1.2.3-1: VCP monitoring parameters


1 Charge pump low threshold above VVBAT1) VCP(UV) 5 6 V

2 Charge pump low debounce time2) tCP(UV) 0.5 1 ms1) Indirect test during ADC measurement2) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part




4.2 Device Modes of Operation

Table 4.2-1: Parameters of device modes


1 Sleep mode timeout1) tTO(SM) 200 300 400 ms1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.2.1 Modes of PWM Control and Overcurrent Failure Reset

Table 4.2.1-1: Mode Selection Pin Parameters


1 Mode select input threshold VMSEL(thres) 1.0 2.0 V

4.3 PWM Control Input

4.3.1 Physical Interface: Pin CI

Table 4.3.1-1: PWM Control Input Electrical Parameters


1 Input high voltage relative to VVS VCI(OFF) / VVS 0.6

2 Input low voltage relative to VVS VCI(ON) / VVS 0.4

3 Input threshold voltage relative to VVS VCI(thres) / VVS 0.4 0.6

4 Hysteresis of input thresholds relative to VVS

*) 1)

VCI(hys) / VVS 0.05 0.1 0.15

5 Internal pull-up resistor RCI(PU) 40 55 70 Ωk

6 PWM timeout2) tCI(TO) 50 100 ms*) Not tested in production1) Defined by design2) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.3.2 Glow Control Input Detection

Table 4.3.2-1: CI Frequency Electrical Parameters


1 Minimum frequency at CI for glowing1) fCI(OFF.low) 20 29 Hz

2 Maximum frequency at CI for glowing1) fCI(OFF.high) 35 45 Hz1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.3.3 Duty Cycle without Spreading

Table 4.3.3-1: Duty Cycle Standard Electrical Parameters


1 Debounce filter time1) tCI(FIL) 100 150 200 µs

2 Minimum duty cycle at CI for glowing (standard mode)1)

DCI= tCI,ON/tCI,per DCI(OFF.low,std) 3.8 4 4.2 %

3 Maximum duty cycle at CI for glowing (standard mode)1)

DCI= tCI,ON/tCI,per DCI(OFF.high,std) 98 98.5 %

1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part




4.3.4 Duty Cycle with Spreading

Table 4.3.4-1: Duty Cycle Spreading Electrical Parameters


1 Minimum duty cycle at CI for glowing with spreading1)

DCI= tCI,ON/tCI,per DCI(OFF,low,adv) 4 5 %

2 Maximum duty cycle at CI for glowing with spreading1)

DCI= tCI,ON/tCI,per DCI(OFF,high,adv) 95 96 %

3 Resolution of duty cycle detection*) DCI(res) 0.1 %*) Not tested in production1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.4 Safety and Diagnosis

4.4.1 Open-Load on Glow Plug

Table 4.4.1-1: Open-load Parameters


1 Open-load detection threshold1) VVBAT ≤-2.5V VCSPx,CSNx ≤ VVBAT

VVBAT ≥ 7.5V

∆VOL 7 12 17 mV

2 Open-load debounce time2) tOL(FIL) 0.5 1.0 ms1) Indirect test during ADC measurement2) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.4.2 Glow Plug Current Monitoring

Table 4.4.2-1: Current Monitoring Parameters


1 Overcurrent threshold relative to VOCTH VVBAT-2.5V ≤VCSPx≤ VVBAT;

≤2.5V VCSNx≤ VVBAT;

≤0.24V VOCTH ≤VCUR

∆VOC(SH)_0 /VOCTH

0.7 0.8 0.9

2 Overcurrent threshold (small value of OCTH voltage) relative to VOCTH

VVBAT-2.5V ≤VCSPx≤ VVBAT;


≤0.1V VOCTH ≤0.24V

∆VOC(SH)_1 /VOCTH

0.8

3 Absolute deviation of overcurrent thresholdfrom its ideal value 0.8*VOCTH



≤0.1V VOCTH ≤0.24V

Abs_ERR -20 20 mV





4 Overcurrent threshold with not-connected OCTH pin


≤2.5V VCSNx≤ VVBAT;pin OCTH open

∆VOC(SH)_2 0.17 0.19 0.21 V

5 Overcurrent debounce time1) tOC(DEB) 30 80 µs

6 Failure masking time after GDx turned on1) tMASK 65 80 95 µs

7 Internal resistor from OCTH pin to ground ROCTH_GND 70 200 450 Ωk

8 Internal resistor from OCTH to CUR ROCTH_CUR 300 800 1800 Ωk1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

Table 4.4.2-2: Current Sense Input Parameters


1 Input current negative current sense inputs (CSNx)

≤6V VCSPx, VCSNx ≤ 16V

ICSN 150 µA

2 Input current positive current sense inputs (CSPx)

≤6V VCSPx. VCSNx ≤ 16V

ICSP 150 µA

3 Difference of input currents of positive and negative current sense input

≤6V VCSPx, VCSNx ≤ 16VVCSPx=VCSNx; gatedriver is switched-on

Idiff_CSP-CSN 30 µA

4 MOS switch failure threshold1) VCSN(TH) 2.5 2.9 V

5 Switch failure debounce time2) tCSN(FIL) 30 80 µs

6 Delay between FET shortcut measurementand switching-on the corresponding gate driver2)

tFSH 200 400 µs

1) Indirect test during ADC measurement2) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.4.3 Temperature Supervision

Table 4.4.3-1: Temperature Supervision Parameters


1 Thermal shutdown threshold (junction)*) TSD 140 170 °C

2 Thermal shutdown threshold hysteresis*) Thyst 10 °C*) Not tested in production

4.4.4 Diagnosis Output

Table 4.4.4-1: Diagnosis Output Electrical Parameters


1 Output low voltage IDIAG ≤ 7mA VDIAG(L) 1.0 V

2 Output current limitation IDIAG(LIM) 7 20 mA

3 Internal pull-up resistor RDIAG(PU) 30 50 65 Ωk




4.4.5 Advanced Diagnosis Mode

Table 4.4.5-1: DIAG generation parameters


1 Baud rate of diagnosis transmission at pin DIAG1)

no failure at CI pin

BRDIAG 32 fCI

2 Time between falling edge at pin CI and falling edge of start bit at pin DIAG1)

no change in fCI tCI,DIAG 100 200 µs

3 Relative error of DIAG baud rate*) ErrBR -1 1 %*) Not tested in production1) Defined digitally (multiple of oscillator clock), indirect test during scan path test of digital part

4.5 Ground Supervision

Table 4.5-1: ground supervision parameters


1 ground sense input voltage range*) 1) VCSNx(range) -2.9 2.9 V

2 maximum ground shift between glow plug ground and IC ground for power regulation2)

∆VGND(rec) 1.0 1.5 V

3 maximum allowed ground shift between glowplug ground and IC ground for glowing2)

∆VGND(glow) 1.8 2.5 V

4 hysteresis for returning to glow plug activa-tion after VGND(glow) was exceeded*) 1)

VCSNx(hys) 0.5 1 V

5 output current during ground sensing1) ICSNx 100 µA

6 Quantization LSB of glow plug ground shift*) 1) LSB(GPGND) 35 mV*) Not tested in production1) Defined by design. Not subject to production test2) Indirect test during ADC measurement

4.6 Glow Plug Assessment

Table 4.6-1: Glow Plug Assessment Parameters


1 Current sense voltage measurement full-scale range*) 1)

VVBAT ≤-1V VCSPx

≤ VVBAT ≤; 5.5V VVBAT ≤ 16V

dVCS 0.3 V

2 Quantization LSB of current sense voltage*) 1) 8 bit quantiza-tion

LSB(dVCS) 1.18 mV

3 Relative measurement error current sensing ≤0.1V dVCS ≤ 0.3V

ERR2_rel(dVCS) -8 +8 %

4 Absolute measurement error current sensing dVCS ≤ 0.1V ERR2_abs(dVCS) -8 +8 mV

5 Battery voltage represented by a value of 0xFF*) 1)

VCP > VCP(UV) VBAT(255) 18 V

6 Quantization LSB battery voltage sensing*) 1) 8 bit quantiza-tion

LSB(VBAT) 70.6 mV

7 VVBAT measurement error at TA=25°C TA= 25°C ERR(VBAT) -1.5 1.5 %

8 VVBAT measurement error in temperature range

ERR_temp(VBAT) -2.5 2.5 %

*) Not tested in production1) Defined by design




4.7 High Side Gate Control

Table 4.7-1: Gate Drivers Electrical Parameters


1 Gate driver ON voltage1) VCSNx=VVBAT ≥ 8V VGD(ON) VVBAT+9V

VVBAT +14V

2 Gate driver ON voltage1) VCSNx=VVBAT < 8V VGD(ON)_vbat,low VVBAT+6V

VVBAT +14V

3 Maximum gate charge current ICUR= -250µA3V<VGDx<VVCP-3V; 0V<VGDx-

CSNx<11V

-IGD(ON) 3 4 5 mA

4 Maximum gate discharge current ICUR= -250µA3V<VGDx<VVCP-3V; 0V<VGDx-

CSNx<11V

IGD(OFF) 3 4 5 mA

5 Current ratio |IGD/ICUR| ≤30µA |ICUR ≤| 250µA

MI(GD) 12 16 22

6 Gate driver OFF voltage above VCSNx IGDx ≤ 50µA, VCSNx ≥ 0V

VGD(OFF) 0.7 V

7 Gate driver OFF voltage above VCSNx duringnegative glow-plug ground shift

VCSNx < 0V VGD(OFF,SH) 0.9 V

8 Resistance between pins GDx and CSNx for passive clamping of gate and source terminals of external switch transistors

RGS 225 300 375 Ωk

9 Threshold of gate-source voltage differ-ence to switch the gate driver to High-Z state

VGS_max_th 12 13 14.75 V

1) indirect test via measurements of VVCP and VGDx drop

Table 4.7-2: Gate Driver Timing (GDx)


1 PWM output rate, using SPI communica-tion1)

Control input CI open (no PWM applied)

TGD(PWM) 28 31.25 35 ms

1) Timing defined in digital circuitry. Indirect test during scan path test of digital part

Table 4.7-3: Gate Current Setting Pin (CUR)


1 CUR output voltage |ICUR ≤| 250µA VCUR 1.13 1.2 1.27 V

2 CUR short current limitation VCUR = 0V ICUR(LIM) 0.28 0.75 mA




4.8 Power Regulation Mode

Table 4.8-1: RMS Regulation Electrical Parameters


1 Reference battery voltage*) 1) VBAT,0 12 V

2 Relative accuracy of power regulation at TA

= 25°C≤8V VVBAT ≤

16V,ΘCI ≥ 15%,VGPGND=0V,TA=25°C

εRMS,rel -1.5 1.5 %

3 Absolute accuracy of power regulation withlow VVBAT at TA=25°C

VVBAT ≤ 8V,ΘCI ≥ 15%,VGPGND=0V,TA=25°C

εRMS,abs -150 150 mV

4 Accuracy of power regulation in temperat-ure range

≤8V VVBAT ≤ 16V,ΘCI ≥ 15%,VGPGND=0V

εRMS,temp -2.5 2.5 %

*) Not tested in production1) Defined by design

4.9 SPI Interface and Digital Functions

Table 4.9-1: Digital port parameters


1 Input Low level of digital input pins relative to VVDD

VIN_LO / VVDD 0.3

2 Input High level of digital input pins relative to VVDD

VIN_HI / VVDD 0.7

3 Input threshold level of digital input pins rel-ative to VVDD

VIN(thres) / VVDD 0.3 0.7

4 Pull-up resistance at pin CSB RPU 90 130 170 Ωk

5 Pull-down resistance at pin MOSI, TMODE RPD 90 130 170 Ωk

6 Voltage difference between VVDDA and MISO output voltage High below

Iout = -2mA VOUT_HI 0.4 V

7 MISO output voltage Low Iout = 2mA VOUT_LO 0.4 V

4.9.1 Description of the SPI

Table 4.9.1-1: SPI electrical parameters


1 SPI clock frequency*) 1) fP_SCLK = 1/tP_SCLK fP_SCLK 4 4.4 MHz

2 time between rising edge of CSB and high impedance at MISO*) 1)

tMISO_Z 100 ns

3 MISO data valid time (time between rising edge of SCLK and MISO data valid)*) 1)

CMISO < 20pF tVALID 35 ns

4 time between falling CSB edge and first rising SCLK edge*) 1)

tLS1 50 ns





5 time between last falling SCLK edge and rising CSB edge*) 1)

tLS2 50 ns

6 inter byte time gap between last falling edge SCLK of a byte transmission and first rising edge SCLK of a subsequent byte within an SPI transfer*) 1)

tIBG 1 µs

7 MOSI setup time (time between MOSI datavalid and falling edge of SCLK)*) 1)

tSETUP 30 ns

8 MOSI hold time (time between falling edge of SCLK and MOSI data invalidation)*) 1)

tHOLD 20 ns

9 Time out for glow plug enable*) 1) tSPI(TO) 100 200 ms*) Not tested in production1) Defined by design. Not subject to production test




5 Functional Description

5.1 Power Supply

Main Supply VSThe main supply current of the E525.07 IC is drawn from pin VS. The supply voltage at pin VS is indirectly mon-itored for an undervoltage by surveillance of the regulated low voltage supply VDDA in order to• switch VBAT to high impedance with minimum current consumption from VBAT (sleep mode) and• disable the charge pump function at VCP.

Regulated Supply (VDDA, VDDD)The IC has an internal voltage regulator based on a bandgap reference voltage which supplies the internal low voltage blocks. This regulator is active in all operation modes.The low voltage supply is separated for analog (VDDA) and digital (VDDD) circuitry. Pin VDDA is the regulator out-put while pin VDDD is a supply input for the digital part. Both supplies shall be connected together externally and buffered with an external blocking capacitor at pin VDDA. This stabilized voltage may be used to supply external circuitry requiring a 3.3V supply with moderate current consumption, e.g. a microcontroller.

Internal digital blocks are supplied from pin VDDD, which must be connected to VDDA externally. An appropriate blocking capacitor must be connected to this pin.

Battery Supply (VBAT)The E525.07 IC has an additional supply input at pin VBAT. This auxiliary supply provides the power input to the internal charge pump.If the main supply at pin VS is so low that the regulated supply voltage VVDDA does not exceed the power-on threshold then the VBAT pin is set to a high impedance state. This ensures that the external power switches are kept off and a minimum current is consumed from VBAT (power down mode).

5.1.1 Charge Pump

An internal charge pump provides a voltage level higher than the battery supply voltage VBAT at pin VCP. The charge pump charges an external tank capacitor at VCP. This capacitor mainly provides the current to drive the gates of the external high-side power NMOS transistors.In case of very high VBAT voltages (VBAT>VBAT_VCP_clamp) or during sleep mode VCP is discharged to VBAT level via resistor RVCP_clamp.

5.1.2 Voltage Monitoring

5.1.2.1 VDD MonitoringThe regulated supply VDDA is supervised by a power-on reset circuit which generates a reset to the circuit control logic, if VDDA falls below the threshold VVDDA(LOW). Furthermore the voltage difference between the pins VDDA and VDDD is supervised to detect a missing external connection between these pins.

The power-on reset is available at pin RESB as an option to reset external devices, too. If operated with SPI com-munication, the reset output RESB is combined with the watchdog reset (see 5.9).

5.1.2.2 VBAT monitoringThe input pin VBAT_SENS is used to measure the battery voltage VVBAT. The measured value is used for the duty-cycle calculation in "power regulation mode" and for detecting battery undervoltage, overvoltage and battery-loss.

The battery voltage VVBAT is monitored in order to• switch off all glow plugs if the supply is lower than VBAT(UV) for at least tBAT(FIL) ("undervoltage") and deactivate the

charge pump during this event• switch off all glow plugs if the supply exceeds VBAT(OV) for at least tBAT(FIL) ("overvoltage") and deactivate the charge

pump during this event




• suppress any open-load diagnosis, if the supply is below VBAT(OL)

• detect a lost VBAT supply, if the supply is below VBAT(OFF)

The glow plugs are switched-on again if the corresponding switch-off condition disappears.

If VVBAT is lower than VBAT(UV) for at least tBAT(FIL), the charge pump will be disabled and the current drawn from the battery supply pin VBAT is reduced to nearly zero by switching the pin to high impedance. Moreover, all glow plugs are switched off and the undervoltage condition is signaled at bit 8 of the "Standard Diagnosis Protocol".

If VVBAT is lower than VBAT(OFF) for at least tBAT(FIL), battery supply loss is signaled additionally at bit 7 of the "Standard Diagnosis Protocol"

With supply pins VS, VBAT and VBAT_SENS at low, the IC cannot be (accidentally) supplied from the interface pins CI or DIAG.The failure detection for FETs and glow plugs is disabled as long as VBAT undervoltage is detected.

If VVBAT exceeds VBAT(OV) for at least tBAT(FIL), all glow plugs are switched off, the charge pump is disabled and a dia-gnosis information is sent to the motor control unit.

If the supply voltage VVBAT is below VBAT(OL) any open-load diagnosis is masked.

5.1.2.3 VCP monitoringIn order to avoid excessive power dissipation in the power NMOS transistors in case of too low charge pump voltage, the voltage at VCP is monitored and the glow plugs are switched-off if it is lower than VVCP(UV) for at least tVCP(FIL) ("charge pump low"). After a "charge pump low" event, the glow plugs remain switched-off even if the chargepump voltage increases above VCP(UV) until the glow plug channels are explicitly switched-on again by a correspond-ing control input via CI or the appropriate SPI command.

5.2 Device Modes of Operation

If no PWM is received at the CI pin (high level input = passive) and no SPI communication occurs for a time longer than the sleep mode time out tTO(SM), the IC enters sleep mode with a minimum current consumption from the supplyinputs VS and VBAT.The regulated supply remains active. Thus an external controller is continuously supplied.

On a falling edge at pin CI the IC transits to normal operation.The same happens, if the SPI is activated by an external controller. On start-up diagnosis data may be sent that describe the intermediate start-up state and are thus invalid for the system and must be neglected by the controller,e.g. the charge pump output will be low at the start command.After all control data have been delivered by the controller, the IC is ready for glowing after the charge pump voltage has reached its nominal value.

5.2.1 Modes of PWM Control and Overcurrent Failure Reset

The pins MSEL and TMS are used to set different device operating modes by connecting these pins to GND or to VDDA as shown in the table below.

• Pin MSEL is used to select the desired PWM control mode• Pin TMS determines the reset condition of overcurrent failures (details see chapter "Overcurrent Failure Count-

ing and Reset")




Table 5.2.1-1: Summary of operation modes

Pin MSEL Pin TMS Mode Description

Ground X RMS regulation ("power regulation mode")

VDDA X Direkt PWM mode (no RMS regulation)

X Ground Overcurrent failures are cleared in sleep mode (until failure counter has reached its limit of 250)

X VDDA Overcurrent failures are not cleared in sleep mode

In the "Direct PWM Mode" the duty cycle of the PWM control input signal at pin CI (or sent via SPI protocol) dir-ectly determines the duty cycle of the gate driver outputs (no RMS regulation).

In the "Power Regulation Mode" the duty cycle of the PWM control input determines the RMS voltage at the glow plugs. In this mode the duty cycle of the gate driver outputs are adjusted depending on the current battery voltage level (see section 5.8 "Power Regulation Mode").

In all modes of operation the diagnosis output pin DIAG is used for transferring diagnostic data from the device to an engine control via a serial protocol (DIAG pin, see 5.4.5). The protocol can be configured in the two different modes "Standard diagnosis" or "Advanced diagnosis". Alternatively all control and diagnosis data can be trans-ferred via the supplementary SPI. This allows access to more diagnosis details in contrast to using the serial pro-tocol via DIAG (see 5.9).

5.3 PWM Control Input

5.3.1 Physical Interface: Pin CI

The control input pin CI is pulled-up by an internal resistor RCI,pu to the supply voltage VVS such that VCI = VCI(OFF) andthe glow plugs are switched-off by default. In PWM control mode, the IC is controlled by level transitions at pin CI from VCI(off) to VCI(on) (falling edge) and vice versa (rising edge). Level changes at pin CI shorter than tCI(FIL) are sup-pressed, which effectively limits the input duty cycle.

5.3.2 Glow Control Input Detection

The IC expects a PWM signal at pin CI to control the glow plugs in PWM control mode. Each falling edge starts measuring the ON time tCI(ON) (length of the low pulse beginning with the falling edge to the next rising edge) and theperiod tCI(PER) (time to next falling edge). The first cycle of the input CI is used for an initial measurement of fre-quency, duty cycle and battery voltage. Outputs GDx are enabled at the start of the second falling edge of CI. The end of a pulse group is detected if no falling edge occurs for a time longer than tCI(TO). All glow plugs are turned off, ifthis time out period is exceeded.

If the PWM input remains passive, i.e. CI at level high, for a time longer than tTO(SM) the device is switched to sleep mode with a minimum current consumption from both supply inputs VS and VBAT (see 5.1).

If controlled via the SPI compatible interface (see 5.9), pin CI must not be operated with a PWM, i.e. the input shall be left open to keep it passive.




Figure 5.3.2-1: CI Signal Filtering

The IC transits from sleep mode to normal mode on the first falling edge at pin CI.Each falling edge starts measuring its ON time tCI,ON (length of the Low pulse beginning with the falling edge to the next rising edge) and its period tCI,per (time to next falling edge).

Validation of CI Frequency

If the measured frequency at CI is either lower than fCI(OFF,low) or higher than fCI(OFF,high) the CI signal is regarded as invalid.After the second invalid CI period the gate drivers are switched-off. The current standard diagnosis protocol at pin DIAG will be completed, but no new diagnosis protocols will be started. Due to the missing diagnosis protocols the Engine Control Unit can detect that its CI signal frequency is not valid.

Figure 5.3.2-2: CI PWM frequency

5.3.3 Duty Cycle without Spreading

The CI duty cycle is defined as DCI =tCI.ON/tCI,per with tCI,ON = low pulse length of the CI signal, because CI is low-act-ive.Low or High Pulses at CI shorter than the CI debounce time tCI(FIL) will be ignored.

In "standard diagnosis mode" the duty cycle is validated as described below.

Validation of CI Duty Cycle

If the CI Low pulses are longer than tCI(FIL) but the CI duty cycle is lower than DCI(OFF,low,std) then the glow plugs are not switched but diagnosis protocol is sent and the device does not enter sleep mode.

5.3.4 Duty Cycle with Spreading

In combination with "Advanced diagnosis" a spreading of the duty cycle is applied.

The duty cycle of the PWM at pin CI is restricted to the range 5...95% to allow short detection between CI line and either ground or VBAT. The ASIC spreads this range to 0...100%.




Figure 5.3.4-1: spreading of CI duty cycle

Validation of CI Duty Cycle

If the CI low pulses are• longer than tCI(FIL) but the CI duty cycle is lower than DCI(OFF,low,adv) or• longer than DCI(OFF,high,adv) then the glow plugs are not switched-on but diagnosis protocol is sent and the device

does not enter sleep mode.

Figure 5.3.4-2: CI PWM duty cycle (advanced mode)

5.4 Safety and Diagnosis

5.4.1 Open-Load on Glow Plug

∆If the voltage drop across the external transistor is less than V OL for at least tOL(FIL) an open-load failure is detected as long as VVBAT > VBAT(OL). Otherwise, it will be ignored. Each glow plug channel is measured in a cyclic manner as long as the respective gate driver is enabled.

Due to the debounce filter time open-load cannot be detected when the output duty cycle is very small.Open-load failures are cleared in sleep mode or if the CI input duty cycle is lower than DUTYCI(OFF,low)




The measurement of the voltage drop across the external glow plug transistor is done via the current sense input pins CSPx and CSNx - see chapter "Current Monitoring and Overcurrent Detection". Due to the different input cur-rents at positive and negative current sense input pins (see "Current Sense Input Parameters") the external series resistors at CSPx and CSNx pins cause a shift of the measured voltage difference VCSPx-VCSNx and finally an effect-ive change of the thresholds of open-load detection or overcurrent detection. This effect limits the maximum value of these resistors.

5.4.2 Glow Plug Current Monitoring

5.4.2.1 Current Monitoring and Overcurrent DetectionThe IC supervises the current through 4 glow plugs by measuring the voltage drop across the power NMOS devices. For this purpose 4 positive current sense input pins (CSP1...4) and 4 negative current sense input pins (CSN1...4) are available. The positive current sense inputs are connected to the drains and the negative current sense pins are connected to the sources of the respective power NMOS.

The glow plug current is measured in a cyclic manner. Each glow plug is measured at the latest tOC(DEB) after the previous measurement. The first measurement is done tMASK after switching on the gate driver to mask false over-current signals during the rising edge of gate voltage. An overcurrent condition is detected, if at least 2 consecutive current measurements show an overcurrent, so the resulting debounce time tOC(DEB) is defined by the measurement cycle time.

∆If the voltage drop across the power NMOS is higher than VOC for at least tOC(DEB) an overcurrent failure is detected,∆a failure flag is set and the corresponding power NMOS is switched-off. The threshold for overcurrent failures VOC

can be varied by the voltage VOCTH applied to the pin OCTH (see 5.4.2.3).

If a FET-open failure and an overcurrent failure occur at the same time, only the FET-open failure will be transmit-ted via diagnosis.

5.4.2.2 Overcurrent Failure Counting and ResetIf a glow-plug overcurrent / short-circuit was detected or a "FET-open" failure, the number of further switching events at this glow-plug is supervised and limited by failure counters for each glow-plug output individually to avoid damage of the corresponding power FET. The failure counter is incremented every time when the corresponding output is shut-off caused by an overcurrent or FET-open failure. The failure counter is decremented when the cor-responding glow-plug channel had no overcurrent failure when going to sleep ("glow-plug short no longer exists").Until the failure counters have not reached their limit value of 250, the detected overcurrent failures or FET-open failures are cleared when the IC is entering sleep mode, so after returning from sleep mode the glow-plugs will be switched-on again. When the failure counter reaches its limit value of 250 then the over current failure is not cleared in next sleep mode phase, so the corresponding glow-plug remains off until next power down. During power-on reset all failure counters are reset to their initial value of 0.

The behaviour described above is valid if the TMS pin is connected to ground. If the TMS pin is connected to VDD then the limit value of the failure counter is 1. In this case overcurrent failures are never reset in sleep mode and the corresponding glow-plug remains switched-off until next power-down.

5.4.2.3 Setting the Overcurrent Threshold∆The overcurrent threshold VOC can be adjusted externally by connecting the pin OCTH to a resistive voltage

divider between pin CUR and ground. If the pin OCTH is left open, an internal voltage divider sets the default value for the overcurrent threshold (see 4.4.2-1).

5.4.3 Switch Supervision

The IC monitors the voltages across the glow plugs using the negative sense inputs CSN1 to CSN4 to detect if the corresponding power NMOS transistor switches operate properly. A switch is rated as defective if it is switched ON but the voltage across the corresponding glow plug is less than VCSN(TH) for at least tCSN(FIL) (FET switch "permanently




off"), or if it is switched OFF but the voltage across the glow plug is higher than VCSN(TH) for at least tCSN(FIL) (FET switch "permanently on").

The measurement is done in a cyclic manner. Each power NMOS transistor is measured twice for each glowing cycle tFSH before switching ON the glow plug for measuring a shorted switch and tMASK after switching ON for meas-uring an open switch. The filter time tCSN(FIL) equals the time between two measurements.

If the output duty cycle is 100%, the measurement of switch short is only possible before switching-on the glow plug.

In case of a detected open switch ("FET open") no overcurrent diagnosis will be transmitted. The power NMOS transistor is switched OFF immediately to protect the module against possible overcurrent damages. The further handling of this "FET open" failure is the same as the handling of overcurrent failures - see chapter "Glow Plug Cur-rent Monitoring". Both types of failures are cleared when the IC enters sleep mode or during power-on reset.

In case of a detected shorted switch the transistor will not be switched ON. A FET short failure diagnosis is not transmitted when an open load failure was detected.

5.4.4 Temperature Supervision

An integrated temperature sensor monitors the junction temperature in the IC. If the junction temperature increasesabove TSD all glow plugs are switched-off. They are switched-on again if the junction temperature falls below TSD - Thyst.

5.4.5 Diagnosis Output

The diagnosis output provides diagnostic data of the four glow plug channels and global status information of the control IC.

The diagnosis output DIAG can operate in two different modes.

In "Standard diagnosis mode" the diagnosis protocol at pin DIAG is a 32-bit frame with each bit starting syn-chronously in respect to the falling edge at pin CI.

In "Advanced diagnosis mode" the DIAG output is running at a higher data rate using a 8N1-UART protocol. Themode selection is done by hardware connection of pin SCLK to PGND or VDDA. The SPI clock input is not used if DIAG is employed for diagnostic data output.

The "Advanced diagnosis mode" is combined with a PWM duty cycle spreading (see chapter "PWM control input") while in "Standard diagnosis mode" this spreading is not activated.

Table 5.4.5-1: DIAG mode selection table

SCLK CSB DIAG Comment

Low High Standard mode SCLK pulled down to PGND

High High Advanced mode (UART) SCLK pulled up to VDDA

Clock input Low don't care SPI operation

The output stage at pin DIAG is a current-limited low-side driver with an internal pull-up resistor RDIAG(PU) to the sup-ply VS. The voltage of a logical low level VDIAG(L) is given by the voltage drop across the low-side driver. The voltage level of a logical high signal is equal to the supply VVS.




5.4.6 Standard Diagnosis Mode

In "standard diagnosis mode" the IC is able to indicate the following failures in the load branches controlled by the circuit:

- overcurrent and shut-off (4 glow plugs, stored until next power on reset),- any of 4 power NMOS switches is defective,- open-load (4 glow plugs),- battery voltage VVBAT is lost,- battery voltage VVBAT is too low ("battery undervoltage"),- battery voltage VVBAT is too high ("battery overvoltage"),- charge pump voltage VVCP is too low ("charge pump low"),- junction temperature TJ is too high and- glow plug ground is out of range

In order to report the occurrence of any of the failures listed above to the Diesel engine management system, the IC provides a serial protocol at the diagnosis output DIAG, if PWM control via pin CI is used.

Different failure types can be distinguished and are assigned to the corresponding glow plugs in the serial protocol. Therefore, failures occurring are written into an internal 8-bit failure register as listed in the table below. A failure is denoted by a high state in the failure register.

Table 5.4.6-1: Failure Register Table

Bit Description (high state)

1 overcurrent or open-load failure or FET-open at glow plug channel 1 (GD1)




5 0 (bit not used)

6 0 (bit not used)

7 over current failure at any glow plug channel (additional to bits 1 to 4)or battery voltage VVBAT is lost (VVBAT < VBAT(OFF)) (1*)

8 One or more of the following failures ("module failure"):- any power switch is open (permanently off - additional to bits 1 to 4)- any power switch is shorted (permanently on)- battery voltage VVBAT is lost (VBAT < VBAT(OFF); "battery loss")- battery voltage VVBAT is too low (VBAT < VBAT(UV); " battery undervoltage")- battery voltage VVBAT is too high (VBAT > VBAT(OV); "battery overvoltage")- junction temperature TJ is too high- charge pump voltage VVCP is too low ("charge pump low")- glow plug ground is out of range

1*) In case of "battery loss" bits 7 and 8 are high.

Bits 1 to 4 are allocated to the individual glow plugs. Depending on the state of bit 7 and 8 an overcurrent failure (bit7 HIGH, bit 8 LOW), an open-load failure (bit 7 LOW, bit 8 LOW) or an open-FET is encoded in bits 1 to 4.Bit 8 indicates if there is any of the listed failures ("module failure"). In case of a battery voltage loss, failure bits 7 and 8 are HIGH.

The PWM signal applied to the control input CI is used as the synchronization clock of the serial protocol to which the contents of the failure register is mapped. After any falling edge of the debounced CI signal the value of the next bit of the bit stream is displayed at the DIAG pin. This causes a delay of tCI(FIL) from CI to DIAG. Each transmis-sion frame consists of a start bit (LOW) followed by the 8 data bits of the failure register. The data is shifted LSB first. The 8 bit register data is followed by a stop bit (HIGH).




In standard mode the device starts transmitting the first frame at the second falling edge of the CI signal after power-on. Since at that time the content of the failure register is cleared, the first 9 bits transmitted (start bit fol-lowed by 8 register bits) are always low. The IC repeats transmission of the frame every 32 falling edges of the PWM signal at pin CI. The failure register saves all failures which occur from begin of a transmission until its end. The failures will then be sent via DIAG whereas the failure register gathers new failures of the next 32 periods.

Running transmissions are canceled on transition to sleep mode.

Figure 5.4.6-1: Serial Diagnosis Protocol

5.4.6.1 Diagnosis during low CI duty cycleIf the CI duty cycle is lower than DUTYCI(OFF,low) than no glow plugs are switched ON, but the diagnosis protocols are sent which contain the following informations:

• Overcurrent / glow plug short or FET open failures: These failures can not occur or can not be detected if theglow plugs are not switched ON. However if such failures were detected earlier and were stored in register then they are sent in diagnosis protocol.

• Open-load failure: Can not be detected if the glow plugs are not switched ON. Open-load failures which were detected earlier are cleared, so no open-load failures can occur in the diagnosis protocol.

• All other failure types: Will be detected and sent in diagnosis protocol.If the frequency at pin CI was out of range and after power-on, one valid period at CI is required to start transmis-sion via DIAG in standard mode.

5.4.7 Advanced Diagnosis Mode

The serial protocol of the "Advanced diagnosis" consists of 3 bytes that are transmitted to the ECU using a 8N1 UART protocol.Thus different failure types can be distinguished and assigned to the glow plugs. Therefore, failures occurring are written into an internal failure register as listed in the tables below.

Diagnosis contains 24 bits consisting of 19 bit information and 5 bit CRC. For CRC calculation the CCITT CRC-5 (EPC version) x^5 + x^3 + 1 (initial value 010012) is used.To calculate the CRC the CRC register is preloaded with the value 010012. The data is encoded MSB first. The value of the CRC register after LSB calculation is the CRC value to transmit.To check the CRC the register is preloaded to 010012. The received data is arranged so thatdata[23:16] = DIAG_VBAT,data[15:8] = DIAG_FAIL_PLUG,data[7:0] = DIAG_FAIL_CRCand then checked MSB first. CRC passes if the CRC check result is 000002 after processing all received bits.




Table 5.4.7-1: DIAG registers

Register Name Address Description

DIAG_FAIL_CRC 0x21 common failure and CRC register

DIAG_FAIL_PLUG 0x22 glow plug failure register

DIAG_VBAT 0x23 mean value of battery voltage (the value used for duty cycle recalculation)

When entering sleep mode all failure flags of the ASIC are cleared.

Table 5.4.7-2: Register DIAG_VBAT (0x23) mean value of battery voltage (the value used for duty cycle recalcula-tion)

MSB LSB

Content VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0

Reset value 0 0 0 0 0 0 0 0

Internal access R/W R/W R/W R/W R/W R/W R/W R/W

External access R R R R R R R R

Bit Description

Table 5.4.7-3: Register DIAG_FAIL_PLUG (0x22) glow plug failure register

MSB LSB

Content GF41 GF40 GF31 GF30 GF21 GF20 GF11 GF10

Reset value 0 0 0 0 0 0 0 0



Bit Description GF41 : glow plug 4 failure bit 1GF40 : glow plug 4 failure bit 0GF31 : glow plug 3 failure bit 1GF30 : glow plug 3 failure bit 0GF21 : glow plug 2 failure bit 1GF20 : glow plug 2 failure bit 0GF11 : glow plug 1 failure bit 1GF10 : glow plug 1 failure bit 0




Table 5.4.7-4: Register DIAG_FAIL_CRC (0x21) common failure and CRC register

MSB LSB

Content SF UV OV CRC4 CRC3 CRC2 CRC1 CRC0

Reset value 0 0 0 0 0 0 0 0



Bit Description SF : sum error (0 if OK, 1 if error) for- open FETs (any FET does not switch on)- charge pump under voltage while VBAT is in normal operating range, too- junction temperature TJ is too high- battery voltage VVBAT is lost (VBAT < VBAT(OFF); "battery loss")- glow plug ground is out of rangeUV : under voltage at VBATOV : over voltage at VBATCRC4 : CRC bit 4CRC3 : CRC bit 3CRC2 : CRC bit 2CRC1 : CRC bit 1CRC0 : CRC bit 0

Table 5.4.7-5: glow plug failure codings

failure bit 1 failure bit 0 glue plug state failure priority for dia-gnosis

0 0 no error

0 1 open load of glow plug prio 3 (lowest)

1 0 short circuit to ground prio 2

1 1 short circuit to VBAT (or FET does not switch off)

prio 1 (highest)

The diagnosis transmission at DIAG uses a normal 8N1 UART coding (8 data bits, no parity bit, 1 stopp bit). 1/32th of the CI frequency is used for UART transmission.

Figure 5.4.7-1: UART byte frame

The diagnosis at pin DIAG consist of 3 bytes which are transmitted without inter byte gap.Message start is synchronized with falling edge of CI signal. (Each falling edge of CI starts a new message trans-mission). First byte start bit leading edge starts latest tCI,DIAGafter falling edge of CI signal.

Figure 5.4.7-2: UART codings




The message is sent when the IC is receiving a PWM on CI pin.No diagnosis is sent during the first two periods of a glowing request at CI.In case of invalid timing at pin CI an ongoing transmission at DIAG is finished first. Any incoming falling edges dur-ing DIAG transmission are ignored.After the last glowing cycle a final diagnosis is transmitted to the motor control unit to allow FET short diagnosis in case of 100% glowing.If glowing stops because of invalid CI period no further diag frame will started until the CI periodtime is within the valid range.

Figure 5.4.7-3: diagnosis timings

5.5 Ground Supervision

For advanced diagnostics of the glow plugs (see 5.6) and precise RMS voltage regulation (see 5.8) the IC includes a measurement channel to sense the local ground VGPGND at the glow plugs. The voltage at each pin CSNx is sensed sequentially in a phase when the corresponding glow plug is not powered, i.e the power NMOS is off. Reg-ularly, current in another glow plug (or several others) can generate a positive ground shift at the glow plugs with respect to the IC ground (pin PGND) depending on the resistance of the wiring harness.

In order to be able to process negative ground shifts, which can be induced by imperfect ground wiring at the glow plug control module itself, the voltage at pins CSNx is not measured directly. The down scaled difference between an internal (3.0V) reference voltage and the CSNx pin is used instead.

In case of glowing at 100% duty cycle, only the first measurements before switching on the glow plugs can be usedfor ground supervision. In this case no further glow plug ground measurements are performed after switching on glow plugs.

The voltage drop measured between IC ground (pin PGND) and the ground level at the glow plugs is used for• ground level supervision• duty cycle recalculation in the power regulation mode (see 5.8)

The following conditions are defined to differentiate ranges of glow plug ground shift:The glow plugs can be switched-on as long as the measured absolute ground shift voltage is within the range

.

If the ground shift exceeds this range the activation of the gate drivers is inhibited and an error flag GDERR will be set.

For the recalculation of the output PWM duty cycle in "power regulation" (see section 5.8. "Power Regulation Mode"), the range of ground shift is limited to

.

The voltage at the glow plug pins CSNx is shifted by a resistor network into the voltage range 0V...3.3V for AD con-version during the appropriate time slot for each glow plug channel according to the following formula (VREFH=3V). The resulting voltage VGPGx is the ADC input voltage.




The effective glow plug ground value VGPGND to be respected is calculated by averaging the values VGPGx of all inputs(x=1...4). After averaging the measured value of the ADC ground VADCGND is subtracted. These operations are per-formed digitally.

If an open-load condition or a short-circuited FET is detected on one glow plug channel, the ground sense meas-urement of this glow plug will be ignored by using the last measured value of the previous channel instead. If open-load or a short-circuited FET has been detected at all glow plugs, then 0V will be used as ground measurement since the ground cannot be measured.

Figure 5.5-1: Sensing Channels with ADC




Figure 5.5-2: Characteristic of ground shift valuation and parameters

5.6 Glow Plug Assessment

The IC supports the assessment of the glow plug performance by providing raw data to calculate the glow plug res-istance during the ON state. The raw data consists of the voltage drop via the power NMOS transistor (representingthe glow plug current in ON state) and the voltage measurements of the battery voltage and the ground shift at the glow plugs.

The current-related voltage drop is:

dVCSx = VCSPx - VCSNx

The voltage drop at the glow plug can be calculated from the voltage measurement of the battery voltage VVBAT, the glow plug ground shift VGPGND (see 5.5) and the drop at the current sensing device dVCSx:VGPx VVBAT - VGPGND - dVCSx

The values of voltage drop measurement (for each channel), battery voltage measurement and glow plug ground measurement are converted and can be accessed via DIAG output or SPI interface.

After collecting these data in a processor, the resistance of each glow plug can be calculated by a division, assum-ing the ON-resistance of power NMOS transistors is sufficiently well known:

5.7 High Side Gate Control

5.7.1 Gate Drivers

The IC contains four gate drivers (GDx pins) for external N-channel Power-MOSFETs in high side configuration. Each gate driver provides a slope control by charging and discharging the gates of the external power MOSFETs with constant currents (IGD(ON) or IGD(OFF)). In order to adjust the slopes, these currents can be varied using the CUR pin (see 5.7.2). The charging current source is supplied by an external capacitor connected to the charge pump output pin VCP.




If the gate-source voltage difference reaches values higher than VGS_max_th then the corresponding gate driver is set to High-Z state to protect the gate of the Power-MOSFET - the gate voltage will follow the source potential by capa-citive coupling via the Power-MOSFET capacitances.

Without supply voltage VS or with lost ground at the IC (i.e. CSNx below PGND) the gates and sources of the external Power-MOSFETs are shorted by internal resistors connected between pins GDx and CSNx.

5.7.2 Gate Charge / Discharge Setting

The pin CUR provides a constant, current limited output voltage VCUR. The charge (or discharge) currents for the gates GDx are a multiple of the current flowing out of pin CUR and can therefore be tuned by connecting a resistor from pin CUR to ground (PGND).

5.7.3 Gate Driver Sequencing using PWM Control (CI pin)

The glow plugs are switched-on after the first detected period of valid timing at pin CI. Under all other circum-stances the power NMOS switches will not switch-on, especially during power-on at the VBAT pin.

The period of the CI PWM signal is used as glowing period at the pins GDx. In case of duty cycles <25% the glow plugs are switched-on at the same time the preceding plug is switched-off to minimize switching current (see 5.7.3-1). In case of larger duty cycles or using the SPI the glow plugs are switched-on sequentially at 0%, 25%, 50% and 75% of a glow period (see 5.7.3-2).

The timing at pins GDx is derived from the timing of the CI signal. In case of timing drift or invalid timing at pin CI the timing at pins GDx may lose synchronization to the CI signal. In this case duty cycle and period of the last valid PWM period, detected at pin CI, are used instead. Glowing is stopped after the second invalid PWM period at pin CI without valid timing.

Figure 5.7.3-1: Gate Driver Sequencing for Duty Cycles up to 25%

Figure 5.7.3-2: Gate Driver Sequencing for Duty Cycles above 25% when a PWM via CI is applied or when usingthe SPI

Failures occuring during switching the gate driver outputs are suppressed for a fixed blanking time tMASK, i.e. they are not sent to the corresponding failure registers in order to avoid a misinterpretation of switching effects.




5.7.4 Gate Drive Sequencing Using SPI Interface

The basic timing of the glow plug control outputs is identical to Figure 5.7.3-2, but the clock reference is taken from the internal oscillator. Accordingly, the frequency of the PWM output is defined as TGD(PWM). The glow plugs are activated after receiving the first complete duty cycle by execution of command DUTY_CYCx and DUTY_START via SPI (see 5.9). This transmission of duty cycle must be repeated always before time out tSPI(TO) has elapsed. Oth-erwise all glow plugs will turn off automatically to avoid possible damage due to failing data transmission.

5.7.5 Output duty cycle limitations

The output duty cycle is either calculated in RMS-mode or directly input in "direct input mode" . The output duty cycle is limited as shown in 5.7.5-1.

Figure 5.7.5-1: Output duty cycle limitations

5.8 Power Regulation Mode

In "power regulation mode" the root mean square voltage level (RMS) at the glow plugs is regulated to a constant value dependent on the current battery voltage VVBAT as measured on chip. In case of constant glow plug resistanceRGP this RMS regulation leads to constant power dissipation in the glow plugs. This mode of operation is selected, ifmode input MSEL is pulled to low level, i.e. VMSEL < VMSEL(TH) (see 5.2).

The power dissipation in one glow plug is a function of the voltage drop at the glow plug VGP - equal to the battery Θvoltage if no ground shift appears at the glow plugs-, the duty cycle G applied to the glow plugs and the glow plug

resistance RPG.

where:

VGP = VVBAT - VGPGND




ΘThe set point of the power is given by the input duty cycle received via CI pin (input PWM) or the SPI CI and the reference battery voltage VBAT,0 (default value 12V):

where:

For RMS voltage regulation (VRMS = VRMS,0 Θ) the output duty cycle at the gate drivers G is calculated and adjusted bythe E525.07 IC according to the measured battery voltage VVBAT and the local glow plug ground VGPGND:

The accuracy of the RMS regulation is expressed as the deviation of the RMS voltage from its set- point value:

,where:

,

5.9 SPI Interface and Digital Functions

5.9.1 Description of the SPI

The SPI can be used as an alternative communication interface for controlling the glow plugs and acquisition of dia-gnosis data of the glow plug module. If this SPI communication channel is used, no PWM input at CI is required and the timing control for the glow plug outputs is generated from the on-chip internal oscillator. The DIAG output isneither used, if SPI communication is employed. As usual, the SPI communication is controlled by the enable pin CSB ("low" during a SPI frame) and the SPI clock input SCLK (see 5.9.1.2-1). This means, pull up or pull down devices as used for definition of the DIAG interface mode, are not allowed if the SPI is active.

The SPI compatible interface is intended for operation of the IC in combination with a micro processor, typically integrated on the same PCB and used to handle alternative communication protocols for the ECU (e.g. LIN, etc.). The SPI communication channel offers the same diagnosis features as the "advanced mode" via DIAG including "Glow plug ground sensing" and "Glow plug Assessment" (sections 5.5 and 5.6).

Moreover, in order to support the supervision of a co-processor, a time-out watchdog is integrated in the IC. This watchdog can be configured and needs to be triggered repetitively via SPI. In case a watchdog time-out expires before receiving a trigger command, the reset output RESB is pulled low to reset the µP.

5.9.1.1 Features- 8 bit transfer- Data is shifted in/out MSB first- Active low CSB input- Read data on MISO/MOSI on falling edge of SCK, write data on rising edge of SCK- Watchdog configuration (time) and trigger via SPI




5.9.1.2 Timing Diagram

Figure 5.9.1.2-1: SPI compatible interface timing diagram

5.9.1.3 SPI Data TransfersAn SPI frame consists of an address byte including information about reading or writing data and a second byte including the data to be written or a dummy byte (5.9.1.3-1 below). For reading data, the MSB of the address byte has to be '1'.

Figure 5.9.1.3-1: SPI Compatible Interface Data Structure




Table 5.9.1.3-1: SPI register

Register Name Address Description

GPFAIL 0x01 This Register contains the status of the glow plugs

SWFAIL 0x02 This Register contains the status of the power switches

MODFAIL 0x03 This register contains the status of the module

VBAT_MEAS 0x04 This register contains the mean battery voltage at VBAT

GPGND_MEAS 0x05 This register contains the mean glow plug ground voltage VGPGND (see section 5.5)

GP1CURR 0x06 This register contains the sensed voltage drop dVCSN of glow plug 1




DUTY_CYC1 0x0A This register contains the duty cycle for glow plug 1

DUTY_CYC2 0x0B This register contains the duty cycle for glow plug 2

DUTY_CYC3 0x0C This register contains the duty cycle for glow plug 3

DUTY_CYC4 0x0D This register contains the duty cycle for glow plug 4

DUTY_START 0x0E With this register the duty cycles will be taken over

WDCONF 0x0F This register contains the configuration data for the watchdog

WDTRIG 0x10 This register triggers the watchdog

Table 5.9.1.3-2: Register GPFAIL (0x01) This Register contains the status of the glow plugs

MSB LSB

Content GP4_OC GP4_open GP3_OC GP3_open GP2_OC GP2_open GP1_OC GP1_open

Reset value 0 0 0 0 0 0 0 0



Bit Description GP4_OC : Over current detected at glow plug 4GP4_open : Open load detected at glow plug 4GP3_OC : Over current detected at glow plug 3GP3_open : Open load detected at glow plug 3GP2_OC : Over current detected at glow plug 2GP2_open : Open load detected at glow plug 2GP1_OC : Over current detected at glow plug 1GP1_open : Open load detected at glow plug 1




Table 5.9.1.3-3: Register SWFAIL (0x02) This Register contains the status of the power switches

MSB LSB

Content FET4_short

FET4_open

FET3_short

FET3_open

FET2_short

FET2_open

FET1_short

FET1_open

Reset value 0 0 0 0 0 0 0 0



Bit Description FET4_short : Detected a short-circuit at FET 4FET4_open : Detected an open FET at FET 4FET3_short : Detected a short-circuit at FET 3FET3_open : Detected an open FET at FET 3FET2_short : Detected a short-circuit at FET 2FET2_open : Detected an open FET at FET 2FET1_short : Detected a short-circuit at FET 1FET1_open : Detected an open FET at FET 1

Table 5.9.1.3-4: Register MODFAIL (0x03) This register contains the status of the module

MSB LSB

Content VBATOV VBATUV VBATLOSS

CPLOW GNDERR THIGH - -

Reset value 0 0 0 0 0 0 0 0



Bit Description VBATOV : VBAT overvoltage occurredVBATUV : VBAT undervoltage occurredVBATLOSS : VBAT loss occurredCPLOW : VCP undervoltage occurredGNDERR : Glow plug ground shift error occurredTHIGH : Overtemperature occurred

Table 5.9.1.3-5: Register VBAT_MEAS (0x04) This register contains the mean battery voltage at VBAT

MSB LSB

Content VBAT[7:0]

Reset value 0

Internal access R/W

External access R

Bit Description VBAT[7:0] : Battery voltage VBAT

Table 5.9.1.3-6: Register GPGND_MEAS (0x05) This register contains the mean glow plug ground voltage VGPGND (see section 5.5)

MSB LSB

Content GND[7:0]

Reset value 0

Internal access R/W

External access R

Bit Description GND[7:0] : Mean glow plug ground voltage




Table 5.9.1.3-7: Register GP1CURR (0x06) This register contains the sensed voltage drop dVCSN of glow plug 1

MSB LSB

Content GPC1[7:0]

Reset value 0

Internal access R/W

External access R

Bit Description GPC1[7:0] : Glow plug current of glow plug 1


MSB LSB

Content GPC2[7:0]

Reset value 0

Internal access R/W

External access R



MSB LSB

Content GPC3[7:0]

Reset value 0

Internal access R/W

External access R



MSB LSB

Content GPC4[7:0]

Reset value 0

Internal access R/W

External access R


Table 5.9.1.3-11: Register DUTY_CYC1 (0x0A) This register contains the duty cycle for glow plug 1

MSB LSB

Content DC1[7:0]

Reset value 0

Internal access R/W

External access R/W

Bit Description DC1[7:0] : Duty Cycle for Glow Plug 1




Table 5.9.1.3-12: Register DUTY_CYC2 (0x0B) This register contains the duty cycle for glow plug 2

MSB LSB

Content DC2[7:0]

Reset value 0

Internal access R/W

External access R/W


Table 5.9.1.3-13: Register DUTY_CYC3 (0x0C) This register contains the duty cycle for glow plug 3

MSB LSB

Content DC3[7:0]

Reset value 0

Internal access R/W

External access R/W


Table 5.9.1.3-14: Register DUTY_CYC4 (0x0D) This register contains the duty cycle for glow plug 4

MSB LSB

Content DC4[7:0]

Reset value 0

Internal access R/W

External access R/W


Table 5.9.1.3-15: Register DUTY_START (0x0E) With this register the duty cycles will be taken over

MSB LSB

Content DS[7:0]

Reset value 0

Internal access R/W

External access W

Bit Description DS[7:0] : Write this address with 0xA3 to take over the values stored in DUTY_CYCx

Table 5.9.1.3-16: Register WDCONF (0x0F) This register contains the configuration data for the watchdog

MSB LSB

Content - - - - - - WDCFG[1:0]

Reset value 0 0 0 0 0 0 00

Internal access R/W R/W R/W R/W R/W R/W R/W

External access R R R R R R R/W

Bit Description WDCFG[1:0] : 00: 10ms Watchdog time01: 20ms Watchdog time10: 50ms Watchdog time11: 100ms Watchdog time




Table 5.9.1.3-17: Register WDTRIG (0x10) This register triggers the watchdog

MSB LSB

Content WD[7:0]

Reset value 0

Internal access R/W

External access W

Bit Description WD[7:0] : Watchdog has to be triggered with WD=0x05

To write duty cycles, the registers DUTY_CYC1 to DUTY_CYC4 have to be written. Afterwards, the register DUTY_START has to be written with the data word 0xA3. This access transfers the data written to DUTY_CYC1 to DUTY_CYC4 to internal registers, where they will be used to define the output duty cycle. The IC will start glowing after this command is received.The duty cycles currently used for glowing can be read by accessing the registers DUTY_CYC1 to DUTY_CYC4.

The transfer to DUTY_START must be repeated before the time out delay tSPI(TO) has elapsed. If no update was received before the time out, all glow plugs are be turned off automatically.The temporary duty cycle registers are not deleted until power on reset, thus writing DUTY_START again triggers anew glowing and resets the glow time out counter.

5.9.2 Watchdog

Table 5.9.2-1: Watchdog times configured by WDCFG

WDCFG[1:0] Watchdog time out

00 10ms

01 20ms

10 50ms

11 100ms

The watchdog is a time-out watchdog. This means after the configured time has elapsed, the watchdog will set the pin RESB to LOW for tWD_RESB_Low. After that, RESB is set to HIGH again and a new period starts with the highest configurable time. This allows a proper start-up of the micro controller.The watchdog can be triggered by writing 0x05 to register WDTRIG. Each reception of a watchdog trigger will resetthe timer and start a new trigger period, which needs to be responded again with the next trigger before the time out occurs.Reconfiguring the time-out of the watchdog may lead to a watchdog reset if the new configured time is lower then the time from the last trigger.Each wake-up event via CI will cause the watchdog to output a reset e.g. for starting a micro controller from sleep mode.

Figure 5.9.2-1: Watchdog behavior and timing




6 Package Outline QFN32L6

Package Outline and Dimensions are according JEDEC MO-220 K, variant VJJC-2




Description Symbolmm inch

min typ max min typ maxPackage height A 0.80 0.90 1.00 0.031 0.035 0.039

Stand off A1 0.00 0.02 0.05 0.000 0.00079 0.002

Thickness of terminal leads, including lead finish A3 -- 0.20 REF -- -- 0.0079 REF --

Width of terminal leads b 0.25 0.30 0.35 0.010 0.012 0.014

Package length / width D / E -- 6.00 BSC -- -- 0.237 BSC --

Length / width of exposed pad D2 / E2 3.60 3.75 3.90 0.142 0.148 0.154

Lead pitch e -- 0.65 BSC -- -- 0.026 BSC --

Length of terminal for soldering to substrate L 0.35 0.40 0.45 0.014 0.016 0.018

Step cut depth (incl. plating layer) SCD 0.075 0.100 0.125 0.003 0.004 0.005

Step cut length (incl. plating layer) SCL 0.025 0.050 0.075 0.001 0.002 0.003

Number of terminal positions N 32 32

Note: the mm values are valid, the inch values contains rounding errorsNote 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification)




7 ESD, Latchup and EMC

7.1 Electro Static Discharge (ESD)

Table 7.1-1: ESD on IC Level, Human Body Model (HBM)

Standard AEC-Q100-002

Model Human Body Model

Capacitance 100 pF

Resistance Ω1,5 k

Minimum withstand Voltage +/- 2 kV

Table 7.1-2: ESD on IC Level, Charged Device Model (CDM)

Standard AEC-Q100-011

Model Charged Device Model

Minimum withstand Voltage +/- 750 V for edge pins

+/- 500 V for all other pins

7.2 Latch-up

Latch-up performance is validated according to JEDEC standard JESD 78 in its valid revision.




8 Reliability

8.1 Qualification

Product qualification is performed according to the automotive standard AEC-Q100 in the revision valid at the start of development.




9 Storage, Handling, Packing and Shipping

9.1 Storage

Storage conditions should not exceed those given in Chapter 3.2 Absolute Maximum Ratings.The Moisture Sensitivity Level is specified according to MSL3 (JEDEC J-STD-020 in its valid revision).

9.2 Handling

Devices are sensitive to damage by Electrostatic Discharge (ESD) and should only be handled at an ESD protec-ted workstation.

Handling conditions should not exceed those given in Chapter 3.2 Absolute Maximum Ratings.

9.3 Packing

Material shall be packed for shipment as follows:• Tape-on-Reel• Drybag for MPC samples• Every reel respectively drybag will be packed in a packing carton. Each packing carton will be marked and

sealed by using the standard label for packings.

9.4 Shipping

Each delivery shall be accompanied by the following:• Certificate of conformance to the specification• Delivery note




10 Record of Revisions

Table 10-1: Record of Revisions

Chapter Rev. Description of change Date Released

- 00 Initial document version Apr 13, 2017 KHN/ZOE




11 Index

Table of Content1 Principle of operation..................................................................................................................................................3

1.1 IC Architecture....................................................................................................................................................31.1.1 Block Diagram............................................................................................................................................3

1.2 Brief functional description.................................................................................................................................32 Package and Pinout...................................................................................................................................................4

2.1 Package Reference............................................................................................................................................42.2 Pin Description...................................................................................................................................................42.3 Package Pinout..................................................................................................................................................5

3 Operating Conditions..................................................................................................................................................63.1 Recommended Operating Conditions................................................................................................................63.2 Absolute Maximum Ratings................................................................................................................................6

4 Detailed Electrical Specification.................................................................................................................................84.1 Power Supply.....................................................................................................................................................8

4.1.1 Charge Pump.............................................................................................................................................84.1.2 Voltage Monitoring.....................................................................................................................................9

4.1.2.1 VDD Monitoring..................................................................................................................................94.1.2.2 VBAT monitoring................................................................................................................................94.1.2.3 VCP monitoring..................................................................................................................................9

4.2 Device Modes of Operation..............................................................................................................................104.2.1 Modes of PWM Control and Overcurrent Failure Reset..........................................................................10

4.3 PWM Control Input...........................................................................................................................................104.3.1 Physical Interface: Pin CI.........................................................................................................................104.3.2 Glow Control Input Detection...................................................................................................................104.3.3 Duty Cycle without Spreading..................................................................................................................104.3.4 Duty Cycle with Spreading.......................................................................................................................11

4.4 Safety and Diagnosis.......................................................................................................................................114.4.1 Open-Load on Glow Plug.........................................................................................................................114.4.2 Glow Plug Current Monitoring..................................................................................................................114.4.3 Temperature Supervision.........................................................................................................................124.4.4 Diagnosis Output......................................................................................................................................124.4.5 Advanced Diagnosis Mode......................................................................................................................13

4.5 Ground Supervision..........................................................................................................................................134.6 Glow Plug Assessment....................................................................................................................................134.7 High Side Gate Control....................................................................................................................................144.8 Power Regulation Mode...................................................................................................................................154.9 SPI Interface and Digital Functions..................................................................................................................15

4.9.1 Description of the SPI..............................................................................................................................155 Functional Description..............................................................................................................................................17

5.1 Power Supply...................................................................................................................................................175.1.1 Charge Pump...........................................................................................................................................175.1.2 Voltage Monitoring...................................................................................................................................17

5.1.2.1 VDD Monitoring................................................................................................................................175.1.2.2 VBAT monitoring..............................................................................................................................175.1.2.3 VCP monitoring................................................................................................................................18

5.2 Device Modes of Operation..............................................................................................................................185.2.1 Modes of PWM Control and Overcurrent Failure Reset..........................................................................18

5.3 PWM Control Input...........................................................................................................................................195.3.1 Physical Interface: Pin CI.........................................................................................................................195.3.2 Glow Control Input Detection...................................................................................................................195.3.3 Duty Cycle without Spreading..................................................................................................................205.3.4 Duty Cycle with Spreading.......................................................................................................................20

5.4 Safety and Diagnosis.......................................................................................................................................21




5.4.1 Open-Load on Glow Plug.........................................................................................................................215.4.2 Glow Plug Current Monitoring..................................................................................................................22

5.4.2.1 Current Monitoring and Overcurrent Detection................................................................................225.4.2.2 Overcurrent Failure Counting and Reset.........................................................................................225.4.2.3 Setting the Overcurrent Threshold...................................................................................................22

5.4.3 Switch Supervision...................................................................................................................................225.4.4 Temperature Supervision.........................................................................................................................235.4.5 Diagnosis Output......................................................................................................................................235.4.6 Standard Diagnosis Mode........................................................................................................................24

5.4.6.1 Diagnosis during low CI duty cycle..................................................................................................255.4.7 Advanced Diagnosis Mode......................................................................................................................25

5.5 Ground Supervision..........................................................................................................................................285.6 Glow Plug Assessment....................................................................................................................................305.7 High Side Gate Control....................................................................................................................................30

5.7.1 Gate Drivers.............................................................................................................................................305.7.2 Gate Charge / Discharge Setting.............................................................................................................315.7.3 Gate Driver Sequencing using PWM Control (CI pin)..............................................................................315.7.4 Gate Drive Sequencing Using SPI Interface............................................................................................325.7.5 Output duty cycle limitations....................................................................................................................32

5.8 Power Regulation Mode...................................................................................................................................325.9 SPI Interface and Digital Functions..................................................................................................................33

5.9.1 Description of the SPI..............................................................................................................................335.9.1.1 Features...........................................................................................................................................335.9.1.2 Timing Diagram................................................................................................................................345.9.1.3 SPI Data Transfers...........................................................................................................................34

5.9.2 Watchdog.................................................................................................................................................396 Package Outline QFN32L6.......................................................................................................................................407 ESD, Latchup and EMC...........................................................................................................................................42

7.1 Electro Static Discharge (ESD)........................................................................................................................427.2 Latch-up............................................................................................................................................................42

8 Reliability..................................................................................................................................................................438.1 Qualification......................................................................................................................................................43

9 Storage, Handling, Packing and Shipping................................................................................................................449.1 Storage.............................................................................................................................................................449.2 Handling...........................................................................................................................................................449.3 Packing.............................................................................................................................................................449.4 Shipping............................................................................................................................................................44

10 Record of Revisions...............................................................................................................................................4511 Index.......................................................................................................................................................................46

Illustration IndexFigure 1: Application diagram........................................................................................................................................1Figure 1.1.1-1: Simplified functional block diagram......................................................................................................3Figure 2.3-1: Package Pinout........................................................................................................................................6Figure 5.3.2-1: CI Signal Filtering................................................................................................................................21Figure 5.3.2-2: CI PWM frequency..............................................................................................................................21Figure 5.3.4-1: spreading of CI duty cycle...................................................................................................................22Figure 5.3.4-2: CI PWM duty cycle (advanced mode)................................................................................................22Figure 5.4.6-1: Serial Diagnosis Protocol....................................................................................................................26Figure 5.4.7-1: UART byte frame................................................................................................................................28Figure 5.4.7-2: UART codings.....................................................................................................................................28Figure 5.4.7-3: diagnosis timings................................................................................................................................29Figure 5.5-1: Sensing Channels with ADC..................................................................................................................30Figure 5.5-2: Characteristic of ground shift valuation and parameters.......................................................................31Figure 5.7.3-1: Gate Driver Sequencing for Duty Cycles up to 25%...........................................................................32




Figure 5.7.3-2: Gate Driver Sequencing for Duty Cycles above 25% when a PWM via CI is applied or when using the SPI.........................................................................................................................................................................32Figure 5.7.5-1: Output duty cycle limitations...............................................................................................................33Figure 5.9.1.2-1: SPI compatible interface timing diagram.........................................................................................35Figure 5.9.1.3-1: SPI Compatible Interface Data Structure.........................................................................................35Figure 5.9.2-1: Watchdog behavior and timing...........................................................................................................40



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