© Semiconductor Components Industries, LLC, 2012

November, 2017 − Rev. 31 Publication Order Number:

FDMS3660S/D

FDMS3660S

PowerTrench� Power Stage

Asymmetric Dual N−Channel MOSFET

DescriptionThis device includes two specialized N−Channel MOSFETs in a

dual PQFN package. The switch node has been internally connected toenable easy placement and routing of synchronous buck converters.The control MOSFET (Q1) and synchronous SyncFET (Q2) havebeen designed to provide optimal power efficiency.

Features

Q1: N−Channel• Max rDS(on) = 8 m� at VGS = 10 V, ID = 13 A

• Max rDS(on) = 11 m� at VGS = 4.5 V, ID = 11 AQ2: N−Channel• Max rDS(on) = 1.8 m� at VGS = 10 V, ID = 30 A

• Max rDS(on) = 2.2 m� at VGS = 4.5 V, ID = 27 A

• Low Inductance Packaging Shortens Rise/Fall Times, Resulting inLower Switching Losses

• MOSFET Integration Enables Optimum Layout for Lower CircuitInductance and Reduced Switch Node Ringing

• These Devices are Pb−Free and are RoHS Compliant

Applications

• Computing

• Communications

• General Purpose Point of Load

• Notebook VCORE

PQFN8POWER 56

CASE 483AJ

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4

3

2

1

5

6

7

Q8 1

QS2

S2

S2

G2

D1

D1

D1

G1

PHASE

2

See detailed ordering and shipping information on page 2 ofthis data sheet.

ORDERING INFORMATION

G1D1

D1D1

G2S2

S2S2

D1

PHASE(S1/D2)

Pin 1

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MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Symbol Rating Q1 Q2 Unit

VDS Drain to Source Voltage 30 30 V

Bvdsst Bvdsst (Transient) < 100 ns 36 36 V

VGS Gate to Source Voltage (Note 3) ±20 ±12 V

ID Drain Current − Continuous (Package limited) (TC = 25°C) 30 60 A

Drain Current − Continuous (Silicon limited) (TC = 25°C) 60 145

Drain Current − Continuous (TA = 25°C) 13 (Note 6a) 30 (Note 6b)

Drain Current − Pulsed 40 120

EAS Single Pulse Avalanche Energy 33 (Note 4) 86 (Note 5) mJ

PD Power Dissipation for Single Operation (TA = 25°C) 2.2 (Note 6a) 2.5 (Note 6b) W

Power Dissipation for Single Operation (TA = 25°C) 1 (Note 6c) 1 (Note 6d)

TJ, TSTG Operating and Storage Junction Temperature Range −55 to +150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS

Symbol Parameter Q1 Q2 Unit

R�JA Thermal Resistance, Junction−to−Ambient 57 (Note 6a) 50 (Note 6b) °C/W

R�JA Thermal Resistance, Junction−to−Ambient 125 (Note 6c) 120 (Note 6d) °C/W

R�JC Thermal Resistance, Junction−to−Case 2.9 2.2 °C/W

PACKAGE MARKING AND ORDERING INFORMATION

Device Device Marking Package Reel Size Tape Width Quantity

FDMS3660S 22CF07OD

Power 56 13″ 12 mm 3000 Units

Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted

Symbol Parameter Test Conditions Type Min Typ Max Units

OFF CHARACTERISTICS

BVDSS Drain to Source Breakdown Voltage ID = 250 �A, VGS = 0 VID = 1 mA, VGS = 0 V

Q1Q2

3030

V

�BVDSS/�TJ

Breakdown Voltage Temperature Coefficient

ID = 250 �A, referenced to 25°CID = 10 mA, referenced to 25°C

Q1Q2

1624

mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1Q2

1500

�A�A

IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 VVGS = 12 V, VDS = 0 V

Q1Q2

100100

nAnA

ON CHARACTERISTICS

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 �AVGS = VDS, ID = 1 mA

Q1Q2

1.11.1

1.91.5

2.72.2

V

�VGS(th)/�TJ

Gate to Source Threshold VoltageTemperature Coefficient

ID = 250 �A, referenced to 25°CID = 10 mA, referenced to 25°C

Q1Q2

−6−3

mV/°C

rDS(on) Drain to Source On Resistance VGS = 10 V, ID = 13 AVGS = 4.5 V, ID = 11 AVGS = 10 V, ID = 13 A, TJ =125°C

Q1 46

5.7

8118.7

m�

VGS = 10 V, ID = 30 AVGS = 4.5 V, ID = 27 AVGS = 10 V, ID = 30 A, TJ = 125°C

Q2 1.31.51.86

1.82.22.6

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Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted

Symbol UnitsMaxTypMinTypeTest ConditionsParameter

ON CHARACTERISTICS

gFS Forward Transconductance VDS = 5 V, ID = 13 AVDS = 5 V, ID = 30 A

Q1Q2

62231

S

DYNAMIC CHARACTERISTICS

Ciss Input Capacitance Q1:VDS = 15 V, VGS = 0 V, f = 1 MHZ

Q2:VDS = 15 V, VGS = 0 V, f = 1 MHZ

Q1Q2

13254130

17655493

pF

Coss Output Capacitance Q1Q2

466915

6201220

pF

Crss Reverse Transfer Capacitance Q1Q2

46124

70185

pF

Rg Gate Resistance Q1Q2

0.20.2

0.60.8

23

�

SWITCHING CHARACTERISTICS

td(on) Turn−On Delay Time Q1:VDD = 15 V, ID = 13 A, RGEN = 6 �

Q2:VDD = 15 V, ID = 30 A, RGEN = 6 �

Q1Q2

7.711

1520

ns

tr Rise Time Q1Q2

2.25

1010

ns

td(off) Turn−Off Delay Time Q1Q2

1940

3464

ns

tf Fall Time Q1Q2

1.83.9

1010

ns

Qg Total Gate Charge VGS = 0 V to10 V

Q1VDD = 15 V, ID = 13 AQ2VDD = 15 V, ID = 30 A

Q1Q2

2162

2987

nC

Qg Total Gate Charge VGS = 0 V to4.5 V

Q1Q2

9.529

1341

nC

Qgs Gate to Source Gate Charge Q1VDD = 15 V, ID = 13 AQ2VDD = 15 V, ID = 30 A

Q1Q2

3.99

nC

Qgd Gate to Drain “Miller” Charge Q1Q2

2.67

nC

DRAIN−SOURCE DIODE CHARACTERISTICS

VSD Source to Drain Diode Forward Volt-age

VGS = 0 V, IS = 13 A (Note 2)VGS = 0 V, IS = 2 A (Note 2)VGS = 0 V, IS = 30 A (Note 2)VGS = 0 V, IS = 2 A (Note 2)

Q1Q1Q2Q2

0.80.70.80.6

1.21.21.21.2

V

trr Reverse Recovery Time Q1IF = 13 A, di/dt = 100 A/�sQ2IF = 30 A, di/dt = 300 A/�s

Q1Q2

2629

4246

ns

Qrr Reverse Recovery Charge Q1Q2

1032

2050

nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.1. R�JA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R�JC is guaranteed

by design while R�CA is determined by the user’s board design.2. Pulse Test: Pulse Width < 300 �s, Duty cycle < 2.0%.3. As an N−ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied with the negative Vgs

rating.4. EAS of 33 mJ is based on starting TJ = 25°C; N−ch: L = 1.9 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A.5. EAS of 86 mJ is based on starting TJ = 25°C; N−ch: L = 0.6 mH, IAS = 17 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 31 A.

FDMS3660S

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(Note 6a) (Note 6b)

(Note 6c) (Note 6d)

G DF

DS

SF

SS

G DF

DS

SF

SS

G DF

DS

SF

SS

G DF

DS

SF

SS

6. a) 57°C/W when mounted on a 1 in2 pad of 2 oz copperb) 50°C/W when mounted on a 1 in2 pad of 2 oz copperc) 125°C/W when mounted on a minimum pad of 2 oz copperd) 120°C/W when mounted on a minimum pad of 2 oz copper

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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted

0.0 0.2 0.4 0.6 0.8 1.00

10

20

30

40

VGS = 6 V

VGS = 4 V

VGS = 10 V

VGS = 4.5 V

VGS = 3.5 V

PULSE DURATION = 80�sDUTY CYCLE = 0.5% MAX

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

0 10 20 30 400

1

2

3

4

VGS = 6 V

VGS = 3.5 V

PULSE DURATION = 80 �sDUTY CYCLE = 0.5% MAX

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

−RE

SIS

TAN

CE

ID, DRAIN CURRENT (A)

VGS = 4 V

VGS = 4.5 V VGS = 10 V

−75 −50 −25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6ID = 13 AVGS = 10 V

NO

RM

AL

IZE

D D

RA

IN T

O S

OU

RC

E O

N−R

ES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (o C)

2 4 6 8 100

4

8

12

16

20

TJ = 125 oC

ID = 13 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS

(on)

,D

RA

IN T

O

SO

UR

CE

ON

−RE

SIS

TA

NC

E( m

�) PULSE DURATION = 80�s

DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.00

10

20

30

40

TJ = 150 oC

VDS = 5 V

PULSE DURATION = 80 �sDUTY CYCLE = 0.5% MAX

TJ = −55oC

TJ = 25 oC

I D, D

RA

IN C

UR

RE

NT

(A

)

VGS, GATE TO SOURCE VOLTAGE (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

40

TJ = −55oC

TJ = 25 oC

TJ = 150 oC

VGS = 0 V

I S, R

EV

ER

SE

DR

AIN

CU

RR

EN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Figure 1. On Region Characteristics Figure 2. Normalized On−Resistance vs. DrainCurrent and Gate Voltage

Figure 3. Normalized On Resistance vs.Junction Temperature

Figure 4. On−Resistance vs. Gate to SourceVoltage

Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode ForwardVoltage vs. Source Current

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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted

0 5 10 15 20 250

2

4

6

8

10ID = 13 A

VDD = 20 V

VDD = 10 V

VG

S, G

AT

E T

O S

OU

RC

E V

OL

TA

GE

(V

)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 3010

100

1000

2000

f = 1 MHz

VGS = 0 V

CA

PA

CIT

AN

CE

(p

F)

VDS, DRAIN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

0.001 0.01 0.1 1 10 1001

10

100

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS, A

VA

LA

NC

HE

CU

RR

EN

T (

A)

25 50 75 100 125 1500

20

40

60

80

R�JC = 2.9 oC/W

VGS = 4.5 V

Limited by Package

VGS = 10 VI D

,DR

AIN

CU

RR

EN

T (

A)

TC, CASE TEMPERATURE (oC)

0.01 0.1 1 10 100 2000.01

0.1

1

10

100

100 �s

DC

100 ms10 ms

1 ms

1 s

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA ISLIMITED BY rDS(on)

SINGLE PULSE

TJ = MAX RATED

R�JA = 125 oC/W

TA = 25 oC

10 s

10−4 10−3 10−2 10−1 1 10 100 10000.1

1

10

100

1000SINGLE PULSE

R�JA= 125 oC/W

P( P

K) ,

PE

AK

TR

AN

SIE

NT

PO

WE

R (W

)

t, PULSE WIDTH (sec)

Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to SourceVoltage

Figure 9. Unclamped Inductive SwitchingCapability

Figure 10. Maximum Continuous DrainCurrent vs. Case Temperature

Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum PowerDissipation

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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted

10−4 10−3 10−2 10−1 11 0 100 10000.001

0.01

0.1

1

2

SINGLE PULSE

R�JA = 125 oC/W

(Note 1c)

DUTY CYCLE−DESCENDING ORDERN

OR

MA

LIZ

ED

TH

ER

MA

LIM

PE

DA

NC

E,

Z�JA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x Z�JA x R�JA + TA

Figure 13. Junction−to−Ambient Transient Thermal Response Curve

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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted

0.0 0.2 0.4 0.6 0.8 1.00

20

40

60

80

100

120

VGS = 2.5 V

VGS = 3 V

VGS = 10 V

VGS = 4.5 V

VGS = 3.5 V

PULSE DURATION = 80�sDUTY CYCLE = 0.5% MAXI D

, DR

AIN

CU

RR

EN

T (A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

0 20 40 60 80 100 1200

1

2

3

4

VGS = 3 V

VGS = 3.5 V

PULSE DURATION = 80 �sDUTY CYCLE = 0.5% MAX

NO

RM

AL

IZE

DD

RA

IN T

O S

OU

RC

E O

N−R

ES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 2.5 V

VGS = 4.5 V VGS = 10 V

−75 −50 −25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6ID = 30 AVGS = 10 V

NO

RM

AL

IZE

D D

RA

IN T

O S

OU

RC

E O

N−R

ES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)

2 4 6 8 100

2

4

6

8

TJ = 125 oC

ID = 30 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS

(on

),D

RA

IN T

O

SO

UR

CE

ON

−RE

SIS

TA

NC

E( m

�) PULSE DURATION = 80�s

DUTY CYCLE = 0.5% MAX

1.0 1.5 2.0 2.5 3.00

20

40

60

80

100

120

TJ = 125 oC

VDS = 5 V

PULSE DURATION = 80�sDUTY CYCLE = 0.5% MAX

TJ = −55oC

TJ = 25 oC

I D, D

RA

IN C

UR

RE

NT

(A

)

VGS, GATE TO SOURCE VOLTAGE (V)0.0 0.2 0.4 0.6 0.8 1.0

0.001

0.01

0.1

1

10

100

TJ = −55oC

TJ = 25 oC

TJ = 125 oC

VGS = 0 V

I S, R

EV

ER

SE

DR

AIN

CU

RR

EN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Figure 14. On Region Characteristics Figure 15. Normalized On−Resistance vs.Drain Current and Gate Voltage

Figure 16. Normalized On−Resistance vs.Junction Temperature

Figure 17. On−Resistance vs. Gate to SourceVoltage

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode ForwardVoltage vs. Source Current

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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted

0 10 20 30 40 50 60 700

2

4

6

8

10ID = 30 A

VDD = 20 V

VDD = 10 V

VG

S, G

AT

E T

O S

OU

RC

E V

OL

TA

GE

(V

)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 3010

100

1000

10000

f = 1 MHz

VGS = 0 V

CA

PA

CIT

AN

CE

(pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

0.001 0.01 0.1 1 10 100 10001

10

100

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS, A

VA

LA

NC

HE

CU

RR

EN

T (

A)

25 50 75 100 125 1500

40

80

120

160

Limited by Package

R�JC = 2.2 oC/W

VGS = 4.5 V

VGS = 10 V

I D,D

RA

IN C

UR

RE

NT

(A

)

TC, CASE TEMPERATURE (oC)

0.01 0.1 1 10 100 2000.01

0.1

1

10

100200

100 �s

DC

100 ms

10 ms

1 ms

1s

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA ISLIMITED BY rDS(on)

SINGLE PULSE

TJ = MAX RATED

R�JA = 120 oC/W

TA = 25 oC

10s

10−4 10−3 10−2 10−1 1 10 100 10000.5

1

10

100

10002000

SINGLE PULSE

R�JA= 120 oC/W

P( P

K) ,

PE

AK

TR

AN

SIE

NT

PO

WE

R (

W)

t, PULSE WIDTH (sec)

Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain to SourceVoltage

Figure 22. Unclamped Inductive SwitchingCapability

Figure 23. Maximum Continuous DrainCurrent vs. Case Temperature

Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum PowerDissipation

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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted

10−4 10−3 10−2 10−1 1 10 100 10000.0001

0.001

0.01

0.1

12

SINGLE PULSE

�JA = 120 oC/W

(Note 1d)

DUTY CYCLE−DESCENDING ORDERN

OR

MA

LIZ

ED

TH

ER

MA

LIM

PE

DA

NC

E,Z

�JA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

PDM

t1t2

NOTES:DUTY FACTOR: D = t 1/t 2PEAK TJ = PDM x Z�JA x R�JA + TA

Figure 26. Junction−to−Ambient Transient Thermal Response Curve

R

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TYPICAL CHARACTERISTICS (continued)

SyncFET Schottky Body Diode CharacteristicsON Semiconductor’s SyncFET process embeds a

Schottky diode in parallel with PowerTrench MOSFET.This diode exhibits similar characteristics to a discreteexternal Schottky diode in parallel with a MOSFET.

Figure 27 shows the reverses recovery characteristic of theFDMS001N025DSD.

Schottky barrier diodes exhibit significant leakage at hightemperature and high reverse voltage. This will increase thepower in the device.

Figure 27. FDMS3660S SyncFET Body DiodeReverse Recovery Characteristic

Figure 28. SyncFET Body Diode Reverse Leakagevs. Drain−Source Voltage

0 100 200 300 400−5

0

5

10

15

20

25

30

35

didt = 300 A/�s

CU

RR

EN

T (

A)

TIME (ns)

0 5 10 15 20 2510−6

10−5

10−4

10−3

10−2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I DS

S, R

EV

ER

SE

LE

AK

AG

E C

UR

RE

NT

(A)

VDS, REVERSE VOLTAGE (V)

Application Information

Switch Node Ringing SuppressionON Semiconductor’s Power Stage products incorporate a

proprietary design that minimizes the peak overshoot,ringing voltage on the switch node (PHASE) without theneed of any external snubbing components in a buck

converter. As shown in the Figure 29, the Power Stagesolution rings significantly less than competitor solutionsunder the same set of test conditions.

Figure 29. Power Stage Phase Node Rising Edge, High Side Turn On

Power Stage Device Competitors Solution

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Figure 30. Shows the Power Stage in a Buck Converter Topology

Recommended PCB Layout GuidelinesAs a PCB designer, it is necessary to address critical issues

in layout to minimize losses and optimize the performanceof the power train. Power Stage is a high power densitysolution and all high current flow paths, such as VIN (D1),

PHASE (S1/D2) and GND (S2), should be short and widefor better and stable current flow, heat radiation and systemperformance. A recommended layout procedure isdiscussed below to maximize the electrical and thermalperformance of the part.

Figure 31. Recommended PCB Layout

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Following is a guideline, not a requirement which thePCB designer should consider:

1. Input ceramic bypass capacitors C1 and C2 mustbe placed close to the D1 and S2 pins of PowerStage to help reduce parasitic inductance and highfrequency conduction loss induced by switchingoperation. C1 and C2 show the bypass capacitorsplaced close to the part between D1 and S2. Inputcapacitors should be connected in parallel close tothe part. Multiple input caps can be connecteddepending upon the application.

2. The PHASE copper trace serves two purposes; Inaddition to being the current path from the PowerStage package to the output inductor (L), it alsoserves as heat sink for the lower FET in the PowerStage package. The trace should be short and wideenough to present a low resistance path for thehigh current flow between the Power Stage and theinductor. This is done to minimize conductionlosses and limit temperature rise. Please note thatthe PHASE node is a high voltage and highfrequency switching node with high noisepotential. Care should be taken to minimizecoupling to adjacent traces. The reference layoutin Figure 31 shows a good balance between thethermal and electrical performance of PowerStage.

3. Output inductor location should be as close aspossible to the Power Stage device for lowerpower loss due to copper trace resistance. Ashorter and wider PHASE trace to the inductorreduces the conduction loss. Preferably the PowerStage should be directly in line (as shown inFigure 31) with the inductor for space savings andcompactness.

4. The PowerTrench Technology MOSFETs used inthe Power Stage are effective at minimizing phasenode ringing. It allows the part to operate well

within the breakdown voltage limits. Thiseliminates the need to have an external snubbercircuit in most cases. If the designer chooses to usean RC snubber, it should be placed close to thepart between the PHASE pad and S2 pins todampen the high−frequency ringing.

5. The driver IC should be placed close to the PowerStage part with the shortest possible paths for theHigh Side gate and Low Side gates through a widetrace connection. This eliminates the effect ofparasitic inductance and resistance between thedriver and the MOSFET and turns the devices onand off as efficiently as possible. Athigher−frequency operation this impedance canlimit the gate current trying to charge theMOSFET input capacitance. This will result inslower rise and fall times and additional switchinglosses. Power Stage has both the gate pins on thesame side of the package which allows for backmounting of the driver IC to the board. Thisprovides a very compact path for the drive signalsand improves efficiency of the part.

6. S2 pins should be connected to the GND planewith multiple vias for a low impedance grounding.Poor grounding can create a noise transient offsetvoltage level between S2 and driver ground. Thiscould lead to faulty operation of the gate driverand MOSFET.

7. Use multiple vias on each copper area tointerconnect top, inner and bottom layers to helpsmooth current flow and heat conduction. Viasshould be relatively large, around 8 mils to10 mils, and of reasonable inductance. Criticalhigh frequency components such as ceramicbypass caps should be located close to the part andon the same side of the PCB. If not feasible, theyshould be connected from the backside via anetwork of low inductance vias.

PowerTrench is a registered trademark of Semiconductor Components Industries, LLC (SCILLC)

PQFN8 5X6, 1.27P (SAWN TYPE)CASE 483AJ

ISSUE ADATE 08 FEB 2021

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON13659GDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2PQFN8 5X6, 1.27P

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

PQFN8 5X6, 1.27P (PUNCHED TYPE)CASE 483AJ

ISSUE ADATE 08 FEB 2021

(SCALE: 2X)

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SEATING PLANE

8XSEEDETAIL C

(SCALE: 2X)

BOTTOM VIEW

0.10 C

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z1

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON13659GDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2PQFN8 5X6, 1.27P

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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