Fast Switches

Switch Fabric Architecture Fast Datagram Switches Higher-Layer and Active Processing (From Kwangwoon Univ.)

Introduction

• The way of the determination and setting the path– Centralized control : single point control– Distributed control : per input port processing– Self-routing : autonomous control– Distributed control & Self-routing

• Advantage : don’t limit scalability• Disadvantage : difficult global optimization

• Blocking Characteristics– Strictly nonblocking– Wide-sense nonblocking : switching algorithm (set path)– Rearrangeably nonblocking : rearrange path– Virtually nonblocking : low probability of blocking

• Nonblocking Switch Fabric Principle : Avoid blocking by space-division parallelism, internal speedup, and internal pipelined buffering with cut-through

Buffering

• Why buffering?– If all traffic were uniform, buffering would not be needed.

– If traffic is bursty, however, buffering would be needed

because packets are to be dropped.

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Buffering

• Buffer Location– Unbuffered

• This way is undesirable for fast packet switches.(buffering)

• Optical components are suitable, because there is no way to queue.– Dealing with an optical burst switch

» Dropping burst and retransmitting end-to-end are enable.

» Burst be deflected by scheduling.

» Convert burst to the electronic domain for queueing.

– Internally buffered• Increases complexity

– Input or ouput queued

– Input AND ouput queued

– Shared buffer switch• A logical partitioning of physical memory

Buffering

• Buffer location– Unbuffered vs internally buffered

Buffering

• Buffer Location– Input or output buffered switches.

Buffering

• Buffer Location– Combined input/output buffered switch

Buffering

• Buffer Location– Shared buffer switch

Buffering

• Head-of-line blocking– Input queueing

• Input queueing holds packets until the switch is able to direct them to the appropriate output

– Output queueing• Shared medium network due to contention from other network nodes for M

AC

– Speedup (S) : the ratio of internal to external data rates

– Internal buffering

– Internal expansion : clos fabic

•Head-of-line blocking Avoidance principle

•Output queueing requires internal speedup, expansion, or buffering. Virtual output requires additional queues or queuing complexity. The two techniques must be traded against on another,and can be used in combination

Buffering

• Head-of-Line Blocking– Input vursus output queueing

Buffering

• Head-of-line blocking– Clos fabric

Buffering

• Virtual Output Queueing– This scheme requires that packets be multiplexed and timestamped todet

ermain the arrival orderamong the queues at each input

– A scheduling algorithm can be applied to determine which packets to accept to match a set of nonconflicting output

– Disadvantage• Waste of buffer space

– tradoff• Increase memory density for more queues practical

• Increased logic density makes more complex hardware

Buffering

• Virtual Output Queueing : – Head of line blocking can be eliminated

Single-Stage Shared Elements

• Bus Interconnects

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Single-Stage Shared Elements

• Bus Interconnects– Packet must wait in input queues until the bus is free

– Aggregate throughput : ri < w/nt (w:bandwidth, 1/nt:n port, bit rate)

– Bus speedup is limited by the available electronic technology

– Multicast

– Ring Switches

– Throughput can be higher due to better ring utilization of the MAC protocol and the isolation of electrical effects.

Single-Stage Shared Elements

• Shared Memory Fabrics

Shared memory

Output demultiplex

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MULTIPLEX

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Single-Stage Shared Elements

• Shared Memory Fabrics– Difficulties

• memory density is increaing exponentially, memory access time are not.• Packet must typically be completely read into memory before being output

– Multicast

Single-Stage Space Division Elements

• Basic Switch Element

– Electronic Switch Elements : 2 * 2 switch element

straight cross duplicate

Control

Packet buffer

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Cut-through

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Outputmultiplexor

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Single-Stage Space Division Elements

• Basic Switch Element– Electronic Switch Elements(2 * 2 Self-routing switch element)

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Single-Stage Space Division Elements

• Basic Switch Element– Optical Switch Elements

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Single-Stage Space Division Elements

• Crossbar

– Crossbar switch point states

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Optical MEMS

cross turn duplicate

Multistage Switches

• Crossbar– Advantage

• Simple and regularity

– Disadvantage• Scaling complexity(n2)

• Simple model of the cost in chip area– A=ac + n(ai + ao) + n2ax

Single-Stage Space Division Elements

• Crossbar– Crossbar switch

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Multistage Switches

• Tiling Crossbar– Tile switch elements in a square array

– This is not a cost effective solution for large switches

• Multistage Interconnection Networks(MINs)– Delta switch

• advantage– Elimination of central switch control(self-routing)

• Disadvantage– Preservation of packet sequence since cell has same path

– Load is not distributed

– Benes switch• Dinamically route packets with additional stages.

– Resequencing buffer by using a timestamp inserted into the internal switch header

– Banyan switch• Using shared memory and crossbar switchs.

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Multistage Switches

• Multistage Interconnection Networks – Delta switch

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Multistage Switches

• Multistage Interconnection Networks– Benes switch

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Multistage Switches

• Multistage Interconnection Networks– Banyan switch

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Multistage Switches

• Multistage Interconnection Networks– Optical Multistage Networks

• Incapable of buffering : nonblocking bufferless interconnection fabrics

• Crosstalk problem : dilation techniques

• Dilated Benes switch

Pass Cross

Multistage Switches

• Scaling Speed(parallel switch slices)

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FabricControl

Multicast Support

• Crossbar Switch Multicast– Service disciplines

• No fanout splitting : according to output blocking

• Fanout splitting

– The Goal of schedule servicing• Throughput is high

• Some fairness measure is met, in particular packets should not be starved

• The scheduling discipline can be implemented at high-speed(line rate)

– Variety of scheduling are possible• Concentrates residue among as few inputs as possible

• Weight based

Multicast Support

• Crossbar Switch Multicast scheduling

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Multicast Support

• Multistage Fabric Multicast

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Copy stages Routing stagesTranslate

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Review – Fast Packet SwitchingReview – Fast Packet Switching

• 80’s link rate technology improvement.• Connection-oriented fast packet switching technologies for

high speed networks.• 90’s widely deployed.

– ex. ATM for high-speed backbone networks

• Benefit (5.3)– Simplifying packet processing and forwarding.– Eliminating the store and forward latency.– Provide QoS quarantees, Resources reservation.

Fast Datagram SwitchesFast Datagram Switches

• Resisted the global deployment of CON.– IP-based Internet, WWW.

– shared medium link protocols were overcome

• Fast Datagram Switches– Motivation

• High Performance maintaining.

• Support Connectionless networks.

– Derivation• Complexity of Switch input and output processing

Fast Packet Switching ArchitectureFast Packet Switching Architecture

routing and s ignaling

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input processing output processing

linkschedulingC ID table

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label swap

Connection-Oriented Vs ConnectionlessConnection-Oriented Vs Connectionless

• Similarity– At a high-level, Each switch has the same functional block.– Ex. Routing, Signaling, Management…

• Difference– Input processing

• Address lookup using a prefix table.• Packet classification.

– Output processing• Packet scheduling to meet QoS requirement.

Architecture of Fast Datagram SwitchingArchitecture of Fast Datagram Switching

routing and s ignaling

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output processinginput processing

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Packet Processing RatesPacket Processing Rates

• Design a switch– Datagram size : Min 40Byte ~ Max 1500Byte.

– Rule of thumb : average packet size.

• Form of Processing– Sequentially processing for minimum packet size.

– Parallel processing for average packet size.

• Packet Processing Rate

The Packet processing rate is a key throughput measure of a switch. Packet processing software and shared parallel hardware resources must be able to sustain the average packet processing rate.

Fast Forwarding LookupFast Forwarding Lookup

• Review - Fast Packet Switching– CID for Fast Packet Switching.

– Problem : Table entry size.

• Fast Datagram Switching– Problem : similar to Fast Packet Switching.

– Solutions• Flat Addressing

• Hierarchical Address

• Software Prefix Matching

• Hardware Matching Support

• Source Routing

Flat AddressingFlat Addressing

adest pout

asrc adest payload payloadasrc adestpout

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softwaresearch

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Figure 5.50 Address lookup

Software SearchSoftware Search

• Lookup Time– Worst case : minimum packet size, worst-case lookup algorithm

• Memory Required– Trade Off( performance vs cost ).– Amount of memory reasonable to contain in the switch input proce

ssing.

• Update Time– Lookup data structure.

• Techniques– Tree search( O(logBN) for N entries, B is branch factor ).– Hash function( O(1) for no hash collisions ).

Content Addressable Memory(CAM)Content Addressable Memory(CAM)

• Feature– Parallel scan– Memory Access– Referencing One(by Key)– Return Associate Data

• Benefit– Initutive & speed

• Model

• Each word consists of a <search-field, return-field>.

• All words are checked in parallel in a single CAM cycle.

• Return-field portion of the word is the output of the CAM read.

• CAMs specifically designed for network address lookup.Key

Data

Association

Data

Hierarchical AddressesHierarchical Addresses

• Exploited to reduce the size of the forwarding tables.

• Forwarding entries can be represented as prefix addresses.

• Higher order bit portion of an address that must be matched to lead toward the destination.

• Similar to PSTN.

Software Prefix MatchingSoftware Prefix Matching

prefix pout fstate

pout 101 011 01 payloadpayload101 011 01

- hop countchecksum fix

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Figure 5.52 IP Prefix matching

Basic Prefix Matching Algorithm Basic Prefix Matching Algorithm

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Figure 5.53 Trie prefix matching

Hardware Matching SupportHardware Matching Support

• Motivation– Complexity of software algorithms.

• Hardware techniques for line rate lookup.– Assisting logic can be Embedded in the memory.

• CAMs for Variable Prefixes.– Translation logic can be provided that assists the location of addre

sses in conventional memory.• Multistage Lookup.

CAMs for Variable PrefixesCAMs for Variable Prefixes

prefix pout fstate

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- hop c ountc hec ksum fix

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prioritymux

Figure 5.54 Ternary C AM prefix matc hing

Multistage LookupMultistage Lookup

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Figure 5.55 Multistage prefix match

Source RoutingSource Routing

• Eliminate the per hop address lookup – By precomputing the route.

• Include the entire path in the packet header.

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Figure 5.56 Source routed label stack

Packet ClassificationPacket Classification

• Two other common forms – Separation of control packets.– Separation of packets belonging to different traffic classes.

• General classification include– Classification into a QoS traffic class.– Policy based routing.– Security.– Higher-layer switching functions.– Active networking.

Packet Filtering ProblemPacket Filtering Problem

• Classification occur before queueing in the node.

• General problem of classification.

TO S src adr payload

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Packet Classification ImplementsPacket Classification Implements

• Hardware Classification– Ternary CAMs can be used to match the rules in parallel.– Similar to the address lookup.

• Software Classification– Forwarding table lookup(section 5.1.1).– “Grid of tries”, “Tuple space search”.

• Preprocessing Classifiers– Preprocess all possible packet fields.

Output Processing and Packet Scheduling (1)Output Processing and Packet Scheduling (1)

• Reasons to perform output scheduling

– Datagrams are consist of• Quranteed Service classes.• Best Effort Traffic.

– Sufficient to meet delay and bandwidth bounds.– Fair service among the best-effort flows.

– Congestion control mechanisms does not protect quaranteed service classes from the best-effort traffic.

Output Processing and Packet Scheduling (2)Output Processing and Packet Scheduling (2)

• Fair Queuing– Packet Fair Queuing(PFQ).

– Weighted Fair Queuing(WFQ).

• Per-Flow Queuing– The highest degree of isolation.

– Control occurs when per flow queuing is used.

• Congestion Control– Large building queues increase delay, resulting in congestion.

– Discard to keep Queues from building.

– Ex. RED(Random early detection)

Higher-Layer and Active ProcessingHigher-Layer and Active Processing

• Active networking uses general classification techniques.– First, identify packets for active processing.

– Executes active applications in the network nodes on the identified packets, connections, or flows to provide the desired service.

• Motivation for “Active networking”– Open flexible interfaces to allow provisioning of new protocols and

services.

• Condition for “Active networking”– Should not impede the non-Active fast path.

Active Network Node Reference ModelActive Network Node Reference Model

MEE( Manage-- ment EE )

EEs ( Execution environments )

NodeO S

switch control

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Ac tiveProcessing

Figure 5.58 Ac tive network node reference model