Institute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, TaiwanVLSI Design Automation LABVLSI Design Automation LAB

Fast FlipFast Flip--Chip PinChip Pin--Out Designation Out Designation Respin by PinRespin by Pin--Block Design and Block Design and Floorplanning for PackageFloorplanning for Package--Board Board CodesignCodesign

Ren-Jie Lee, Ming-Fang Lai and Hung-Ming Chen

Department of Electronics Engineering and SoC Research Center

National Chiao Tung University, Hsinchu, Taiwanrjlee@vda.ee.nctu.edu.tw ,{terry,hmchen}@mail.nctu.edu.tw

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 2/26

2007/1/30

Outline

Introduction and MotivationIntroduction and Motivation

Proposed design flowProposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 3/26

2007/1/30

Introduction—Conventional Design Flow of Chip-Package-Board Codesign

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 4/26

2007/1/30

Motivation

To speed up turn around time of chipTo speed up turn around time of chip--packagepackage--board board codesigncodesign

To account for practical experience and To account for practical experience and techniques in automatically designing techniques in automatically designing interfaceinterface

To optimize package size To optimize package size

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 5/26

2007/1/30

Outline

Introduction and MotivationIntroduction and Motivation

Proposed design flowProposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 6/26

2007/1/30

Proposed Design Flow(Chip-Package-Board Codesign)

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 7/26

2007/1/30

Outline

Introduction and MotivationIntroduction and Motivation

Proposed design flowProposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 8/26

2007/1/30

33

41

2

1

3

4

2

IC Package

Constraints and Considerations (1/5)

A general layout of PCB board.

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛

=

loop current in inductance Equivalent switchingdrivers of Number

Noise Switchingeous Simultan

::

:

tot

SSN

totSSN

LNV

dtdINLV

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 9/26

2007/1/30

Constraints and Considerations (2/5)

Die-Package-PCB cross-section view

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 10/26

2007/1/30

Constraints and Considerations (3/5)

The routing pattern on PCB top layer (a) (b) and package bottom layer (c) (d).

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 11/26

2007/1/30

Constraints and Considerations (4/5)

The row number of signal-pin with different package size.(ball pitch=1.0mm, net width=5 mil, net spacing = 5 mil, for four layer PCB board).

Max. Avg. Max. Avg.37.5 x 37.5 36 x 36 9 8 7 6

35 x 35 34 x 34 9 8 7 631 x 31 30 x 30 9 8 7 627 x 27 26 x 26 9 8 7 6

… … 9 8 7 6

Package size (mm)(Width x Height)

Pin number (Rowx Column)

Row number of outer-pin(power-pin, ground-pin

and signal-pin)

Row number of outer-pin(signal-pin only)

(Top View)

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 12/26

2007/1/30

Constraints and Considerations (5/5)

capactance Mutual

capacitor mutualby induced Noise

:

:,

,

m

Cnoise

drivermCnoise

C

Idt

dVCI

m

m=

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

AD_N0

AD_P1

AD_N1

AD_P5

AD_N5

AD_P3

AD_N3

AD_P7

AD_N7

AD_P0

AD_N4

AD_P4

AD_N2

AD_P2

AD_N6

AD_P6

Return path pinShielding pin

I-I

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 13/26

2007/1/30

Outline

Introduction and MotivationIntroduction and Motivation

Proposed design flowProposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 14/26

2007/1/30

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

AD_N0

AD_P1

AD_N1

AD_P5

AD_N5

AD_P3

AD_N3

AD_P7

AD_N7

AD_P0

AD_N4

AD_P4

AD_N2

AD_P2

AD_N6

AD_P6

(1)

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

AD_N0

AD_P0

AD_N5

AD_P5

AD_N2

AD_P2

AD_N7

AD_P7

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS AD_P6AD_N6

AD_N4

AD_P4

AD_P3AD_N3

AD_N1

AD_P1

AD_P9AD_N9

AD_N8

AD_P8

(2)

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

AD_P2

AD_N2

AD_P6

AD_N6

AD_P3

AD_N3

AD_P7

AD_N7

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AD_P0AD_N0

AD_P4AD_N4

AD_P5AD_N5

AD_P1AD_N1

AD_P8AD_N8

AD_P9AD_N9

(3)

PinPin--Block Design and Block Design and FloorplanningFloorplanning (1/6)

Proposed pin pattern (1), (2), (3)

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 15/26

2007/1/30

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

AD14AD15

AD11

AD10

AD6

AD7

AD3

AD2

AD22AD23

AD19

AD18

AD0

AD1

AD8

AD9

AD12AD13

AD4

AD5

AD16AD17

AD20AD21

(5)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS AD14AD15

AD11

AD10

AD6

AD7

AD3

AD2

AD22AD23

AD19

AD18

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AD0

AD1

AD8

AD9

AD12AD13

AD4

AD5

AD16AD17

AD20AD21

(4)

TIN2

TIN3

VSS

VDD

TRAP6TRAP7

VSS

VDD

EN0

EN1

VSS

VDD

SEL2

SEL3

TRAP3

TRAP2

DB2

DB3

DB7

DB6

TIN7

TIN6

RST0

RST1

VDD

VSS

DB5

DB4

VDD

VSS

TRAP1

TRAP0

VDD

VSS

TIN9

TIN8

SEL0

SEL1

DB0

DB1

TIN0

TIN1

TRAP4TRAP5

TIN4

TIN5

RST2

RST3

(6)

PinPin--Block Design and Block Design and FloorplanningFloorplanning (2/6)

Proposed pin pattern (4), (5), (6)

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 16/26

2007/1/30

PinPin--Block Design and Block Design and FloorplanningFloorplanning (3/6)

Characteristics of signal-pin patterns.Applications, pin-designation efficiency, pin-to-pin crosstalk immunity, net balance, ..., etc.

Top layer Bottom layer Top layer Bottom layer Top layer Bottom layer

Pattern(1) Differential signal 16 Excellent Good Good Good Good Ground Ground Without Not good

Pattern(2)

Differencial signal /Single-ended signal 20 Good Good Good Good Not good Ground Ground Without Average

Pattern(3)

Differencial signal /Single-ended signal 20 Good Not good Good Good Good Ground Ground Without Average

Pattern(4)

Differencial signal /Single-ended signal 24 Excellent Not good Good Good Not good Ground Ground Without Good

Pattern(5)

Differencial signal /Single-ended signal 24 Excellent Not good Good Good Not good Power Ground With Good

Pattern(6) Single-ended signal 36 Not good Not good Not good Not good Not good None None With Excellent

ApplicationSignal-pin NO.

Pin-to-pincrosstalkimmunity

Net balance Signal shielding on packagesubstrate (Power/Ground)

Powerdelivaryaware

Pin-designationefficiency

PCB board Package substrate

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 17/26

2007/1/30

PinPin--Block Design and Block Design and FloorplanningFloorplanning (4/6)

An example of pin configuration chart and pin block.

Signal-pin name I/O buffertype

I/O width(um)

I/Oheight(um)

Selectedsignal-pin

pattern

Group Side Order Power-pinname

Power-pinNO.

AD_P[0:7] AIO1XH0J 40 500 1 1 1 1 VDDA 10AD_N[0:7] AIO1XH0J 40 500 1 1 1 1 VDDA 10

… … … … … … … … … …AD[0:15] BIO1XH0J 30 350 3 2 1 2 VDDB 8

… … … … … … … … … …TEST_IN[0:6] CIO1XH0J 25 400 4 3 2 1 VDDC 5TEST_OUT[0:6] CIO1XH0J 25 400 4 3 2 1 VDDC 5TRAP[0:6] CIO1XH1J 25 400 4 3 2 1 VDDC 5

… … … … … … … … … …

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 18/26

2007/1/30

PinPin--Block Design and Block Design and FloorplanningFloorplanning (5/6)

Package size optimizationE1 to E4 represent the width (height) of the excess or empty area in each side.

Floorplanning

A42

A32 A31

A22

A21

A11 A12

A33

A21

A31

A33

A41

Wmin

Hmin

A32 A31

A41

A42

A22

A21

A11 A12

A33

F

E1

E2

E4

E3

h1 w2

h21

h22

w31w32w33

h3

w11 w12

h41

h42

w4

(Side, Order)A11: (1, 1) A12: (1, 2) A21: (2, 1) A22: (2, 2) A31: (3, 1) A32: (3, 2) A33: (3, 3)A41: (4, 1) A42: (4, 2)

F

⎪⎩

⎪⎨

⎧

<=>

Empty Exact Excess

E,0,0,0

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 19/26

2007/1/30

PinPin--Block Design and Block Design and FloorplanningFloorplanning (6/6)

Problem formulation— to minimize package size

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 20/26

2007/1/30

Outline

Introduction and MotivationIntroduction and Motivation

Proposed design flowProposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 21/26

2007/1/30

Experimental Results (1/3)

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 22/26

2007/1/30

Experimental Results (2/3)Case (I):

(b) Automated pin-out designation.(c) Manual pin-out designation.

26 26 26

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 23/26

2007/1/30

Experimental Results (3/3)Case (II):

(e) Automated pin-out designation.(f) Manual pin-out designation.

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 24/26

2007/1/30

Outline

IntroductionIntroduction

Motivation and proposed design flowMotivation and proposed design flow

Constraints and ConsiderationsConstraints and Considerations

PinPin--Block Design and Block Design and FloorplanningFloorplanning

Experimental ResultsExperimental Results

ConclusionConclusion

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 25/26

2007/1/30

ConclusionWe have designed six signalWe have designed six signal--pin patterns pin patterns (template) for pin block construction in package (template) for pin block construction in package design.design.

We have proposed a near optimal approach to We have proposed a near optimal approach to minimize package size.minimize package size.

We automate this pinWe automate this pin--out designation process for out designation process for packagepackage--board codesign.board codesign.

VLSI Design Automation LABVLSI Design Automation LABInstitute of Electronics, National Institute of Electronics, National ChiaoChiao TungTung University, TaiwanUniversity, Taiwan R. J. LeeR. J. Lee 26/26

2007/1/30