F700_EMIF

1External Memory Interface and On-Chip XRAM Overview

In this section, we are going to cover the Silicon Labs C8051F700 family external memory interface.

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Agenda

C8051F700 Block Diagram

C8051F700 Device features

External memory interface and XRAM module and usage

Where to learn more

We are going to look at the new C8051F700 devices in this module. We will first take a look at the high level block diagram and then dive into the EMIF peripheral.

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Cost Optimized C8051F700

New patented capacitive touch sense True capacitance-to-digital converter Robust and responsive Easy to use

High Performance MCU 25 MHz 8051 CPU Best in class ADC 16 kB Flash 32 B data-EEPROM

54 multi-function GPIO User configured as digital or analog Digital Crossbar assigns pins Up to 32 capacitive touch sense inputs Available in TQFP64, TQFP48, and

QFN48 (7x7mm) packages

The new C8051F700 microcontroller family is a high pin count device enabling maximum flexibility while allowing customers to cost effectively add capacitive sensing. Here are a few highlights. The Silicon labs patented 32 input capacitance to digital converter (CDC) enables very accurate, responsive and very reliable capacitive touch sense capability. The MCU has a high performance core. A fast 25 MIPS CPU, best in class analog functions, such as the accurate 10 bit analog to digital converter with internal voltage reference. 2% calibrated internal precision oscillator. Up to 16Kbytes of in system programmable flash and 32 bytes of EEPROM with 100,000 cycle endurance guaranteed which helps to reduce overall system cost.

With Silicon Labs MCUs, you dont have to choose between SMBus, SPI or UART. All are included as independent functions. There is also the timers and PCA as well as the external memory interface. Finally, there are 54 general purpose I/O pins. You can configure most inputs to be analog inputs to the ADC, comparator or capacitance to digital converter via software and digital functions can be enabled through a priority encoded crossbar that provides complete flexibility in the choice of peripheral usage.

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C8051F700 Product Family Selection

24 unique part numbers Choice of Flash size Can select EEPROM (in larger Flash size, EEPROM is traded for 1 kB Flash) ADC or no-ADC Capacitive touch sense option

Part Number MIPS (peak)

FLASH Memory (bytes)

Data EEPROM

(bytes)

RAM (bytes)

Digital Port I/O

PinsSerial Buses Timers (16-bit)

PCA Chnls

Internal Osc

Cap Touch Sense

ADC0 Temp Sensor VREF Comp. Package

C8051F700-GQ 25 15kB 32 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP64C8051F701-GQ 25 15kB 32 512 54 UART, I2C, SPI 4 3 2% Y - 1 QFP64C8051F702-GQ 25 16kB - 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP64C8051F703-GQ 25 16kB - 512 54 UART, I2C, SPI 4 3 2% Y - 1 QFP64C8051F704-GQ 25 15kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48C8051F704-GM 25 15kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48C8051F705-GQ 25 15kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48C8051F705-GM 25 15kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48C8051F706-GQ 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48C8051F706-GM 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48C8051F707-GQ 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48C8051F707-GM 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48C8051F708-GQ 25 8kB 32 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP64C8051F709-GQ 25 8kB 32 512 54 UART, I2C, SPI 4 3 2% Y - 1 QFP64C8051F710-GQ 25 8kB - 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP64C8051F711-GQ 25 8kB - 512 54 UART, I2C, SPI 4 3 2% Y - 1 QFP64C8051F712-GQ 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48C8051F712-GM 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48C8051F713-GQ 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48C8051F713-GM 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48C8051F714-GQ 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48C8051F714-GM 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48C8051F715-GQ 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48C8051F715-GM 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48

5C8051F700 EMIF and XRAM

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External Data Memory (XRAM)

XRAM Additional on-chip memory mapped to the external data address

space (XRAM) Accessed using the MOVX instruction

64K XRAM Address Space

F700 ExampleF700 Example

The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which contains the effective address of the XRAM location to be read from or written to. The second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM address.

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Two Important Registers

Data pointer register (DPTR) Provides the full 16-bit external data memory address for the MOVX

command No paging using DPTR as the entire 64 K data memory space is

accessible

XRAM page select register (EMI0CN) Provides the high byte of the 16-bit external data memory address

when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.

Complete 16 bit address formed by using the R0 or R1 registers for the low byte of the address

EMI0CN contents get output to the upper address port pins when used for off-chip access

The main difference between these two registers is the bit width and how they are handled for the external memory control. The DPTR register is 16 bits and therefore covers the entire 64K address space. When using this register the complete address is loaded into DPTR. The EMI0CN register is 8 bits and holds the upper address byte used for memory accesses. R0 or R1 are used to generate the lower address bits. 256 bytes can be accessed using the EMI0CN before a change to the register is required.

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Accessing XRAM

Two methods for accessing XRAM Data pointer register (DPTR) Used for full 16 bit addressing

Compilers use this when the memory model is set to largeMemory space referred to as xdata

Indirect using the R0 or R1 registerSets up 256 byte pages using R0 or R1Compilers use this when the memory model is set to compactMemory space referred to as pdata

MOV DPTR, #1234 ;load DPTR with 16-bit address to read (0x1234)MOVX A, @DPTR ; load contents of 0x1234 into accumulator A

MOV EMI0CN, #12 ; load high byte of address into EMI0CNMOV R0, #34 ; load low byte of address into R0 (or R1)MOVX A, @R0 ; load contents of 0x1234 into accumulator A

The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register. The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately, the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains the lower 8-bits of DPTR. Using the DPTR method the entire memory space is available without managing separate pages.

The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A. Using the pdata space provides 256 address pages to access the entire memory.

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External Memory Interface

External memory interface (EMIF) provides access to external devices connected to port pins Can access off chip memories and memory mapped devices Can be multiplexed or non-multiplexed I/O pins are not driven when the bus is not active

I/O default pin states should be parked to a known bus configuration (i.e. all bits logic 1)

F700

EMIF

Address

Data

ControlFPGA SRAM

Example EMIF ApplicationExample EMIF Application

The External Memory Interface can be used to expand the peripheral set of the MCU itself or it can allow the MCU to become a companion device to an FPGA. It is not uncommon to find a parallel interfaces used in FPGA designs. They are easy to implement since they only need a parallel set of registers and the latch controls are supplied by the interface. Since the interface has 64 K addresses we can also attach other peripheral devices such as SRAM or even an LCD display.

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Configuring the EMIF

1. Configure the output modes of the associated port pins as either push-pull or open-drain (push-pull is most common)

2. Configure port latches to park the EMIF pins in a dormant state (usually by setting them to logic 1)

3. Select multiplexed mode or non-multiplexed mode

4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select or off-chip only)

5. Set up timing to interface with off-chip memory or peripherals

The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches for those pins. The Port latches should be explicitly configured to park the External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1.

During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be configured for push-pull mode.

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Digital Push-Pull I/O Pins

All port pins can be used for digital I/O Port pin configured as digital using PxMDIN register bits set to a 1 The output mode is selected to be push-pull using the PxMDOUT bits set to a 1

Push Pull: pin driven High111Push Pull: pin driven Low011Open drain high/Digital Input101Open drain low001DescriptionPxPxMDOUTPxMDIN

Park the I/O in a dormant state

Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external event trigger functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers. Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the output logic value of the Port pin.

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4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only)


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Multiplexed Memory Interface

Lower address byte and the data bus share the same port pins Reduces device pin count requirements

Address Latch Enable (ALE) signal used to latch the lower address bits

Register EMI0CF bit 4 (EMD2) set to 0

In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface logic. In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the states of the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.

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Non-Multiplexed Memory Interface

Address and data available on separate port pins Increases device pin count requirements

Address Latch Enable (ALE) signal not used Port pin can be used for other functions No external latch required

Register EMI0CF bit 4 (EMD2) set to 1

Example connection to external SRAMExample connection to external SRAM

In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. This reduces complexity at the expense of higher pin counts.

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EMIF Operating Modes (1 of 4)

Internal XRAM only EMI0CF[3:2] are set to 00

8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address

16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address

When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 4 kB boundaries. As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.

8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address.16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.

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Split mode without bank select EMI0CF[3:2] are set to 01

Effective addresses below the internal XRAM size boundary will access on-chip XRAM space

Effective addresses above the internal XRAM size boundary will access off-chip space

The 8-bit MOVX instruction will not drive the port pins with the value from the EMI0CN register

The 16-bit MOVX instruction will drive the port pins with the address

One of the biggest differences for this mode compared to others is how the port pins are controlled. In the 8 bit mode the port pins are not driven by the values stored in the EMI0CN register. The value is determined by the actual port pin values.

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Split mode with bank select EMI0CF[3:2] are set to 10

Effective addresses below the internal XRAM size boundary will access on-chip XRAM space

Effective addresses above the internal XRAM size boundary will access off-chip space

The 8-bit MOVX instruction will drive the port pins with the value from the EMI0CN register

The 16-bit MOVX instruction will drive the port pins with the address

When operating in the split mode with bank select the output pins for the upper address bits in the 8 bit mode are determined by the EMI0CN register.

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External only (off-chip only) EMI0CF[3:2] are set to 11

8-bit MOVX operations ignore the contents of EMI0CNUpper Address bits A[15:8] are not driven Upper address bits set via the Port state registers directlyThe lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1

16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address

When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the internal XRAM size boundary.

1) 8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identical behavior to an off-chip access in Split Mode without Bank Select described above). This allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.2) 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.

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EMIF Timing: EMI0TC Register

EMIF Operating Mode Select Bits.00: Internal Only 01: Split Mode without Bank Select 10: Split Mode with Bank Select11: External Only

EMD[1:0]3:2

ALE Pulse-Width Select BitsThese bits only have an effect when EMD2 = 0.00: ALE high and ALE low pulse width = 1 SYSCLK cycle01: ALE high and ALE low pulse width = 2 SYSCLK cycles10: ALE high and ALE low pulse width = 3 SYSCLK cycles11: ALE high and ALE low pulse width = 4 SYSCLK cycles

EALE[1:0]1:0

EMIF Multiplex Mode Select Bit0: EMIF operates in multiplexed address/data mode1: EMIF operates in non-multiplexed mode (separate address and data pins)

EMD24

UnusedRead = 000b; Write = Dont care

Unused7:5

FunctionNameBits

Here we see some of the key bits used to set up the external memory interface. The external interface is defined using the EMI0TC register. The EMD2 bit defines whether or not the bus interface is using the multiplexed mode or the non-multiplexed mode. The EMD bits set the access method and how the memory appears to the system, for example split mode with ban select.

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EMIF Timing

The EMIF timing can be configured to enable connection to devices having different setup and hold time requirements

Programmable timing in SYSCLK periods Address setup time Address hold time RD and WR strobe widths ALE pulse width in multiplexed mode

Non-multiplexed mode minimum write or read cycle time of 5 SYSCLK periods

Multiplexed mode minimum write or read cycle time of 7 SYSCLK periods

The timing of the EMIF is programmable in order to provide flexibility for connecting to a wide variety of peripherals. The EMIF should be configured to accommodate the timings required by the slowest device being attached to the bus. Consult the data sheet for the external devices to verify the proper bus speed configuration.

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EMIF Timing: EMI0TC Register

EMIF Address Hold Time00: Adress hold time = 0 SYSCLK cycles01: Address hold time = 1 SYSCLK cycle10: Address hold time = 2 SYSCLK cycles11: Address hold time = 3 SYSCLK cycles

EAH[1:0]1:0

EMIF WR and RD Pulse Width Control Bits0000: WR and RD pulse width = 1 SYSCLK cycles0001: WR and RD pulse width = 2 SYSCLK cycles0010: WR and RD pulse width = 3 SYSCLK cycles0011: WR and RD pulse width = 4 SYSCLK cycles

1111: WR and RD pulse width = 16 SYSCLK cycles

EWR[3:0]5:2

EMIF Address Setup Time00: Adress setup time = 0 SYSCLK cycles01: Address setup time = 1 SYSCLK cycle10: Address setup time = 2 SYSCLK cycles11: Address setup time = 3 SYSCLK cycles

EAS[1:0]7:6

FunctionNameBits

EMIF timing is defined in terms of SYSCLK cycles. Therefore, it is important to know the clock sources and the configuration registers required for selecting the internal clock that is driving the system clock. For example, the F700 operates from the internal precision oscillator out of reset and it is calibrated to 24.5MHz. That provides a minimum SYSCLK period of 39.4ns and gives a maximum read and write pulse width of about 630ns (39.4ns * 16).

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The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches for those pins. See Section 25. Port Input/Output on page 164 for more information about Port operation and configuration. The Port latches should be explicitly configured to park the External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1.

During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be configured for push-pull mode.

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EMIF Configuration Example

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